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mpc83xx: MVBLM7: minor build fixups
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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a1293e549b
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@ -29,44 +29,12 @@
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#endif
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#endif
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#include <pci.h>
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#include <pci.h>
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#include <mpc83xx.h>
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#include <mpc83xx.h>
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#include <fpga.h>
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#include "mvblm7.h"
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#include "mvblm7.h"
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#include "fpga.h"
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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/* System RAM mapped to PCI space */
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#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
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#define SLOT0_IRQ 3
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#define SLOT1_IRQ 4
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void pci_mvblm7_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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{
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unsigned char line = 0xff;
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if (PCI_BUS(dev) == 0) {
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switch (PCI_DEV(dev)) {
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case 0x0:
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return;
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case 0xb:
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line = 0;
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break;
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case 0xc:
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line = 1;
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break;
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default:
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printf("***pci_scan: illegal dev = 0x%08x\n",
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PCI_DEV(dev));
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line = 0xff;
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break;
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}
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
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}
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}
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static struct pci_controller pci_hose = {
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fixup_irq:pci_mvblm7_fixup_irq
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};
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int mvblm7_load_fpga(void)
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int mvblm7_load_fpga(void)
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{
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{
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size_t data_size = 0;
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size_t data_size = 0;
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@ -118,7 +118,7 @@
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
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#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
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#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
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OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS|\
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
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OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
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OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
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OR_GPCM_EAD)
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OR_GPCM_EAD)
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#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE
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#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE
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