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powerpc/8xxx: Add base support for the SEC4

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Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kim Phillips 2010-06-01 12:24:34 -05:00 committed by Kumar Gala
parent 929a213830
commit 22f292c7b2
3 changed files with 47 additions and 1 deletions
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6
arch/powerpc/cpu/mpc8xxx/fdt.c
View File

@ -183,4 +183,10 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
}
#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */
void fdt_fixup_crypto_node(void *blob, int sec_rev)
{
if (!sec_rev)
fdt_del_node_and_alias(blob, "crypto");
}
#endif

4
arch/powerpc/include/asm/config.h
View File

@ -69,7 +69,9 @@
/*
* SEC (crypto unit) major compatible version determination
*/
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
#if defined(CONFIG_FSL_CORENET)
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#endif

38
arch/powerpc/include/asm/immap_85xx.h
View File

@ -2045,6 +2045,41 @@ enum {
FSL_SRDS_B3_LANE_D = 23,
};
/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
typedef struct ccsr_sec {
u8 res1[0xfa0];
u32 crnr_ms; /* CHA Revision Number Register, MS */
u32 crnr_ls; /* CHA Revision Number Register, LS */
u32 ctpr_ms; /* Compile Time Parameters Register, MS */
#define SEC_CTPR_MS_AXI_LIODN 0x08000000
#define SEC_CTPR_MS_QI 0x02000000
u32 ctpr_ls; /* Compile Time Parameters Register, LS */
u8 res2[0x10];
u32 far_ms; /* Fault Address Register, MS */
u32 far_ls; /* Fault Address Register, LS */
u32 falr; /* Fault Address LIODN Register */
u32 fadr; /* Fault Address Detail Register */
u8 res3[0x4];
u32 csta; /* CAAM Status Register */
u8 res4[0x8];
u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
#define SEC_RVID_MA 0x0f000000
u32 ccbvid; /* CHA Cluster Block Version ID Register */
u32 chavid_ms; /* CHA Version ID Register, MS */
u32 chavid_ls; /* CHA Version ID Register, LS */
u32 chanum_ms; /* CHA Number Register, MS */
#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000
#define SEC_CHANUM_MS_JQNUM_SHIFT 28
#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
#define SEC_CHANUM_MS_DECONUM_SHIFT 24
u32 chanum_ls; /* CHA Number Register, LS */
u32 caamvid_ms; /* CAAM Version ID Register, MS */
u32 caamvid_ls; /* CAAM Version ID Register, LS */
u8 res5[0xf000];
} ccsr_sec_t;
#endif
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
@ -2059,6 +2094,7 @@ enum {
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
#define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */
@ -2143,6 +2179,8 @@ enum {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
#define CONFIG_SYS_MPC85xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)