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Prepare v2024.070-rc4

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Merge tag 'v2024.07-rc4' into next

Prepare v2024.070-rc4
This commit is contained in:
Tom Rini 2024-06-03 18:42:11 -06:00
commit 227be29df3
106 changed files with 884 additions and 8067 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
.mailmap
View File

@ -42,6 +42,7 @@ Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com>
Fabio Estevam <fabio.estevam@nxp.com>
Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com>
Heiko Stuebner <heiko.stuebner@cherry.de> <heiko.stuebner@theobroma-systems.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> <ibai.erkiaga-elorza@xilinx.com>
@ -53,12 +54,14 @@ Jagan Teki <jaganna@gmail.com>
Jagan Teki <jaganna@xilinx.com>
Jagan Teki <jagannadh.teki@gmail.com>
Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de> <jakob.unterwurzacher@theobroma-systems.com>
Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com>
Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
John Linn <john.linn@amd.com> <john.linn@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com>
Klaus Goger <klaus.goger@cherry.de> <klaus.goger@theobroma-systems.com>
Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org>
Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com>
Lukasz Majewski <lukma@denx.de>
@ -88,9 +91,11 @@ This contributor prefers not to receive mails <noreply@example.com> <pali.rohar@
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
Philipp Tomsich <philipp.tomsich@vrull.eu> <philipp.tomsich@theobroma-systems.com>
Piyush Mehta <piyush.mehta@amd.com> <piyush.mehta@xilinx.com>
Prabhakar Kushwaha <prabhakar@freescale.com>
Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@amd.com> <punnaiah.choudary.kalluri@xilinx.com>
Quentin Schulz <quentin.schulz@cherry.de> <quentin.schulz@theobroma-systems.com>
Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> <radhey.shyam.pandey@xilinx.com>
Rajeshwari Shinde <rajeshwari.s@samsung.com>
Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com> <raju.kumar-pothuraju@xilinx.com>

7
MAINTAINERS
View File

@ -579,19 +579,14 @@ F: drivers/clk/exynos/clk.h
ARM SAMSUNG EXYNOS850 SOC
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: arch/arm/dts/exynos850-pinctrl.dtsi
F: arch/arm/dts/exynos850.dtsi
F: doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
F: drivers/clk/exynos/clk-exynos850.c
F: drivers/pinctrl/exynos/pinctrl-exynos850.c
F: include/dt-bindings/clock/exynos850.h
ARM SAMSUNG SOC DRIVERS
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: doc/device-tree-bindings/soc/samsung/*
F: doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
F: drivers/soc/samsung/*
F: include/dt-bindings/soc/samsung,*.h
ARM SANCLOUD
M: Paul Barker <paul.barker@sancloud.com>

2
Makefile
View File

@ -3,7 +3,7 @@
VERSION = 2024
PATCHLEVEL = 07
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*

7
arch/arm/dts/Makefile
View File

@ -31,7 +31,6 @@ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_E850_96) += exynos850-e850-96.dtb
dtb-$(CONFIG_ARCH_APPLE) += \
t8103-j274.dtb \
@ -97,9 +96,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
dtb-$(CONFIG_ROCKCHIP_RV1126) += \
rv1126-edgeble-neu2-io.dtb
dtb-$(CONFIG_ARCH_S5P4418) += \
s5p4418-nanopi2.dtb
@ -1024,9 +1020,6 @@ dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \
dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb
dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
omap3-igep0020.dtb
dtb-$(CONFIG_TARGET_OMAP4_PANDA) += \
omap4-panda.dtb \
omap4-panda-es.dtb

28
arch/arm/dts/exynos850-e850-96-u-boot.dtsi
View File

@ -3,35 +3,7 @@
* Copyright (c) 2023 Linaro Ltd.
*/
&cmu_top {
bootph-all;
};
&cmu_peri {
bootph-all;
};
&oscclk {
bootph-all;
};
&pinctrl_alive {
bootph-all;
};
&pmu_system_controller {
bootph-all;
samsung,uart-debug-1;
};
&serial_0 {
bootph-all;
};
&uart1_pins {
bootph-all;
};
&usi_uart {
bootph-all;
};

273
arch/arm/dts/exynos850-e850-96.dts
View File

@ -1,273 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* WinLink E850-96 board device tree source
*
* Copyright (C) 2018 Samsung Electronics Co., Ltd.
* Copyright (C) 2021 Linaro Ltd.
*
* Device tree source file for WinLink's E850-96 board which is based on
* Samsung Exynos850 SoC.
*/
/dts-v1/;
#include "exynos850.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "WinLink E850-96 board";
compatible = "winlink,e850-96", "samsung,exynos850";
aliases {
mmc0 = &mmc_0;
serial0 = &serial_0;
};
chosen {
stdout-path = &serial_0;
};
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
label = "micro-USB";
type = "micro";
vbus-supply = <&reg_usb_host_vbus>;
id-gpios = <&gpa0 0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&micro_usb_det_pins>;
port {
usb_dr_connector: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
/*
* RAM: 4 GiB (eMCP):
* - 2 GiB at 0x80000000
* - 2 GiB at 0x880000000
*
* 0xbab00000..0xbfffffff: secure memory (85 MiB).
*/
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x3ab00000>,
<0x0 0xc0000000 0x40000000>,
<0x8 0x80000000 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_voldown_pins &key_volup_pins>;
volume-down-key {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
gpios = <&gpa1 0 GPIO_ACTIVE_LOW>;
};
volume-up-key {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&gpa0 7 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
/* HEART_BEAT_LED */
user_led1: led-1 {
label = "yellow:user1";
gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_HEARTBEAT;
linux,default-trigger = "heartbeat";
};
/* eMMC_LED */
user_led2: led-2 {
label = "yellow:user2";
gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_YELLOW>;
linux,default-trigger = "mmc0";
};
/* SD_LED */
user_led3: led-3 {
label = "white:user3";
gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_SD;
linux,default-trigger = "mmc2";
};
/* WIFI_LED */
wlan_active_led: led-4 {
label = "yellow:wlan";
gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_WLAN;
linux,default-trigger = "phy0tx";
default-state = "off";
};
/* BLUETOOTH_LED */
bt_active_led: led-5 {
label = "blue:bt";
gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_BLUETOOTH;
linux,default-trigger = "hci0-power";
default-state = "off";
};
};
/* TODO: Remove this once PMIC is implemented */
reg_dummy: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "dummy_reg";
};
reg_usb_host_vbus: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "usb_host_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpa3 5 GPIO_ACTIVE_LOW>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <1>;
ranges;
ramoops@f0000000 {
compatible = "ramoops";
reg = <0x0 0xf0000000 0x200000>;
record-size = <0x20000>;
console-size = <0x20000>;
ftrace-size = <0x100000>;
pmsg-size = <0x20000>;
};
};
/*
* RTC clock (XrtcXTI); external, must be 32.768 kHz.
*
* TODO: Remove this once RTC clock is implemented properly as part of
* PMIC driver.
*/
rtcclk: clock-rtcclk {
compatible = "fixed-clock";
clock-output-names = "rtcclk";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&cmu_hsi {
clocks = <&oscclk>, <&rtcclk>,
<&cmu_top CLK_DOUT_HSI_BUS>,
<&cmu_top CLK_DOUT_HSI_MMC_CARD>,
<&cmu_top CLK_DOUT_HSI_USB20DRD>;
clock-names = "oscclk", "rtcclk", "dout_hsi_bus",
"dout_hsi_mmc_card", "dout_hsi_usb20drd";
};
&mmc_0 {
status = "okay";
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cap-mmc-highspeed;
non-removable;
mmc-hs400-enhanced-strobe;
card-detect-delay = <200>;
clock-frequency = <800000000>;
bus-width = <8>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <2 4>;
samsung,dw-mshc-hs400-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins
&sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>;
};
&oscclk {
clock-frequency = <26000000>;
};
&pinctrl_alive {
key_voldown_pins: key-voldown-pins {
samsung,pins = "gpa1-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
key_volup_pins: key-volup-pins {
samsung,pins = "gpa0-7";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
micro_usb_det_pins: micro-usb-det-pins {
samsung,pins = "gpa0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
};
&rtc {
status = "okay";
clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>;
clock-names = "rtc", "rtc_src";
};
&serial_0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
};
&usbdrd {
status = "okay";
vdd10-supply = <&reg_dummy>;
vdd33-supply = <&reg_dummy>;
};
&usbdrd_dwc3 {
dr_mode = "otg";
usb-role-switch;
role-switch-default-mode = "host";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&usb_dr_connector>;
};
};
};
&usbdrd_phy {
status = "okay";
};
&usi_uart {
samsung,clkreq-on; /* needed for UART mode */
status = "okay";
};
&watchdog_cl0 {
status = "okay";
};
&watchdog_cl1 {
status = "okay";
};

663
arch/arm/dts/exynos850-pinctrl.dtsi
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@ -1,663 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's Exynos850 SoC pin-mux and pin-config device tree source
*
* Copyright (C) 2017 Samsung Electronics Co., Ltd.
* Copyright (C) 2021 Linaro Ltd.
*
* Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
* tree nodes in this file.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "exynos-pinctrl.h"
&pinctrl_alive {
gpa0: gpa0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
};
gpa1: gpa1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
};
gpa2: gpa2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
};
gpa3: gpa3-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
gpa4: gpa4-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
};
gpq0: gpq0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* I2C5 (also called CAM_PMIC_I2C in TRM) */
i2c5_pins: i2c5-pins {
samsung,pins = "gpa3-5", "gpa3-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* I2C6 (also called MOTOR_I2C in TRM) */
i2c6_pins: i2c6-pins {
samsung,pins = "gpa3-7", "gpa4-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI: UART_DEBUG_0 pins */
uart0_pins: uart0-pins {
samsung,pins = "gpq0-0", "gpq0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
/* USI: UART_DEBUG_1 pins */
uart1_pins: uart1-pins {
samsung,pins = "gpa3-7", "gpa4-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
};
&pinctrl_cmgp {
gpm0: gpm0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
};
gpm1: gpm1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
};
gpm2: gpm2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
gpm3: gpm3-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
gpm4: gpm4-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
};
gpm5: gpm5-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
};
gpm6: gpm6-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
};
gpm7: gpm7-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
};
/* USI_CMGP0: HSI2C function */
hsi2c3_pins: hsi2c3-pins {
samsung,pins = "gpm0-0", "gpm1-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI_CMGP0: UART function (4 pins, Auto Flow Control) */
uart1_single_pins: uart1-single-pins {
samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
/* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */
uart1_dual_pins: uart1-dual-pins {
samsung,pins = "gpm0-0", "gpm1-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
/* USI_CMGP0: SPI function */
spi1_pins: spi1-pins {
samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI_CMGP1: HSI2C function */
hsi2c4_pins: hsi2c4-pins {
samsung,pins = "gpm4-0", "gpm5-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI_CMGP1: UART function (4 pins, Auto Flow Control) */
uart2_single_pins: uart2-single-pins {
samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
/* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */
uart2_dual_pins: uart2-dual-pins {
samsung,pins = "gpm4-0", "gpm5-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
/* USI_CMGP1: SPI function */
spi2_pins: spi2-pins {
samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
};
&pinctrl_aud {
gpb0: gpb0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb1: gpb1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
aud_codec_mclk_pins: aud-codec-mclk-pins {
samsung,pins = "gpb0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins {
samsung,pins = "gpb0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_i2s0_pins: aud-i2s0-pins {
samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_i2s0_idle_pins: aud-i2s0-idle-pins {
samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_i2s1_pins: aud-i2s1-pins {
samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_i2s1_idle_pins: aud-i2s1-idle-pins {
samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_fm_pins: aud-fm-pins {
samsung,pins = "gpb1-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_fm_idle_pins: aud-fm-idle-pins {
samsung,pins = "gpb1-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
};
&pinctrl_hsi {
gpf2: gpf2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sd2_clk_pins: sd2-clk-pins {
samsung,pins = "gpf2-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
};
sd2_cmd_pins: sd2-cmd-pins {
samsung,pins = "gpf2-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
};
sd2_bus1_pins: sd2-bus1-pins {
samsung,pins = "gpf2-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
};
sd2_bus4_pins: sd2-bus4-pins {
samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
};
sd2_pdn_pins: sd2-pdn-pins {
samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
"gpf2-4", "gpf2-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
};
&pinctrl_core {
gpf0: gpf0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf1: gpf1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sd0_clk_pins: sd0-clk-pins {
samsung,pins = "gpf0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd0_cmd_pins: sd0-cmd-pins {
samsung,pins = "gpf0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd0_rdqs_pins: sd0-rdqs-pins {
samsung,pins = "gpf0-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd0_nreset_pins: sd0-nreset-pins {
samsung,pins = "gpf0-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd0_bus1_pins: sd0-bus1-pins {
samsung,pins = "gpf1-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd0_bus4_pins: sd0-bus4-pins {
samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd0_bus8_pins: sd0-bus8-pins {
samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
};
&pinctrl_peri {
gpc0: gpc0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc1: gpc1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg0: gpg0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg1: gpg1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg2: gpg2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg3: gpg3-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpp0: gpp0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpp1: gpp1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpp2: gpp2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sensor_mclk0_in_pins: sensor-mclk0-in-pins {
samsung,pins = "gpc0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk0_out_pins: sensor-mclk0-out-pins {
samsung,pins = "gpc0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk0_fn_pins: sensor-mclk0-fn-pins {
samsung,pins = "gpc0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk1_in_pins: sensor-mclk1-in-pins {
samsung,pins = "gpc0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk1_out_pins: sensor-mclk1-out-pins {
samsung,pins = "gpc0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk1_fn_pins: sensor-mclk1-fn-pins {
samsung,pins = "gpc0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk2_in_pins: sensor-mclk2-in-pins {
samsung,pins = "gpc0-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk2_out_pins: sensor-mclk2-out-pins {
samsung,pins = "gpc0-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk2_fn_pins: sensor-mclk2-fn-pins {
samsung,pins = "gpc0-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
/* USI: HSI2C0 */
hsi2c0_pins: hsi2c0-pins {
samsung,pins = "gpc1-0", "gpc1-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI: HSI2C1 */
hsi2c1_pins: hsi2c1-pins {
samsung,pins = "gpc1-2", "gpc1-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI: HSI2C2 */
hsi2c2_pins: hsi2c2-pins {
samsung,pins = "gpc1-4", "gpc1-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI: SPI */
spi0_pins: spi0-pins {
samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
i2c0_pins: i2c0-pins {
samsung,pins = "gpp0-0", "gpp0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
i2c1_pins: i2c1-pins {
samsung,pins = "gpp0-2", "gpp0-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
i2c2_pins: i2c2-pins {
samsung,pins = "gpp0-4", "gpp0-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
i2c3_pins: i2c3-pins {
samsung,pins = "gpp1-0", "gpp1-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
i2c4_pins: i2c4-pins {
samsung,pins = "gpp1-2", "gpp1-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
xclkout_pins: xclkout-pins {
samsung,pins = "gpq0-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
};

809
arch/arm/dts/exynos850.dtsi
View File

@ -1,809 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung Exynos850 SoC device tree source
*
* Copyright (C) 2018 Samsung Electronics Co., Ltd.
* Copyright (C) 2021 Linaro Ltd.
*
* Samsung Exynos850 SoC device nodes are listed in this file.
* Exynos850 based board files can include this file and provide
* values for board specific bindings.
*/
#include <dt-bindings/clock/exynos850.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/samsung,exynos-usi.h>
/ {
/* Also known under engineering name Exynos3830 */
compatible = "samsung,exynos850";
#address-cells = <2>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
pinctrl0 = &pinctrl_alive;
pinctrl1 = &pinctrl_cmgp;
pinctrl2 = &pinctrl_aud;
pinctrl3 = &pinctrl_hsi;
pinctrl4 = &pinctrl_core;
pinctrl5 = &pinctrl_peri;
};
arm-pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
/* Main system clock (XTCXO); external, must be 26 MHz */
oscclk: clock-oscclk {
compatible = "fixed-clock";
clock-output-names = "oscclk";
#clock-cells = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x3>;
enable-method = "psci";
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x101>;
enable-method = "psci";
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x102>;
enable-method = "psci";
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x103>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
/* Hypervisor Virtual Timer interrupt is not wired to GIC */
interrupts =
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x20000000>;
chipid@10000000 {
compatible = "samsung,exynos850-chipid";
reg = <0x10000000 0x100>;
};
timer@10040000 {
compatible = "samsung,exynos850-mct",
"samsung,exynos4210-mct";
reg = <0x10040000 0x800>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>;
clock-names = "fin_pll", "mct";
};
gic: interrupt-controller@12a01000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x12a01000 0x1000>,
<0x12a02000 0x2000>,
<0x12a04000 0x2000>,
<0x12a06000 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_HIGH)>;
};
pmu_system_controller: system-controller@11860000 {
compatible = "samsung,exynos850-pmu", "syscon";
reg = <0x11860000 0x10000>;
reboot: syscon-reboot {
compatible = "syscon-reboot";
regmap = <&pmu_system_controller>;
offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
mask = <0x2>; /* SWRESET_SYSTEM */
value = <0x2>; /* reset value */
};
};
watchdog_cl0: watchdog@10050000 {
compatible = "samsung,exynos850-wdt";
reg = <0x10050000 0x100>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;
clock-names = "watchdog", "watchdog_src";
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,cluster-index = <0>;
status = "disabled";
};
watchdog_cl1: watchdog@10060000 {
compatible = "samsung,exynos850-wdt";
reg = <0x10060000 0x100>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>;
clock-names = "watchdog", "watchdog_src";
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,cluster-index = <1>;
status = "disabled";
};
cmu_peri: clock-controller@10030000 {
compatible = "samsung,exynos850-cmu-peri";
reg = <0x10030000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
<&cmu_top CLK_DOUT_PERI_UART>,
<&cmu_top CLK_DOUT_PERI_IP>;
clock-names = "oscclk", "dout_peri_bus",
"dout_peri_uart", "dout_peri_ip";
};
cmu_g3d: clock-controller@11400000 {
compatible = "samsung,exynos850-cmu-g3d";
reg = <0x11400000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
clock-names = "oscclk", "dout_g3d_switch";
};
cmu_apm: clock-controller@11800000 {
compatible = "samsung,exynos850-cmu-apm";
reg = <0x11800000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
clock-names = "oscclk", "dout_clkcmu_apm_bus";
};
cmu_cmgp: clock-controller@11c00000 {
compatible = "samsung,exynos850-cmu-cmgp";
reg = <0x11c00000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>;
clock-names = "oscclk", "gout_clkcmu_cmgp_bus";
};
cmu_core: clock-controller@12000000 {
compatible = "samsung,exynos850-cmu-core";
reg = <0x12000000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
<&cmu_top CLK_DOUT_CORE_CCI>,
<&cmu_top CLK_DOUT_CORE_MMC_EMBD>,
<&cmu_top CLK_DOUT_CORE_SSS>;
clock-names = "oscclk", "dout_core_bus",
"dout_core_cci", "dout_core_mmc_embd",
"dout_core_sss";
};
cmu_top: clock-controller@120e0000 {
compatible = "samsung,exynos850-cmu-top";
reg = <0x120e0000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>;
clock-names = "oscclk";
};
cmu_mfcmscl: clock-controller@12c00000 {
compatible = "samsung,exynos850-cmu-mfcmscl";
reg = <0x12c00000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_MFCMSCL_MFC>,
<&cmu_top CLK_DOUT_MFCMSCL_M2M>,
<&cmu_top CLK_DOUT_MFCMSCL_MCSC>,
<&cmu_top CLK_DOUT_MFCMSCL_JPEG>;
clock-names = "oscclk", "dout_mfcmscl_mfc",
"dout_mfcmscl_m2m", "dout_mfcmscl_mcsc",
"dout_mfcmscl_jpeg";
};
cmu_dpu: clock-controller@13000000 {
compatible = "samsung,exynos850-cmu-dpu";
reg = <0x13000000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>;
clock-names = "oscclk", "dout_dpu";
};
cmu_hsi: clock-controller@13400000 {
compatible = "samsung,exynos850-cmu-hsi";
reg = <0x13400000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_HSI_BUS>,
<&cmu_top CLK_DOUT_HSI_MMC_CARD>,
<&cmu_top CLK_DOUT_HSI_USB20DRD>;
clock-names = "oscclk", "dout_hsi_bus",
"dout_hsi_mmc_card", "dout_hsi_usb20drd";
};
cmu_is: clock-controller@14500000 {
compatible = "samsung,exynos850-cmu-is";
reg = <0x14500000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_IS_BUS>,
<&cmu_top CLK_DOUT_IS_ITP>,
<&cmu_top CLK_DOUT_IS_VRA>,
<&cmu_top CLK_DOUT_IS_GDC>;
clock-names = "oscclk", "dout_is_bus", "dout_is_itp",
"dout_is_vra", "dout_is_gdc";
};
cmu_aud: clock-controller@14a00000 {
compatible = "samsung,exynos850-cmu-aud";
reg = <0x14a00000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>;
clock-names = "oscclk", "dout_aud";
};
pinctrl_alive: pinctrl@11850000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x11850000 0x1000>;
wakeup-interrupt-controller {
compatible = "samsung,exynos850-wakeup-eint";
};
};
pinctrl_cmgp: pinctrl@11c30000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x11c30000 0x1000>;
wakeup-interrupt-controller {
compatible = "samsung,exynos850-wakeup-eint";
};
};
pinctrl_core: pinctrl@12070000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x12070000 0x1000>;
interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_hsi: pinctrl@13430000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x13430000 0x1000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_peri: pinctrl@139b0000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x139b0000 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_aud: pinctrl@14a60000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x14a60000 0x1000>;
};
rtc: rtc@11a30000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x11a30000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>;
clock-names = "rtc";
status = "disabled";
};
mmc_0: mmc@12100000 {
compatible = "samsung,exynos7-dw-mshc-smu";
reg = <0x12100000 0x2000>;
interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>,
<&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
i2c_0: i2c@13830000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13830000 0x100>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
clock-names = "i2c";
status = "disabled";
};
i2c_1: i2c@13840000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13840000 0x100>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
clock-names = "i2c";
status = "disabled";
};
i2c_2: i2c@13850000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13850000 0x100>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
clock-names = "i2c";
status = "disabled";
};
i2c_3: i2c@13860000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
clock-names = "i2c";
status = "disabled";
};
i2c_4: i2c@13870000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
clock-names = "i2c";
status = "disabled";
};
/* I2C_5 (also called CAM_PMIC_I2C in TRM) */
i2c_5: i2c@13880000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
clock-names = "i2c";
status = "disabled";
};
/* I2C_6 (also called MOTOR_I2C in TRM) */
i2c_6: i2c@13890000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
clock-names = "i2c";
status = "disabled";
};
sysmmu_mfcmscl: sysmmu@12c50000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12c50000 0x9000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu";
clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>;
#iommu-cells = <0>;
};
sysmmu_dpu: sysmmu@130c0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x130c0000 0x9000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu";
clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>;
#iommu-cells = <0>;
};
sysmmu_is0: sysmmu@14550000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14550000 0x9000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu";
clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>;
#iommu-cells = <0>;
};
sysmmu_is1: sysmmu@14570000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14570000 0x9000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu";
clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>;
#iommu-cells = <0>;
};
sysmmu_aud: sysmmu@14850000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14850000 0x9000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu";
clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>;
#iommu-cells = <0>;
};
sysreg_peri: syscon@10020000 {
compatible = "samsung,exynos850-peri-sysreg",
"samsung,exynos850-sysreg", "syscon";
reg = <0x10020000 0x10000>;
clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>;
};
sysreg_cmgp: syscon@11c20000 {
compatible = "samsung,exynos850-cmgp-sysreg",
"samsung,exynos850-sysreg", "syscon";
reg = <0x11c20000 0x10000>;
clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
};
usbdrd: usb@13600000 {
compatible = "samsung,exynos850-dwusb3";
ranges = <0x0 0x13600000 0x10000>;
clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>,
<&cmu_hsi CLK_GOUT_USB_REF_CLK>;
clock-names = "bus_early", "ref";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
usbdrd_dwc3: usb@0 {
compatible = "snps,dwc3";
reg = <0x0 0x10000>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy 0>;
phy-names = "usb2-phy";
};
};
usbdrd_phy: phy@135d0000 {
compatible = "samsung,exynos850-usbdrd-phy";
reg = <0x135d0000 0x100>;
clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>,
<&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
status = "disabled";
};
usi_uart: usi@138200c0 {
compatible = "samsung,exynos850-usi";
reg = <0x138200c0 0x20>;
samsung,sysreg = <&sysreg_peri 0x1010>;
samsung,mode = <USI_V2_UART>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
<&cmu_peri CLK_GOUT_UART_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
serial_0: serial@13820000 {
compatible = "samsung,exynos850-uart";
reg = <0x13820000 0xc0>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
<&cmu_peri CLK_GOUT_UART_IPCLK>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
};
usi_hsi2c_0: usi@138a00c0 {
compatible = "samsung,exynos850-usi";
reg = <0x138a00c0 0x20>;
samsung,sysreg = <&sysreg_peri 0x1020>;
samsung,mode = <USI_V2_I2C>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>,
<&cmu_peri CLK_GOUT_HSI2C0_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
hsi2c_0: i2c@138a0000 {
compatible = "samsung,exynosautov9-hsi2c";
reg = <0x138a0000 0xc0>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c0_pins>;
clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>,
<&cmu_peri CLK_GOUT_HSI2C0_PCLK>;
clock-names = "hsi2c", "hsi2c_pclk";
status = "disabled";
};
};
usi_hsi2c_1: usi@138b00c0 {
compatible = "samsung,exynos850-usi";
reg = <0x138b00c0 0x20>;
samsung,sysreg = <&sysreg_peri 0x1030>;
samsung,mode = <USI_V2_I2C>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>,
<&cmu_peri CLK_GOUT_HSI2C1_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
hsi2c_1: i2c@138b0000 {
compatible = "samsung,exynosautov9-hsi2c";
reg = <0x138b0000 0xc0>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c1_pins>;
clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>,
<&cmu_peri CLK_GOUT_HSI2C1_PCLK>;
clock-names = "hsi2c", "hsi2c_pclk";
status = "disabled";
};
};
usi_hsi2c_2: usi@138c00c0 {
compatible = "samsung,exynos850-usi";
reg = <0x138c00c0 0x20>;
samsung,sysreg = <&sysreg_peri 0x1040>;
samsung,mode = <USI_V2_I2C>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>,
<&cmu_peri CLK_GOUT_HSI2C2_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
hsi2c_2: i2c@138c0000 {
compatible = "samsung,exynosautov9-hsi2c";
reg = <0x138c0000 0xc0>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c2_pins>;
clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>,
<&cmu_peri CLK_GOUT_HSI2C2_PCLK>;
clock-names = "hsi2c", "hsi2c_pclk";
status = "disabled";
};
};
usi_spi_0: usi@139400c0 {
compatible = "samsung,exynos850-usi";
reg = <0x139400c0 0x20>;
samsung,sysreg = <&sysreg_peri 0x1050>;
samsung,mode = <USI_V2_SPI>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
<&cmu_peri CLK_GOUT_SPI0_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
};
usi_cmgp0: usi@11d000c0 {
compatible = "samsung,exynos850-usi";
reg = <0x11d000c0 0x20>;
samsung,sysreg = <&sysreg_cmgp 0x2000>;
samsung,mode = <USI_V2_I2C>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
<&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
hsi2c_3: i2c@11d00000 {
compatible = "samsung,exynosautov9-hsi2c";
reg = <0x11d00000 0xc0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c3_pins>;
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>,
<&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>;
clock-names = "hsi2c", "hsi2c_pclk";
status = "disabled";
};
serial_1: serial@11d00000 {
compatible = "samsung,exynos850-uart";
reg = <0x11d00000 0xc0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_single_pins>;
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
<&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
};
usi_cmgp1: usi@11d200c0 {
compatible = "samsung,exynos850-usi";
reg = <0x11d200c0 0x20>;
samsung,sysreg = <&sysreg_cmgp 0x2010>;
samsung,mode = <USI_V2_I2C>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
<&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
hsi2c_4: i2c@11d20000 {
compatible = "samsung,exynosautov9-hsi2c";
reg = <0x11d20000 0xc0>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c4_pins>;
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>,
<&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>;
clock-names = "hsi2c", "hsi2c_pclk";
status = "disabled";
};
serial_2: serial@11d20000 {
compatible = "samsung,exynos850-uart";
reg = <0x11d20000 0xc0>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_single_pins>;
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
<&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
};
};
};
#include "exynos850-pinctrl.dtsi"

247
arch/arm/dts/omap3-igep.dtsi
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@ -1,247 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Common device tree for IGEP boards based on AM/DM37x
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
*/
/dts-v1/;
#include "omap36xx.dtsi"
/ {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
chosen {
stdout-path = &uart3;
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "igep2";
ti,mcbsp = <&mcbsp2>;
};
vdd33: regulator-vdd33 {
compatible = "regulator-fixed";
regulator-name = "vdd33";
regulator-always-on;
};
};
&omap3_pmx_core {
gpmc_pins: pinmux_gpmc_pins {
pinctrl-single,pins = <
/* OneNAND seems to require PIN_INPUT on clock. */
OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
>;
};
mcbsp2_pins: pinmux_mcbsp2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
>;
};
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
>;
};
};
&gpmc {
pinctrl-names = "default";
pinctrl-0 = <&gpmc_pins>;
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
linux,mtd-name = "micron,mt29c4g96maz";
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "bch8";
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-off-ns = <40>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
};
onenand@0,0 {
compatible = "ti,omap2-onenand";
reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
gpmc,sync-read;
gpmc,sync-write;
gpmc,burst-length = <16>;
gpmc,burst-wrap;
gpmc,burst-read;
gpmc,burst-write;
gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <96>;
gpmc,cs-wr-off-ns = <96>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <12>;
gpmc,adv-wr-off-ns = <12>;
gpmc,oe-on-ns = <18>;
gpmc,oe-off-ns = <96>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <96>;
gpmc,rd-cycle-ns = <114>;
gpmc,wr-cycle-ns = <114>;
gpmc,access-ns = <90>;
gpmc,page-burst-access-ns = <12>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <6>;
gpmc,wr-data-mux-bus-ns = <30>;
gpmc,wr-access-ns = <90>;
gpmc,sync-clk-ps = <12000>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
};
};
#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
};
&mcbsp2 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vmmc1>;
vmmc_aux-supply = <&vsim>;
bus-width = <4>;
cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
};
&mmc3 {
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
};
&twl_gpio {
ti,use-leds;
};
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
phys = <&usb2_phy>;
phy-names = "usb2-phy";
mode = <3>;
power = <50>;
};

261
arch/arm/dts/omap3-igep0020-common.dtsi
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@ -1,261 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Common Device Tree Source for IGEPv2
*
* Copyright (C) 2014 Javier Martinez Canillas <javier@dowhile0.org>
* Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
*/
#include "omap3-igep.dtsi"
#include "omap-gpmc-smsc9221.dtsi"
/ {
leds {
pinctrl-names = "default";
pinctrl-0 = <&leds_pins>;
compatible = "gpio-leds";
boot {
label = "omap3:green:boot";
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
user0 {
label = "omap3:red:user0";
gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
user1 {
label = "omap3:red:user1";
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
user2 {
label = "omap3:green:user1";
gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
};
};
/* HS USB Port 1 Power */
hsusb1_power: hsusb1_power_reg {
compatible = "regulator-fixed";
regulator-name = "hsusb1_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
startup-delay-us = <70000>;
};
/* HS USB Host PHY on PORT 1 */
hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
vcc-supply = <&hsusb1_power>;
#phy-cells = <0>;
};
tfp410: encoder {
compatible = "ti,tfp410";
powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint {
remote-endpoint = <&dpi_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
dvi0: connector {
compatible = "dvi-connector";
label = "dvi";
digital;
ddc-i2c-bus = <&i2c3>;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
};
&omap3_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&tfp410_pins
&dss_dpi_pins
>;
tfp410_pins: pinmux_tfp410_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
>;
};
dss_dpi_pins: pinmux_dss_dpi_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
>;
};
smsc9221_pins: pinmux_smsc9221_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
>;
};
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <
&hsusbb1_pins
>;
hsusbb1_pins: pinmux_hsusbb1_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
>;
};
mmc1_wp_pins: pinmux_mmc1_cd_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */
>;
};
};
&i2c3 {
clock-frequency = <100000>;
/*
* Display monitor features are burnt in the EEPROM
* as EDID data.
*/
eeprom@50 {
compatible = "ti,eeprom";
reg = <0x50>;
};
};
&gpmc {
ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */
<5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */
ethernet@gpmc {
pinctrl-names = "default";
pinctrl-0 = <&smsc9221_pins>;
reg = <5 0 0xff>;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};
&usbhshost {
port1-mode = "ehci-phy";
};
&usbhsehci {
phys = <&hsusb1_phy>;
};
&vpll2 {
/* Needed for DSS */
regulator-name = "vdds_dsi";
};
&dss {
status = "okay";
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
};
&mmc1 {
pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>;
wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */
};

14
arch/arm/dts/omap3-igep0020-u-boot.dtsi
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@ -5,20 +5,10 @@
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
*/
#include "omap3-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart3;
};
};
&uart1 {
reg-shift = <2>;
};
&uart2 {
reg-shift = <2>;
};
&uart3 {
reg-shift = <2>;
};

47
arch/arm/dts/omap3-igep0020.dts
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@ -1,47 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
*/
#include "omap3-igep0020-common.dtsi"
/ {
model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
vmmcsdio_fixed: fixedregulator-mmcsdio {
compatible = "regulator-fixed";
regulator-name = "vmmcsdio_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
mmc2_pwrseq: mmc2_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */
<&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */
};
};
&omap3_pmx_core {
lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */
OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */
>;
};
};
/* On board Wifi module */
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
vmmc-supply = <&vmmcsdio_fixed>;
mmc-pwrseq = <&mmc2_pwrseq>;
bus-width = <4>;
non-removable;
};

9
arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi Normal file
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@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk356x-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = &sdmmc0, &sdhci;
};
};

112
arch/arm/dts/rv1126-edgeble-neu2-io.dts
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@ -1,112 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
/dts-v1/;
#include "rv1126.dtsi"
#include "rv1126-edgeble-neu2.dtsi"
/ {
model = "Edgeble Neu2 IO Board";
compatible = "edgeble,neural-compute-module-2-io",
"edgeble,neural-compute-module-2", "rockchip,rv1126";
aliases {
serial2 = &uart2;
};
chosen {
stdout-path = "serial2:1500000n8";
};
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
v3v3_sys: v3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "v3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
};
&gmac {
assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
<&cru CLK_GMAC_ETHERNET_OUT>;
assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
assigned-clock-rates = <125000000>, <0>, <25000000>;
clock_in_out = "input";
phy-handle = <&phy>;
phy-mode = "rgmii";
phy-supply = <&vcc_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>;
tx_delay = <0x2a>;
rx_delay = <0x1a>;
status = "okay";
};
&mdio {
phy: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c916",
"ethernet-phy-ieee802.3-c22";
reg = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&eth_phy_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
ethernet {
eth_phy_rst: eth-phy-rst {
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&pwm11 {
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
rockchip,default-sample-phase = <90>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr104;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&uart2 {
status = "okay";
};

345
arch/arm/dts/rv1126-edgeble-neu2.dtsi
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@ -1,345 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
/ {
compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
aliases {
mmc0 = &emmc;
};
vccio_flash: vccio-flash-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&flash_vol_sel>;
regulator-name = "vccio_flash";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
};
sdio_pwrseq: pwrseq-sdio {
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>;
rockchip,default-sample-phase = <90>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vccio_flash>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc_buck5>;
vcc6-supply = <&vcc_buck5>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
regulators {
vdd_npu_vepu: DCDC_REG1 {
regulator-name = "vdd_npu_vepu";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc3v3_sys: DCDC_REG4 {
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_buck5: DCDC_REG5 {
regulator-name = "vcc_buck5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2200000>;
};
};
vcc_0v8: LDO_REG1 {
regulator-name = "vcc_0v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmu: LDO_REG2 {
regulator-name = "vcc1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd0v8_pmu: LDO_REG3 {
regulator-name = "vcc0v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <800000>;
};
};
vcc_1v8: LDO_REG4 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_dovdd: LDO_REG5 {
regulator-name = "vcc_dovdd";
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_dvdd: LDO_REG6 {
regulator-name = "vcc_dvdd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_avdd: LDO_REG7 {
regulator-name = "vcc_avdd";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG8 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: LDO_REG9 {
regulator-name = "vcc3v3_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_5v0: SWITCH_REG1 {
regulator-name = "vcc_5v0";
};
vcc_3v3: SWITCH_REG2 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
};
};
};
};
&pinctrl {
bt {
bt_enable: bt-enable {
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
flash {
flash_vol_sel: flash-vol-sel {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
wifi {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio0-supply = <&vcc1v8_pmu>;
pmuio1-supply = <&vcc3v3_sys>;
vccio1-supply = <&vccio_flash>;
vccio2-supply = <&vccio_sd>;
vccio3-supply = <&vcc_1v8>;
vccio4-supply = <&vcc_dovdd>;
vccio5-supply = <&vcc_1v8>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_dovdd>;
status = "okay";
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&sfc {
pinctrl-names = "default";
pinctrl-0 = <&fspi_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&sdio {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
max-frequency = <100000000>;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
rockchip,default-sample-phase = <90>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sys>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
status = "okay";
bluetooth {
compatible = "qcom,qca9377-bt";
clocks = <&rk809 1>;
enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */
max-speed = <2000000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_enable>;
vddxo-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
};
};

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arch/arm/dts/rv1126-pinctrl.dtsi
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@ -1,341 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <dt-bindings/pinctrl/rockchip.h>
#include "rockchip-pinconf.dtsi"
/*
* This file is auto generated by pin2dts tool, please keep these code
* by adding changes at end of this file.
*/
&pinctrl {
clk_out_ethernet {
/omit-if-no-ref/
clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
rockchip,pins =
/* clk_out_ethernet_m1 */
<2 RK_PC5 2 &pcfg_pull_none>;
};
};
emmc {
/omit-if-no-ref/
emmc_rstnout: emmc-rstnout {
rockchip,pins =
/* emmc_rstn */
<1 RK_PA3 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
emmc_bus8: emmc-bus8 {
rockchip,pins =
/* emmc_d0 */
<0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d1 */
<0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d2 */
<0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d3 */
<0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d4 */
<0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d5 */
<0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d6 */
<0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d7 */
<0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
emmc_clk: emmc-clk {
rockchip,pins =
/* emmc_clko */
<0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
emmc_cmd: emmc-cmd {
rockchip,pins =
/* emmc_cmd */
<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
};
};
fspi {
/omit-if-no-ref/
fspi_pins: fspi-pins {
rockchip,pins =
/* fspi_clk */
<1 RK_PA3 3 &pcfg_pull_down>,
/* fspi_cs0n */
<0 RK_PD4 3 &pcfg_pull_up>,
/* fspi_d0 */
<1 RK_PA0 3 &pcfg_pull_up>,
/* fspi_d1 */
<1 RK_PA1 3 &pcfg_pull_up>,
/* fspi_d2 */
<0 RK_PD6 3 &pcfg_pull_up>,
/* fspi_d3 */
<1 RK_PA2 3 &pcfg_pull_up>;
};
};
i2c0 {
/omit-if-no-ref/
i2c0_xfer: i2c0-xfer {
rockchip,pins =
/* i2c0_scl */
<0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
/* i2c0_sda */
<0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
};
};
i2c2 {
/omit-if-no-ref/
i2c2_xfer: i2c2-xfer {
rockchip,pins =
/* i2c2_scl */
<0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
/* i2c2_sda */
<0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
};
};
pwm2 {
/omit-if-no-ref/
pwm2m0_pins: pwm2m0-pins {
rockchip,pins =
/* pwm2_pin_m0 */
<0 RK_PC0 3 &pcfg_pull_none>;
};
};
pwm11 {
/omit-if-no-ref/
pwm11m0_pins: pwm11m0-pins {
rockchip,pins =
/* pwm11_pin_m0 */
<3 RK_PA7 6 &pcfg_pull_none>;
};
};
rgmii {
/omit-if-no-ref/
rgmiim1_miim: rgmiim1-miim {
rockchip,pins =
/* rgmii_mdc_m1 */
<2 RK_PC2 2 &pcfg_pull_none>,
/* rgmii_mdio_m1 */
<2 RK_PC1 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim1_rxer: rgmiim1-rxer {
rockchip,pins =
/* rgmii_rxer_m1 */
<2 RK_PC0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim1_bus2: rgmiim1-bus2 {
rockchip,pins =
/* rgmii_rxd0_m1 */
<2 RK_PB5 2 &pcfg_pull_none>,
/* rgmii_rxd1_m1 */
<2 RK_PB6 2 &pcfg_pull_none>,
/* rgmii_rxdv_m1 */
<2 RK_PB4 2 &pcfg_pull_none>,
/* rgmii_txd0_m1 */
<2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txd1_m1 */
<2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txen_m1 */
<2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgmiim1_bus4: rgmiim1-bus4 {
rockchip,pins =
/* rgmii_rxclk_m1 */
<2 RK_PD3 2 &pcfg_pull_none>,
/* rgmii_rxd2_m1 */
<2 RK_PC7 2 &pcfg_pull_none>,
/* rgmii_rxd3_m1 */
<2 RK_PD0 2 &pcfg_pull_none>,
/* rgmii_txclk_m1 */
<2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txd2_m1 */
<2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txd3_m1 */
<2 RK_PA4 2 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgmiim1_mclkinout: rgmiim1-mclkinout {
rockchip,pins =
/* rgmii_clk_m1 */
<2 RK_PB7 2 &pcfg_pull_none>;
};
};
sdmmc0 {
/omit-if-no-ref/
sdmmc0_bus4: sdmmc0-bus4 {
rockchip,pins =
/* sdmmc0_d0 */
<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc0_d1 */
<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc0_d2 */
<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc0_d3 */
<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc0_clk: sdmmc0-clk {
rockchip,pins =
/* sdmmc0_clk */
<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc0_cmd: sdmmc0-cmd {
rockchip,pins =
/* sdmmc0_cmd */
<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc0_det: sdmmc0-det {
rockchip,pins =
<0 RK_PA3 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
sdmmc0_pwr: sdmmc0-pwr {
rockchip,pins =
<0 RK_PC0 1 &pcfg_pull_none>;
};
};
sdmmc1 {
/omit-if-no-ref/
sdmmc1_bus4: sdmmc1-bus4 {
rockchip,pins =
/* sdmmc1_d0 */
<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc1_d1 */
<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc1_d2 */
<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc1_d3 */
<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc1_clk: sdmmc1-clk {
rockchip,pins =
/* sdmmc1_clk */
<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc1_cmd: sdmmc1-cmd {
rockchip,pins =
/* sdmmc1_cmd */
<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc1_det: sdmmc1-det {
rockchip,pins =
<1 RK_PD0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
sdmmc1_pwr: sdmmc1-pwr {
rockchip,pins =
<1 RK_PD1 2 &pcfg_pull_none>;
};
};
uart0 {
/omit-if-no-ref/
uart0_xfer: uart0-xfer {
rockchip,pins =
/* uart0_rx */
<1 RK_PC2 1 &pcfg_pull_up>,
/* uart0_tx */
<1 RK_PC3 1 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart0_ctsn: uart0-ctsn {
rockchip,pins =
<1 RK_PC1 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart0_rtsn: uart0-rtsn {
rockchip,pins =
<1 RK_PC0 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart0_rtsn_gpio: uart0-rts-pin {
rockchip,pins =
<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
uart1 {
/omit-if-no-ref/
uart1m0_xfer: uart1m0-xfer {
rockchip,pins =
/* uart1_rx_m0 */
<0 RK_PB7 2 &pcfg_pull_up>,
/* uart1_tx_m0 */
<0 RK_PB6 2 &pcfg_pull_up>;
};
};
uart2 {
/omit-if-no-ref/
uart2m1_xfer: uart2m1-xfer {
rockchip,pins =
/* uart2_rx_m1 */
<3 RK_PA3 1 &pcfg_pull_up>,
/* uart2_tx_m1 */
<3 RK_PA2 1 &pcfg_pull_up>;
};
};
uart3 {
/omit-if-no-ref/
uart3m0_xfer: uart3m0-xfer {
rockchip,pins =
/* uart3_rx_m0 */
<3 RK_PC7 4 &pcfg_pull_up>,
/* uart3_tx_m0 */
<3 RK_PC6 4 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart3m2_xfer: uart3m2-xfer {
rockchip,pins =
/* uart3_rx_m2 */
<3 RK_PA1 4 &pcfg_pull_up>,
/* uart3_tx_m2 */
<3 RK_PA0 4 &pcfg_pull_up>;
};
};
uart4 {
/omit-if-no-ref/
uart4m0_xfer: uart4m0-xfer {
rockchip,pins =
/* uart4_rx_m0 */
<3 RK_PA5 4 &pcfg_pull_up>,
/* uart4_tx_m0 */
<3 RK_PA4 4 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart4m2_xfer: uart4m2-xfer {
rockchip,pins =
/* uart4_rx_m2 */
<1 RK_PD4 3 &pcfg_pull_up>,
/* uart4_tx_m2 */
<1 RK_PD5 3 &pcfg_pull_up>;
};
};
uart5 {
/omit-if-no-ref/
uart5m0_xfer: uart5m0-xfer {
rockchip,pins =
/* uart5_rx_m0 */
<3 RK_PA7 4 &pcfg_pull_up>,
/* uart5_tx_m0 */
<3 RK_PA6 4 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart5m2_xfer: uart5m2-xfer {
rockchip,pins =
/* uart5_rx_m2 */
<2 RK_PA1 3 &pcfg_pull_up>,
/* uart5_tx_m2 */
<2 RK_PA0 3 &pcfg_pull_up>;
};
};
};

29
arch/arm/dts/rv1126-sonoff-ihost.dts
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@ -1,29 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1126.dtsi"
#include "rv1126-sonoff-ihost.dtsi"
/ {
model = "Sonoff iHost 4G";
compatible = "itead,sonoff-ihost", "rockchip,rv1126";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};

404
arch/arm/dts/rv1126-sonoff-ihost.dtsi
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@ -1,404 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
/ {
aliases {
ethernet0 = &gmac;
mmc0 = &emmc;
};
chosen {
stdout-path = "serial2:1500000n8";
};
vcc5v0_sys: regulator-vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
sdio_pwrseq: pwrseq-sdio {
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
};
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
rockchip,default-sample-phase = <90>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc_buck5>;
vcc6-supply = <&vcc_buck5>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
regulators {
vdd_npu_vepu: DCDC_REG1 {
regulator-name = "vdd_npu_vepu";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc3v3_sys: DCDC_REG4 {
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_buck5: DCDC_REG5 {
regulator-name = "vcc_buck5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2200000>;
};
};
vcc_0v8: LDO_REG1 {
regulator-name = "vcc_0v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmu: LDO_REG2 {
regulator-name = "vcc1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd0v8_pmu: LDO_REG3 {
regulator-name = "vcc0v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <800000>;
};
};
vcc_1v8: LDO_REG4 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_dovdd: LDO_REG5 {
regulator-name = "vcc_dovdd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_dvdd: LDO_REG6 {
regulator-name = "vcc_dvdd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_avdd: LDO_REG7 {
regulator-name = "vcc_avdd";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG8 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: LDO_REG9 {
regulator-name = "vcc3v3_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_5v0: SWITCH_REG1 {
regulator-name = "vcc_5v0";
};
vcc_3v3: SWITCH_REG2 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
};
};
};
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
#clock-cells = <0>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
clock-output-names = "xin32k";
};
};
&gmac {
assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>,
<&cru CLK_GMAC_TX_RX>;
assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>,
<&cru RMII_MODE_CLK>;
assigned-clock-rates = <0>, <50000000>;
clock_in_out = "output";
phy-handle = <&phy>;
phy-mode = "rmii";
phy-supply = <&vcc_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_miim &rgmiim1_rxer &rgmiim1_bus2 &rgmiim1_mclkinout>;
status = "okay";
};
&mdio {
phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&eth_phy_rst>;
reset-active-low;
reset-assert-us = <50000>;
reset-deassert-us = <10000>;
reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
ethernet {
eth_phy_rst: eth-phy-rst {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
bt {
bt_enable: bt-enable {
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_dev: bt-wake-dev {
rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_host: bt-wake-host {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
wifi {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio0-supply = <&vcc1v8_pmu>;
pmuio1-supply = <&vcc3v3_sys>;
vccio1-supply = <&vcc_1v8>;
vccio2-supply = <&vccio_sd>;
vccio3-supply = <&vcc_1v8>;
vccio4-supply = <&vcc_dovdd>;
vccio5-supply = <&vcc_1v8>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_dovdd>;
status = "okay";
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&sdio {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
max-frequency = <100000000>;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
rockchip,default-sample-phase = <90>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sys>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
rockchip,default-sample-phase = <90>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr104;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "realtek,rtl8723ds-bt";
device-wake-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; /* BT_WAKE */
enable-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; /* BT_RST */
host-wake-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; /* BT_WAKE_HOST */
max-speed = <2000000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>;
};
};
&uart2 {
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3m2_xfer>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4m2_xfer>;
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/clock/rockchip,rv1126-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rockchip,rv1126-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "rockchip,rv1126";
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
i2c2 = &i2c2;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
};
cpu1: cpu@f01 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf01>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
};
cpu2: cpu@f02 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf02>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
};
cpu3: cpu@f03 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf03>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
};
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};
display_subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop_out>;
};
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xin24m";
#clock-cells = <0>;
};
grf: syscon@fe000000 {
compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
reg = <0xfe000000 0x20000>;
};
pmugrf: syscon@fe020000 {
compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
reg = <0xfe020000 0x1000>;
pmu_io_domains: io-domains {
compatible = "rockchip,rv1126-pmu-io-voltage-domain";
status = "disabled";
};
};
qos_emmc: qos@fe860000 {
compatible = "rockchip,rv1126-qos", "syscon";
reg = <0xfe860000 0x20>;
};
qos_nandc: qos@fe860080 {
compatible = "rockchip,rv1126-qos", "syscon";
reg = <0xfe860080 0x20>;
};
qos_sfc: qos@fe860200 {
compatible = "rockchip,rv1126-qos", "syscon";
reg = <0xfe860200 0x20>;
};
qos_sdio: qos@fe86c000 {
compatible = "rockchip,rv1126-qos", "syscon";
reg = <0xfe86c000 0x20>;
};
qos_iep: qos@fe8a0000 {
compatible = "rockchip,rv1126-qos", "syscon";
reg = <0xfe8a0000 0x20>;
};
qos_rga_rd: qos@fe8a0080 {
compatible = "rockchip,rv1126-qos", "syscon";
reg = <0xfe8a0080 0x20>;
};
qos_rga_wr: qos@fe8a0100 {
compatible = "rockchip,rv1126-qos", "syscon";
reg = <0xfe8a0100 0x20>;
};
qos_vop: qos@fe8a0180 {
compatible = "rockchip,rv1126-qos", "syscon";
reg = <0xfe8a0180 0x20>;
};
gic: interrupt-controller@feff0000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0xfeff1000 0x1000>,
<0xfeff2000 0x2000>,
<0xfeff4000 0x2000>,
<0xfeff6000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
pmu: power-management@ff3e0000 {
compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
reg = <0xff3e0000 0x1000>;
power: power-controller {
compatible = "rockchip,rv1126-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RV1126_PD_NVM {
reg = <RV1126_PD_NVM>;
clocks = <&cru HCLK_EMMC>,
<&cru CLK_EMMC>,
<&cru HCLK_NANDC>,
<&cru CLK_NANDC>,
<&cru HCLK_SFC>,
<&cru HCLK_SFCXIP>,
<&cru SCLK_SFC>;
pm_qos = <&qos_emmc>,
<&qos_nandc>,
<&qos_sfc>;
#power-domain-cells = <0>;
};
power-domain@RV1126_PD_SDIO {
reg = <RV1126_PD_SDIO>;
clocks = <&cru HCLK_SDIO>,
<&cru CLK_SDIO>;
pm_qos = <&qos_sdio>;
#power-domain-cells = <0>;
};
power-domain@RV1126_PD_VO {
reg = <RV1126_PD_VO>;
clocks = <&cru ACLK_RGA>,
<&cru HCLK_RGA>,
<&cru CLK_RGA_CORE>,
<&cru ACLK_VOP>,
<&cru HCLK_VOP>,
<&cru DCLK_VOP>,
<&cru PCLK_DSIHOST>,
<&cru ACLK_IEP>,
<&cru HCLK_IEP>,
<&cru CLK_IEP_CORE>;
pm_qos = <&qos_rga_rd>,
<&qos_rga_wr>,
<&qos_vop>,
<&qos_iep>;
#power-domain-cells = <0>;
};
};
};
i2c0: i2c@ff3f0000 {
compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
reg = <0xff3f0000 0x1000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
rockchip,grf = <&pmugrf>;
clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@ff400000 {
compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
reg = <0xff400000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
rockchip,grf = <&pmugrf>;
clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart1: serial@ff410000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff410000 0x100>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 7>, <&dmac 6>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
pwm2: pwm@ff430020 {
compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
reg = <0xff430020 0x10>;
clock-names = "pwm", "pclk";
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2m0_pins>;
#pwm-cells = <3>;
status = "disabled";
};
pmucru: clock-controller@ff480000 {
compatible = "rockchip,rv1126-pmucru";
reg = <0xff480000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
cru: clock-controller@ff490000 {
compatible = "rockchip,rv1126-cru";
reg = <0xff490000 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
dmac: dma-controller@ff4e0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xff4e0000 0x4000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
};
pwm11: pwm@ff550030 {
compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
reg = <0xff550030 0x10>;
clock-names = "pwm", "pclk";
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
pinctrl-0 = <&pwm11m0_pins>;
pinctrl-names = "default";
#pwm-cells = <3>;
status = "disabled";
};
uart0: serial@ff560000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff560000 0x100>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 5>, <&dmac 4>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@ff570000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff570000 0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 9>, <&dmac 8>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@ff580000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff580000 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 11>, <&dmac 10>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart3m0_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart4: serial@ff590000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff590000 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 13>, <&dmac 12>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart4m0_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart5: serial@ff5a0000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff5a0000 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 15>, <&dmac 14>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart5m0_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
saradc: adc@ff5e0000 {
compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
reg = <0xff5e0000 0x100>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC_P>;
reset-names = "saradc-apb";
status = "disabled";
};
timer0: timer@ff660000 {
compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
reg = <0xff660000 0x20>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
clock-names = "pclk", "timer";
};
vop: vop@ffb00000 {
compatible = "rockchip,rv1126-vop";
reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
reset-names = "axi", "ahb", "dclk";
resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
iommus = <&vop_mmu>;
power-domains = <&power RV1126_PD_VO>;
status = "disabled";
vop_out: port {
#address-cells = <1>;
#size-cells = <0>;
vop_out_rgb: endpoint@0 {
reg = <0>;
};
vop_out_dsi: endpoint@1 {
reg = <1>;
};
};
};
vop_mmu: iommu@ffb00f00 {
compatible = "rockchip,iommu";
reg = <0xffb00f00 0x100>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "aclk", "iface";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
#iommu-cells = <0>;
power-domains = <&power RV1126_PD_VO>;
status = "disabled";
};
gmac: ethernet@ffc40000 {
compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
reg = <0xffc40000 0x4000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
rockchip,grf = <&grf>;
clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
<&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
<&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
<&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"aclk_mac", "pclk_mac",
"clk_mac_speed", "ptp_ref";
resets = <&cru SRST_GMAC_A>;
reset-names = "stmmaceth";
snps,mixed-burst;
snps,tso;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
status = "disabled";
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <4>;
snps,rd_osr_lmt = <8>;
snps,blen = <0 0 0 0 16 8 4>;
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
};
emmc: mmc@ffc50000 {
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0xffc50000 0x4000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <200000000>;
power-domains = <&power RV1126_PD_NVM>;
status = "disabled";
};
sdmmc: mmc@ffc60000 {
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0xffc60000 0x4000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <200000000>;
status = "disabled";
};
sdio: mmc@ffc70000 {
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0xffc70000 0x4000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <200000000>;
power-domains = <&power RV1126_PD_SDIO>;
status = "disabled";
};
sfc: spi@ffc90000 {
compatible = "rockchip,sfc";
reg = <0xffc90000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru SCLK_SFC>;
assigned-clock-rates = <80000000>;
clock-names = "clk_sfc", "hclk_sfc";
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
power-domains = <&power RV1126_PD_NVM>;
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rv1126-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmugrf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio@ff460000 {
compatible = "rockchip,gpio-bank";
reg = <0xff460000 0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@ff620000 {
compatible = "rockchip,gpio-bank";
reg = <0xff620000 0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@ff630000 {
compatible = "rockchip,gpio-bank";
reg = <0xff630000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@ff640000 {
compatible = "rockchip,gpio-bank";
reg = <0xff640000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@ff650000 {
compatible = "rockchip,gpio-bank";
reg = <0xff650000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
#include "rv1126-pinctrl.dtsi"

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arch/arm/dts/salvator-common.dtsi
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arch/arm/dts/salvator-x.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X board
*
* Copyright (C) 2015-2016 Renesas Electronics Corp.
*/
#include "salvator-common.dtsi"
/ {
model = "Renesas Salvator-X board";
compatible = "renesas,salvator-x";
};
&extal_clk {
clock-frequency = <16666666>;
};
&i2c4 {
clock-frequency = <400000>;
versaclock5: clock-generator@6a {
compatible = "idt,5p49v5923";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x23_clk>;
clock-names = "xin";
};
};

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arch/arm/dts/salvator-xs.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X 2nd version board
*
* Copyright (C) 2015-2017 Renesas Electronics Corp.
*/
#include "salvator-common.dtsi"
/ {
model = "Renesas Salvator-X 2nd version board";
compatible = "renesas,salvator-xs";
};
&extal_clk {
clock-frequency = <16640000>;
};
&i2c4 {
clock-frequency = <400000>;
versaclock6: clock-generator@6a {
compatible = "idt,5p49v6901";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x23_clk>;
clock-names = "xin";
};
};
#ifdef SOC_HAS_SATA
&pca9654 {
pcie-sata-switch-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low; /* enable SATA by default */
line-name = "PCIE/SATA switch";
};
};
/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
#endif /* SOC_HAS_SATA */
#ifdef SOC_HAS_USB2_CH3
&ehci3 {
dr_mode = "otg";
status = "okay";
};
&hsusb3 {
dr_mode = "otg";
status = "okay";
};
&ohci3 {
dr_mode = "otg";
status = "okay";
};
&pfc {
/*
* - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
* (when SW31 is the default setting on Salvator-XS).
* - If SW31 is the default setting, you cannot use USB2.0 ch3 on
* r8a77951 with Salvator-XS.
* Hence the SW31 setting must be changed like 2) below.
* 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
* - Connect GP6_3[01] to ADV7842.
* 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
* - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
* - Connect GP6_{04,21} to ADV7842.
*/
usb2_ch3_pins: usb2_ch3 {
groups = "usb2_ch3";
function = "usb2_ch3";
};
};
&usb2_phy3 {
pinctrl-0 = <&usb2_ch3_pins>;
pinctrl-names = "default";
status = "okay";
};
#endif /* SOC_HAS_USB2_CH3 */

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arch/arm/dts/ulcb-audio-graph-card.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree for ULCB + Audio Graph Card
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
/*
* (A) CPU0 <-----> ak4613
* (B) CPU1 -----> HDMI
*
* (A) aplay -D plughw:0,0 xxx.wav
* (B) aplay -D plughw:0,1 xxx.wav
*
* (A) arecord -D plughw:0,0 xxx.wav
*/
/ {
sound_card: sound {
compatible = "audio-graph-card";
label = "rcar-sound";
dais = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */
&rsnd_port1 /* (B) CPU1 -> HDMI */
>;
};
};
&ak4613 {
#sound-dai-cells = <0>;
port {
/*
* (A) CPU0 <-> ak4613
*/
ak4613_endpoint: endpoint {
remote-endpoint = <&rsnd_for_ak4613>;
};
};
};
&hdmi0 {
ports {
port@2 {
/*
* (B) CPU1 -> HDMI
*/
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_for_hdmi>;
};
};
};
};
&rcar_sound {
ports {
#address-cells = <1>;
#size-cells = <0>;
rsnd_port0: port@0 {
/*
* (A) CPU0 <-> ak4613
*/
reg = <0>;
rsnd_for_ak4613: endpoint {
remote-endpoint = <&ak4613_endpoint>;
bitclock-master;
frame-master;
playback = <&ssi0>, <&src0>, <&dvc0>;
capture = <&ssi1>, <&src1>, <&dvc1>;
};
};
rsnd_port1: port@1 {
/*
* (B) CPU1 -> HDMI
*/
reg = <1>;
rsnd_for_hdmi: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
bitclock-master;
frame-master;
playback = <&ssi2>;
};
};
};
};

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arch/arm/dts/ulcb-audio-graph-card2.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree for ULCB + Audio Graph Card2
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
/*
* (A) CPU0 <----> ak4613
* (B) CPU1 ----> HDMI
*
* (A) aplay -D plughw:0,0 xxx.wav
* (B) aplay -D plughw:0,1 xxx.wav
*
* (A) arecord -D plughw:0,0 xxx.wav
*/
#include "ulcb-audio-graph-card.dtsi"
&sound_card {
compatible = "audio-graph-card2";
/delete-property/ dais;
links = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */
&rsnd_port1 /* (B) CPU1 -> HDMI */
>;
};

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arch/arm/dts/ulcb.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the R-Car Gen3 ULCB board
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Renesas R-Car Gen3 ULCB board";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
serial0 = &scif2;
ethernet0 = &avb;
mmc0 = &sdhi2;
mmc1 = &sdhi0;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
};
hdmi0-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con: endpoint {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
};
};
keyboard {
compatible = "gpio-keys";
key-1 {
linux,code = <KEY_1>;
label = "SW3";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led5 {
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
};
led6 {
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
};
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
x23_clk: x23-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
&a57_0 {
cpu-supply = <&dvfs>;
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
};
&du {
status = "okay";
};
&ehci1 {
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
};
};
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <100000>;
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
reg = <0x10>;
clocks = <&rcar_sound 3>;
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
};
cs2000: clk-multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
versaclock5: clock-generator@6a {
compatible = "idt,5p49v5925";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x23_clk>;
clock-names = "xin";
};
};
&i2c_dvfs {
status = "okay";
clock-frequency = <400000>;
pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "rohm,bd9571mwv";
reg = <0x30>;
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
rohm,ddr-backup-power = <0xf>;
rohm,rstbmode-pulse;
regulators {
dvfs: dvfs {
regulator-name = "dvfs";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1030000>;
regulator-boot-on;
regulator-always-on;
};
};
};
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
};
&ohci1 {
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb {
mux {
groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb";
};
pins_mdio {
groups = "avb_mdio";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
drive-strength = <12>;
};
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
function = "sdhi2";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
sound_clk_pins: sound-clk {
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout3_a";
function = "audio_clk";
};
usb1_pins: usb1 {
groups = "usb1";
function = "usb1";
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
status = "okay";
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
};
&rpc {
/* Left disabled. To be enabled by firmware when unlocked. */
flash@0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
bl2@40000 {
reg = <0x00040000 0x140000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x040000>;
read-only;
};
tee@200000 {
reg = <0x00200000 0x440000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x100000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&ssi1 {
shared-pin;
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};
/*
* For sound-test.
*
* We can switch Audio Card for testing
*
* #include "ulcb-simple-audio-card.dtsi"
* #include "ulcb-simple-audio-card-mix+split.dtsi"
* #include "ulcb-audio-graph-card.dtsi"
* #include "ulcb-audio-graph-card-mix+split.dtsi"
* #include "ulcb-audio-graph-card2-mix+split.dtsi"
*/
#include "ulcb-audio-graph-card2.dtsi"

4
arch/arm/include/asm/arch-rockchip/cru_rk3588.h
View File

@ -29,6 +29,7 @@ enum rk3588_pll_id {
V0PLL,
AUPLL,
PPLL,
SPLL,
PLL_COUNT,
};
@ -150,6 +151,9 @@ struct pll_rate_table {
#define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
#define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
#define RK3588_SBUSCRU_SPLL_CON(x) ((x) * 0x4 + 0x220)
#define RK3588_SBUSCRU_MODE_CON0 0x280
enum {
/* CRU_CLK_SEL8_CON */
ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT = 14,

1
arch/arm/mach-exynos/Kconfig
View File

@ -249,6 +249,7 @@ config TARGET_E850_96
select OF_CONTROL
select PINCTRL
select PINCTRL_EXYNOS850
imply OF_UPSTREAM
endchoice
endif

8
arch/arm/mach-exynos/mmu-arm64.c
View File

@ -100,6 +100,14 @@ struct mm_region *mem_map = exynos7880_mem_map;
static struct mm_region exynos850_mem_map[] = {
{
/* iRAM */
.virt = 0x02000000UL,
.phys = 0x02000000UL,
.size = SZ_2M,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* Peripheral block */
.virt = 0x10000000UL,
.phys = 0x10000000UL,

1
arch/arm/mach-k3/am62px/Kconfig
View File

@ -13,6 +13,7 @@ config TARGET_AM62P5_A53_EVM
bool "TI K3 based AM62P5 EVM running on A53"
select ARM64
select BINMAN
select OF_SYSTEM_SETUP
config TARGET_AM62P5_R5_EVM
bool "TI K3 based AM62P5 EVM running on R5"

1
arch/arm/mach-k3/am62px/Makefile
View File

@ -3,4 +3,5 @@
# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
# Andrew Davis <afd@ti.com>
obj-$(CONFIG_OF_SYSTEM_SETUP) += am62p5_fdt.o
obj-$(CONFIG_SPL_BUILD) += am62p5_init.o

16
arch/arm/mach-k3/am62px/am62p5_fdt.c Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <asm/hardware.h>
#include "../common_fdt.h"
#include <fdt_support.h>
int ft_system_setup(void *blob, struct bd_info *bd)
{
fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000);
fdt_fixup_reserved(blob, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000);
return 0;
}

1
arch/arm/mach-rockchip/Kconfig
View File

@ -427,6 +427,7 @@ config ROCKCHIP_RV1126
imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_SERIAL
imply SPL_SYSCON
imply OF_UPSTREAM
config ROCKCHIP_USB_UART
bool "Route uart output to usb pins"

8
arch/arm/mach-rockchip/px30/Kconfig
View File

@ -68,8 +68,11 @@ config ROCKCHIP_STIMER_BASE
config SYS_SOC
default "px30"
config ROCKCHIP_COMMON_STACK_ADDR
default y
config SYS_MALLOC_F_LEN
default 0x400
default 0x400 if !SPL_SHARES_INIT_SP_ADDR
config SPL_SERIAL
default y
@ -83,6 +86,9 @@ config TPL_TEXT_BASE
config TPL_STACK
default 0xff0e4fff
config TPL_SYS_MALLOC_F_LEN
default 0x600
config DEBUG_UART_CHANNEL
int "Mux channel to use for debug UART2/UART3"
depends on DEBUG_UART_BOARD_INIT

6
arch/arm/mach-rockchip/rk3568/Kconfig
View File

@ -22,6 +22,11 @@ config TARGET_ODROID_M1_RK3568
help
Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC.
config TARGET_POWKIDDY_X55_RK3566
bool "Powkiddy X55"
help
Powkiddy X55 handheld gaming console with an RK3566 SoC.
config TARGET_QUARTZ64_RK3566
bool "Pine64 Quartz64"
help
@ -48,5 +53,6 @@ source "board/rockchip/evb_rk3568/Kconfig"
source "board/anbernic/rgxx3_rk3566/Kconfig"
source "board/hardkernel/odroid_m1/Kconfig"
source "board/pine64/quartz64_rk3566/Kconfig"
source "board/powkiddy/x55/Kconfig"
endif

10
arch/arm/mach-rockchip/rk3588/Kconfig
View File

@ -78,6 +78,15 @@ config TARGET_NANOPCT6_RK3588
Power: 5.5*2.1mm DC Jack, 12VDC input
Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)
config TARGET_NOVA_RK3588
bool "Indiedroid Nova RK3588"
select BOARD_LATE_INIT
help
Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid.
It comes in configurations from 4GB of RAM to 16GB of RAM,
includes socket for eMMC storage, an SDMMC slot, and a 40-pin
GPIO header for expansion.
config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
@ -223,6 +232,7 @@ config TEXT_BASE
source "board/edgeble/neural-compute-module-6/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
source "board/indiedroid/nova/Kconfig"
source "board/pine64/quartzpro64-rk3588/Kconfig"
source "board/turing/turing-rk1-rk3588/Kconfig"
source "board/radxa/rock5a-rk3588s/Kconfig"

4
arch/riscv/cpu/andes/cache.c
View File

@ -43,9 +43,7 @@ static void cache_ops(int (*ops)(struct udevice *dev))
void flush_dcache_all(void)
{
#if CONFIG_IS_ENABLED(RISCV_MMODE)
csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
#endif
csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
}
void flush_dcache_range(unsigned long start, unsigned long end)

4
arch/riscv/cpu/start.S
View File

@ -210,10 +210,6 @@ wait_for_gd_init:
bnez s2, secondary_hart_loop
#endif
/* Enable cache */
jal icache_enable
jal dcache_enable
#ifdef CONFIG_DEBUG_UART
jal debug_uart_init
#endif

2
arch/riscv/include/asm/arch-andes/csr.h
View File

@ -12,7 +12,7 @@
#define CSR_MCACHE_CTL 0x7ca
#define CSR_MMISC_CTL 0x7d0
#define CSR_MCCTLCOMMAND 0x7cc
#define CSR_UCCTLCOMMAND 0x80c
/* mcache_ctl register */

2
board/armltd/vexpress/MAINTAINERS
View File

@ -1,5 +1,5 @@
VERSATILE EXPRESS BOARDS
M: Kristian Amlie <kristian.amlie@northern.tech>
M: Josef Holzmayr <josef.holzmayr@northern.tech>
S: Maintained
F: board/armltd/vexpress/
F: include/configs/vexpress_ca9x4.h

1
board/beacon/beacon-rzg2m/MAINTAINERS
View File

@ -1,5 +1,6 @@
BEACON_RZG2M BOARD
M: Adam Ford <aford173@gmail.com>
M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
F: board/beacon/beacon-rzg2m/
F: include/configs/beacon-rzg2m.h

2
board/hardkernel/odroid_go2/MAINTAINERS
View File

@ -1,5 +1,5 @@
GO2
M: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
M: Heiko Stuebner <heiko.stuebner@cherry.de>
S: Maintained
F: board/hardkernel/odroid_go2/
F: include/configs/odroid_go2.h

12
board/indiedroid/nova/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_NOVA_RK3588
config SYS_BOARD
default "nova-rk3588s"
config SYS_VENDOR
default "indiedroid"
config SYS_CONFIG_NAME
default "nova-rk3588s"
endif

6
board/indiedroid/nova/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
INDIEDROID-NOVA-RK3588
M: Chris Morgan <macromorgan@hotmail.com>
S: Maintained
F: board/indiedroid/nova
F: configs/nova-rk3588s_defconfig
F: include/configs/nova-rk3588s.h

12
board/isee/igep00x0/igep00x0.c
View File

@ -29,18 +29,6 @@
#include <fdt_support.h>
#include "igep00x0.h"
static const struct ns16550_plat igep_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DRVINFO(igep_uart) = {
"ns16550_serial",
&igep_serial
};
/*
* Routine: get_board_revision
* Description: GPIO_28 and GPIO_129 are used to read board and revision from

25
board/microchip/mpfs_icicle/mpfs_icicle.c
View File

@ -72,25 +72,13 @@ int board_early_init_f(void)
int board_late_init(void)
{
u32 ret;
u32 node;
int node;
u8 idx;
u8 device_serial_number[16] = { 0 };
unsigned char mac_addr[6];
char icicle_mac_addr[20];
void *blob = (void *)gd->fdt_blob;
node = fdt_path_offset(blob, "/soc/ethernet@20112000");
if (node < 0) {
printf("No ethernet0 path offset\n");
return -ENODEV;
}
ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr, 6);
if (ret) {
printf("No local-mac-address property for ethernet@20112000\n");
return -EINVAL;
}
read_device_serial_number(device_serial_number, 16);
/* Update MAC address with device serial number */
@ -101,10 +89,13 @@ int board_late_init(void)
mac_addr[4] = device_serial_number[1];
mac_addr[5] = device_serial_number[0];
ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
if (ret) {
printf("Error setting local-mac-address property for ethernet@20112000\n");
return -ENODEV;
node = fdt_path_offset(blob, "/soc/ethernet@20112000");
if (node >= 0) {
ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
if (ret) {
printf("Error setting local-mac-address property for ethernet@20112000\n");
return -ENODEV;
}
}
icicle_mac_addr[0] = '[';

15
board/powkiddy/x55/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_POWKIDDY_X55_RK3566
config SYS_BOARD
default "x55"
config SYS_VENDOR
default "powkiddy"
config SYS_CONFIG_NAME
default "powkiddy-x55-rk3566"
config BOARD_SPECIFIC_OPTIONS
def_bool y
endif

7
board/powkiddy/x55/MAINTAINERS Normal file
View File

@ -0,0 +1,7 @@
X55
M: Chris Morgan <macromorgan@hotmail.com>
S: Maintained
F: board/powkiddy/x55
F: include/configs/powkiddy-x55-rk3566.h
F: configs/powkiddy-x55-rk3566_defconfig
F: arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi

6
board/powkiddy/x55/Makefile Normal file
View File

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2023 Chris Morgan <macromorgan@hotmail.com>
#
obj-y += x55.o

39
board/powkiddy/x55/x55.c Normal file
View File

@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2023 Chris Morgan <macromorgan@hotmail.com>
*/
#include <asm/io.h>
#define GPIO4_BASE 0xfe770000
#define GPIO_SWPORT_DR_L 0x0000
#define GPIO_SWPORT_DDR_L 0x0008
#define GPIO_B4 BIT(12)
#define GPIO_B5 BIT(13)
#define GPIO_B6 BIT(14)
#define GPIO_WRITEMASK(bits) ((bits) << 16)
/*
* Start LED very early so user knows device is on. Set color
* to red.
*/
void spl_board_init(void)
{
/* Set GPIO4_B4, GPIO4_B5, and GPIO4_B6 to output. */
writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | \
(GPIO_B6 | GPIO_B5 | GPIO_B4),
(GPIO4_BASE + GPIO_SWPORT_DDR_L));
/* Set GPIO4_B5 and GPIO4_B6 to 0 and GPIO4_B4 to 1. */
writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | GPIO_B4,
(GPIO4_BASE + GPIO_SWPORT_DR_L));
}
int rk_board_late_init(void)
{
/* Turn off red LED and turn on orange LED. */
writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | GPIO_B6,
(GPIO4_BASE + GPIO_SWPORT_DR_L));
return 0;
}

1
board/samsung/e850-96/MAINTAINERS
View File

@ -2,7 +2,6 @@ WINLINK E850-96 BOARD
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: arch/arm/dts/exynos850-e850-96-u-boot.dtsi
F: arch/arm/dts/exynos850-e850-96.dts
F: board/samsung/e850-96/
F: configs/e850-96_defconfig
F: doc/board/samsung/e850-96.rst

89
board/starfive/visionfive2/spl.c
View File

@ -86,6 +86,43 @@ static const struct starfive_vf2_pro starfive_verb[] = {
"tx-internal-delay-ps", "0"},
};
static const struct starfive_vf2_pro star64_pine64[] = {
{"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
{"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,tx-clk-adj-enabled", NULL},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,tx-clk-10-inverted", NULL},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,tx-clk-100-inverted", NULL},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,tx-clk-1000-inverted", NULL},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,rx-clk-drv-microamp", "2910"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,rx-data-drv-microamp", "2910"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"rx-internal-delay-ps", "1900"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"tx-internal-delay-ps", "1500"},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,tx-clk-adj-enabled", NULL},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,tx-clk-10-inverted", NULL},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,tx-clk-100-inverted", NULL},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,rx-clk-drv-microamp", "2910"},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,rx-data-drv-microamp", "2910"},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"rx-internal-delay-ps", "0"},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"tx-internal-delay-ps", "300"},
};
void spl_fdt_fixup_mars(void *fdt)
{
static const char compat[] = "milkv,mars\0starfive,jh7110";
@ -250,6 +287,56 @@ void spl_fdt_fixup_version_b(void *fdt)
}
}
void spl_fdt_fixup_star64(void *fdt)
{
static const char compat[] = "pine64,star64\0starfive,jh7110";
u32 phandle;
u8 i;
int offset;
int ret;
fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
"Pine64 Star64");
/* gmac0 */
offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
phandle = fdt_get_phandle(fdt, offset);
offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
JH7110_AONCLK_GMAC0_RMII_RTX);
/* gmac1 */
offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
phandle = fdt_get_phandle(fdt, offset);
offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
JH7110_SYSCLK_GMAC1_RMII_RTX);
for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) {
offset = fdt_path_offset(fdt, star64_pine64[i].path);
if (star64_pine64[i].value)
ret = fdt_setprop_u32(fdt, offset, star64_pine64[i].name,
dectoul(star64_pine64[i].value, NULL));
else
ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name);
if (ret) {
pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name);
break;
}
}
}
void spl_perform_fixups(struct spl_image_info *spl_image)
{
u8 version;
@ -278,6 +365,8 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
spl_fdt_fixup_version_b(spl_image->fdt_addr);
break;
};
} else if (!strncmp(product_id, "STAR64", 6)) {
spl_fdt_fixup_star64(spl_image->fdt_addr);
} else {
pr_err("Unknown product %s\n", product_id);
};

4
board/starfive/visionfive2/starfive_visionfive2.c
View File

@ -27,6 +27,8 @@ DECLARE_GLOBAL_DATA_PTR;
"starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
#define FDTFILE_VISIONFIVE2_1_3B \
"starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
#define FDTFILE_PINE64_STAR64 \
"starfive/jh7110-pine64-star64.dtb"
/* enable U74-mc hart1~hart4 prefetcher */
static void enable_prefetcher(void)
@ -87,6 +89,8 @@ static void set_fdtfile(void)
fdtfile = FDTFILE_VISIONFIVE2_1_3B;
break;
}
} else if (!strncmp(product_id, "STAR64", 6)) {
fdtfile = FDTFILE_PINE64_STAR64;
} else {
log_err("Unknown product\n");
return;

8
board/theobroma-systems/jaguar_rk3588/MAINTAINERS
View File

@ -1,6 +1,6 @@
JAGUAR-RK3588 (SBC-RK3588-AMR Single Board Computer)
M: Klaus Goger <klaus.goger@theobroma-systems.com>
M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
M: Klaus Goger <klaus.goger@cherry.de>
M: Quentin Schulz <quentin.schulz@cherry.de>
M: Heiko Stuebner <heiko.stuebner@cherry.de>
S: Maintained
F: board/theobroma-systems/jaguar_rk3588
@ -9,5 +9,5 @@ F: doc/board/theobroma-systems/
F: include/configs/jaguar_rk3588.h
F: arch/arm/dts/rk3588-jaguar*
F: configs/jaguar-rk3588_defconfig
W: https://theobroma-systems.com/product/jaguar-sbc-rk3588/
T: git git://git.theobroma-systems.com/jaguar-u-boot.git
W: https://embedded.cherry.de/product/jaguar-sbc-rk3588/
T: git git://git.embedded.cherry.de/jaguar-u-boot.git

4
board/theobroma-systems/lion_rk3368/MAINTAINERS
View File

@ -1,6 +1,6 @@
LION-RK3368 (RK3368-uQ7 system-on-module)
M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
M: Klaus Goger <klaus.goger@theobroma-systems.com>
M: Quentin Schulz <quentin.schulz@cherry.de>
M: Klaus Goger <klaus.goger@cherry.de>
S: Maintained
F: board/theobroma-systems/lion_rk3368
F: include/configs/lion_rk3368.h

8
board/theobroma-systems/puma_rk3399/MAINTAINERS
View File

@ -1,6 +1,6 @@
PUMA-RK3399
M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
M: Klaus Goger <klaus.goger@theobroma-systems.com>
M: Quentin Schulz <quentin.schulz@cherry.de>
M: Klaus Goger <klaus.goger@cherry.de>
S: Maintained
F: board/theobroma-systems/puma_rk3399
F: board/theobroma-systems/common
@ -8,5 +8,5 @@ F: doc/board/theobroma-systems
F: include/configs/puma_rk3399.h
F: arch/arm/dts/rk3399-puma*
F: configs/puma-rk3399_defconfig
W: https://www.theobroma-systems.com/rk3399-q7/tech-specs
T: git git://git.theobroma-systems.com/puma-u-boot.git
W: https://embedded.cherry.de/product/puma-som-rk3399-q7/
T: git git://git.embedded.cherry.de/puma-u-boot.git

7
board/theobroma-systems/ringneck_px30/MAINTAINERS
View File

@ -1,6 +1,6 @@
RINGNECK-PX30
M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
M: Klaus Goger <klaus.goger@theobroma-systems.com>
M: Quentin Schulz <quentin.schulz@cherry.de>
M: Klaus Goger <klaus.goger@cherry.de>
S: Maintained
F: board/theobroma-systems/ringneck_px30
F: board/theobroma-systems/common
@ -8,4 +8,5 @@ F: doc/board/theobroma-systems/
F: include/configs/ringneck_px30.h
F: arch/arm/dts/px30-ringneck*
F: configs/ringneck-px30_defconfig
W: https://theobroma-systems.com/product/ringneck-som-px30-uq7/
W: https://embedded.cherry.de/product/ringneck-som-px30-uq7/
T: git git://git.embedded.cherry.de/ringneck-u-boot.git

2
board/toradex/apalis-imx8/MAINTAINERS
View File

@ -1,5 +1,5 @@
Apalis iMX8
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
S: Maintained
F: arch/arm/dts/fsl-imx8qm-apalis.dts

2
board/toradex/apalis-tk1/MAINTAINERS
View File

@ -1,5 +1,5 @@
Apalis TK1
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
F: board/toradex/apalis-tk1/
F: board/toradex/common/

2
board/toradex/apalis_imx6/MAINTAINERS
View File

@ -1,5 +1,5 @@
Apalis iMX6
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained

2
board/toradex/apalis_t30/MAINTAINERS
View File

@ -1,5 +1,5 @@
Apalis T30
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
F: board/toradex/apalis_t30/
F: board/toradex/common/

2
board/toradex/colibri-imx6ull/MAINTAINERS
View File

@ -1,5 +1,5 @@
Colibri iMX6ULL
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained

2
board/toradex/colibri-imx8x/MAINTAINERS
View File

@ -1,5 +1,5 @@
Colibri iMX8X
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
S: Maintained
F: arch/arm/dts/fsl-imx8x-colibri.dts

2
board/toradex/colibri_imx6/MAINTAINERS
View File

@ -1,5 +1,5 @@
Colibri iMX6
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained

2
board/toradex/colibri_imx7/MAINTAINERS
View File

@ -1,5 +1,5 @@
Colibri iMX7
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained

2
board/toradex/colibri_t20/MAINTAINERS
View File

@ -1,5 +1,5 @@
COLIBRI_T20
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
F: board/toradex/colibri_t20/
F: board/toradex/common/

2
board/toradex/colibri_t30/MAINTAINERS
View File

@ -1,5 +1,5 @@
Colibri T30
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
F: board/toradex/colibri_t30/
F: board/toradex/common/

2
board/toradex/colibri_vf/MAINTAINERS
View File

@ -1,5 +1,5 @@
Colibri VFxx
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained

2
board/toradex/verdin-am62/MAINTAINERS
View File

@ -8,6 +8,6 @@ F: configs/verdin-am62_a53_defconfig
F: configs/verdin-am62_r5_defconfig
F: doc/board/toradex/verdin-am62.rst
F: include/configs/verdin-am62.h
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am-62

2
board/toradex/verdin-imx8mm/MAINTAINERS
View File

@ -1,5 +1,5 @@
Verdin iMX8M Mini
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini
S: Maintained
F: arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi

2
board/toradex/verdin-imx8mp/MAINTAINERS
View File

@ -5,6 +5,6 @@ F: board/toradex/common/
F: configs/verdin-imx8mp_defconfig
F: doc/board/toradex/verdin-imx8mp.rst
F: include/configs/verdin-imx8mp.h
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus

49
cmd/tpm-v2.c
View File

@ -98,11 +98,19 @@ static int do_tpm2_pcr_extend(struct cmd_tbl *cmdtp, int flag, int argc,
struct tpm_chip_priv *priv;
u32 index = simple_strtoul(argv[1], NULL, 0);
void *digest = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
int algo = TPM2_ALG_SHA256;
int algo_len;
int ret;
u32 rc;
if (argc != 3)
if (argc < 3 || argc > 4)
return CMD_RET_USAGE;
if (argc == 4) {
algo = tpm2_name_to_algorithm(argv[3]);
if (algo < 0)
return CMD_RET_FAILURE;
}
algo_len = tpm2_algorithm_to_len(algo);
ret = get_tpm(&dev);
if (ret)
@ -115,8 +123,12 @@ static int do_tpm2_pcr_extend(struct cmd_tbl *cmdtp, int flag, int argc,
if (index >= priv->pcr_count)
return -EINVAL;
rc = tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, digest,
TPM2_DIGEST_LEN);
rc = tpm2_pcr_extend(dev, index, algo, digest, algo_len);
if (!rc) {
printf("PCR #%u extended with %d byte %s digest\n", index,
algo_len, tpm2_algorithm_name(algo));
print_byte_string(digest, algo_len);
}
unmap_sysmem(digest);
@ -126,15 +138,23 @@ static int do_tpm2_pcr_extend(struct cmd_tbl *cmdtp, int flag, int argc,
static int do_tpm_pcr_read(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
enum tpm2_algorithms algo = TPM2_ALG_SHA256;
struct udevice *dev;
struct tpm_chip_priv *priv;
u32 index, rc;
int algo_len;
unsigned int updates;
void *data;
int ret;
if (argc != 3)
if (argc < 3 || argc > 4)
return CMD_RET_USAGE;
if (argc == 4) {
algo = tpm2_name_to_algorithm(argv[3]);
if (algo < 0)
return CMD_RET_FAILURE;
}
algo_len = tpm2_algorithm_to_len(algo);
ret = get_tpm(&dev);
if (ret)
@ -150,11 +170,12 @@ static int do_tpm_pcr_read(struct cmd_tbl *cmdtp, int flag, int argc,
data = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, TPM2_ALG_SHA256,
data, TPM2_DIGEST_LEN, &updates);
rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, algo,
data, algo_len, &updates);
if (!rc) {
printf("PCR #%u content (%u known updates):\n", index, updates);
print_byte_string(data, TPM2_DIGEST_LEN);
printf("PCR #%u %s %d byte content (%u known updates):\n", index,
tpm2_algorithm_name(algo), algo_len, updates);
print_byte_string(data, algo_len);
}
unmap_sysmem(data);
@ -414,14 +435,14 @@ U_BOOT_CMD(tpm2, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command",
" <hierarchy> is one of:\n"
" * TPM2_RH_LOCKOUT\n"
" * TPM2_RH_PLATFORM\n"
"pcr_extend <pcr> <digest_addr>\n"
" Extend PCR #<pcr> with digest at <digest_addr>.\n"
"pcr_extend <pcr> <digest_addr> [<digest_algo>]\n"
" Extend PCR #<pcr> with digest at <digest_addr> with digest_algo.\n"
" <pcr>: index of the PCR\n"
" <digest_addr>: address of a 32-byte SHA256 digest\n"
"pcr_read <pcr> <digest_addr>\n"
" Read PCR #<pcr> to memory address <digest_addr>.\n"
" <digest_addr>: address of digest of digest_algo type (defaults to SHA256)\n"
"pcr_read <pcr> <digest_addr> [<digest_algo>]\n"
" Read PCR #<pcr> to memory address <digest_addr> with <digest_algo>.\n"
" <pcr>: index of the PCR\n"
" <digest_addr>: address to store the a 32-byte SHA256 digest\n"
" <digest_addr>: address of digest of digest_algo type (defaults to SHA256)\n"
"get_capability <capability> <property> <addr> <count>\n"
" Read and display <count> entries indexed by <capability>/<property>.\n"
" Values are 4 bytes long and are written at <addr>.\n"

2
configs/e850-96_defconfig
View File

@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ARCH_EXYNOS9=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000
CONFIG_DEFAULT_DEVICE_TREE="exynos850-e850-96"
CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos850-e850-96"
CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_AUTOBOOT is not set
# CONFIG_DISPLAY_CPUINFO is not set

1
configs/evb-px30_defconfig
View File

@ -16,7 +16,6 @@ CONFIG_ROCKCHIP_PX30=y
CONFIG_TARGET_EVB_PX30=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

1
configs/firefly-px30_defconfig
View File

@ -17,7 +17,6 @@ CONFIG_TARGET_EVB_PX30=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

26
configs/igep00x0_defconfig
View File

@ -1,15 +1,18 @@
CONFIG_ARM=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_ENV_SIZE=0x8000
CONFIG_DEFAULT_DEVICE_TREE="omap3-igep0020"
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/omap3-igep0020"
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
@ -39,16 +42,7 @@ CONFIG_SPL_UBI_LEB_START=2048
CONFIG_SPL_UBI_INFO_ADDR=0x88080000
CONFIG_SPL_UBI_VOL_IDS=8
CONFIG_SPL_UBI_LOAD_MONITOR_ID=0
CONFIG_SPL_UBI_LOAD_KERNEL_ID=3
CONFIG_SPL_UBI_LOAD_ARGS_ID=4
CONFIG_SPL_ONENAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x84000000
CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
CONFIG_CMD_SPL=y
CONFIG_CMD_NAND=y
CONFIG_CMD_ONENAND=y
@ -58,7 +52,12 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_UBI=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
@ -68,6 +67,7 @@ CONFIG_ENV_UBI_VOLUME_REDUND="config_r"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_NET is not set
CONFIG_SPL_DM=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
@ -80,8 +80,6 @@ CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=3
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_BCH=y

2
configs/neu2-io-rv1126_defconfig
View File

@ -5,7 +5,7 @@ CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="rv1126-edgeble-neu2-io"
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1126-edgeble-neu2-io"
CONFIG_SYS_MONITOR_LEN=614400
CONFIG_ROCKCHIP_RV1126=y
CONFIG_TARGET_RV1126_NEU2=y

69
configs/nova-rk3588s_defconfig Normal file
View File

@ -0,0 +1,69 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-indiedroid-nova"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_NOVA_RK3588=y
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-indiedroid-nova.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_ERRNO_STR=y

1
configs/odroid-go2_defconfig
View File

@ -19,7 +19,6 @@ CONFIG_TARGET_ODROID_GO2=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

58
configs/powkiddy-x55-rk3566_defconfig Normal file
View File

@ -0,0 +1,58 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-powkiddy-x55"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-powkiddy-x55.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_ERRNO_STR=y

1
configs/px30-core-ctouch2-of10-px30_defconfig
View File

@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

1
configs/px30-core-ctouch2-px30_defconfig
View File

@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

1
configs/px30-core-edimm2.2-px30_defconfig
View File

@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

19
configs/ringneck-px30_defconfig
View File

@ -2,28 +2,15 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_RINGNECK_PX30=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@ -42,11 +29,11 @@ CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set

3
configs/rzg2_beacon_defconfig
View File

@ -3,7 +3,8 @@ CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_OFFSET=0x0
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-beacon-rzg2m-kit"
CONFIG_RCAR_GEN3=y

2
configs/sonoff-ihost-rv1126_defconfig
View File

@ -5,7 +5,7 @@ CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rv1126-sonoff-ihost"
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1126-sonoff-ihost"
CONFIG_SYS_MONITOR_LEN=614400
CONFIG_ROCKCHIP_RV1126=y
CONFIG_TARGET_RV1126_SONOFF_IHOST=y

2
doc/board/rockchip/rockchip.rst
View File

@ -104,6 +104,7 @@ List of mainline supported Rockchip boards:
- Pine64 SOQuartz on Blade (soquartz-blade-rk3566)
- Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566)
- Pine64 SOQuartz on Model A (soquartz-model-a-rk3566)
- Powkiddy X55 (powkiddy-x55-rk3566)
- Radxa CM3 IO Board (radxa-cm3-io-rk3566)
* rk3568
@ -123,6 +124,7 @@ List of mainline supported Rockchip boards:
- Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
- FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
- Generic RK3588S/RK3588 (generic-rk3588)
- Indiedroid Nova (nova-rk3588s)
- Pine64 QuartzPro64 (quartzpro64-rk3588)
- Radxa ROCK 5A (rock5a-rk3588s)
- Radxa ROCK 5B (rock5b-rk3588)

1
doc/board/starfive/index.rst
View File

@ -8,4 +8,5 @@ StarFive
milk-v_mars
milk-v_mars_cm
pine64_star64
visionfive2

201
doc/board/starfive/pine64_star64.rst Normal file
View File

@ -0,0 +1,201 @@
.. SPDX-License-Identifier: GPL-2.0+
Pine64 Star64
=============
U-Boot for the Star64 uses the same U-Boot binaries as the VisionFive 2 board.
In U-Boot SPL the actual board is detected and the device-tree patched
accordingly.
Building
~~~~~~~~
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
.. code-block:: none
export CROSS_COMPILE=<riscv64 toolchain prefix>
The M-mode software OpenSBI provides the supervisor binary interface (SBI) and
is responsible for the switch to S-Mode. It is a prerequisite to build U-Boot.
Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended to use
a current release.
.. code-block:: console
git clone https://github.com/riscv/opensbi.git
cd opensbi
make PLATFORM=generic FW_TEXT_START=0x40000000
Now build the U-Boot SPL and U-Boot proper.
.. code-block:: console
cd <U-Boot-dir>
make starfive_visionfive2_defconfig
make OPENSBI=$(opensbi_dir)/build/platform/generic/firmware/fw_dynamic.bin
This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well
as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
Device-tree selection
~~~~~~~~~~~~~~~~~~~~~
U-Boot will set variable $fdtfile to starfive/jh7110-pine64-star64.dtb.
To overrule this selection the variable can be set manually and saved in the
environment
::
env set fdtfile my_device-tree.dtb
env save
or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to
provide a default value.
Boot source selection
~~~~~~~~~~~~~~~~~~~~~
Boot mode is selected by an MSEL-DIP marked S1804 and GPIO_0 position adjacent
to the 40pin GPIO header. ON/ONKE and number markings of the MSEL-DIP are
misleading; Instead refer to the ``L`` (0) and ``H`` (1) silkscreen for
accurate selection.
+ (QSPI) Flash: 00
+ SD: 01
+ EMMC: 10
+ UART: 11
Preparing the SD-Card
~~~~~~~~~~~~~~~~~~~~~
The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
to choose any partition number.
With the default configuration U-Boot SPL loads the U-Boot FIT image
(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2).
When formatting it is recommended to use GUID
BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition.
The FIT image (u-boot.itb) is a combination of OpenSBI's fw_dynamic.bin,
u-boot-nodtb.bin and the device tree blob.
Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
.. code-block:: bash
sudo sgdisk --clear \
--set-alignment=2 \
--new=1:4096:8191 --change-name=1:spl --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985\
--new=2:8192:16383 --change-name=2:uboot --typecode=2:BC13C2FF-59E6-4262-A352-B275FD6F7172 \
--new=3:16384:1654784 --change-name=3:system --typecode=3:EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 \
/dev/sdb
Copy U-Boot to the SD card
.. code-block:: bash
sudo dd if=u-boot-spl.bin.normal.out of=/dev/sdb1
sudo dd if=u-boot.itb of=/dev/sdb2
sudo mount /dev/sdb3 /mnt/
sudo cp u-boot-spl.bin.normal.out /mnt/
sudo cp u-boot.itb /mnt/
sudo cp Image.gz /mnt/
sudo cp initramfs.cpio.gz /mnt/
sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
Booting
~~~~~~~
Once you plugin the sdcard and power up, you should see the U-Boot prompt.
Serial Number and MAC address issues
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
U-Boot requires valid EEPROM data to determine which board-specific fix-up to
apply at runtime. This affects the size of memory initialized, network mac
address numbering, and tuning of the network PHYs.
The Star64 does not currently ship with unique serial numbers per-device.
Devices follow a pattern where the last mac address bytes are a sum of 0x7558
and the serial number (lower port mac0), or a sum of 0x7559 and the serial
number (upper port mac1).
As tested there are several 4gb model units where the serial number and network
mac addresses collide with other devices (serial
``STAR64V1-2310-D004E000-00000005``, MACs ``6c:cf:39:00:75:61``,
``6c:cf:39:00:75:62``)
Some early Star64 boards shipped with an uninitialized EEPROM and no write
protect pull-up resistor in place. Later units of all 4gb and 8gb models
sharing the same serial number in EEPROM data will have this problem that the
network mac addresses are alike between different models and this may be
corrected by defeating the write protect resistor to write new values. As an
alternative to this, it may be worked around by overriding the mac addresses
via U-Boot environment variables.
It is required for any unit having uninitialized EEPROM and recommended for
all later Star64 4gb model units (not properly serialized) to have decided on a
new 6-byte serial number. This serial number should be high enough to
avoid collision with other JH7110 boards and low enough not to overflow i.e.
between ``cafe00`` and ``f00d00``.
Update EEPROM values
^^^^^^^^^^^^^^^^^^^^
1. Prepare EEPROM data in memory
::
## When there is no error to load existing data:
mac read_eeprom
## When there is an error to load non-existing data:
# "DRAM: Not a StarFive EEPROM data format - magic error"
mac initialize
2. Set Star64 values
::
## Common values
mac vendor PINE64
mac pcb_revision c1
mac bom_revision A
## Device-specific values
# Year 2023 week 10 production date, 8GB DRAM, optional eMMC, serial cdef01
mac product_id STAR64V1-2310-D008E000-00cdef01
# Last three bytes mac0: 0x7558 + serial number 0xcdef01
mac mac0_address 6c:cf:39:ce:64:59
# Last three bytes mac1: 0x7559 + serial number 0xcdef01
mac mac1_address 6c:cf:39:ce:64:5a
3. Defeat write-protect pull-up resistor (if installed) and write to EEPROM
::
mac write_eeprom
Set Variables in U-Boot
^^^^^^^^^^^^^^^^^^^^^^^
.. note:: Changing just the serial number will not alter your MAC address
The MAC addresses may be "set" as follows by writing as a custom config to SPI
(Change the last 3 bytes of MAC addreses as appropriate):
::
env set serial# STAR64V1-2310-D008E000-00cdef01
env set ethaddr 6c:cf:39:ce:64:59
env set eth1addr 6c:cf:39:ce:64:5a
env save
reset

2
doc/develop/release_cycle.rst
View File

@ -73,7 +73,7 @@ For the next scheduled release, release candidates were made on::
* U-Boot v2024.07-rc3 was released on Mon 20 May 2024.
.. * U-Boot v2024.07-rc4 was released on Mon 03 June 2024.
* U-Boot v2024.07-rc4 was released on Mon 03 June 2024.
.. * U-Boot v2024.07-rc5 was released on Mon 17 June 2024.

307
doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
View File

@ -1,307 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos850 SoC clock controller
maintainers:
- Sam Protsenko <semen.protsenko@linaro.org>
description: |
Exynos850 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. Root clocks in that clock tree are
two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
clocks must be defined as fixed-rate clocks in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'dt-bindings/clock/exynos850.h' header.
properties:
compatible:
enum:
- samsung,exynos850-cmu-top
- samsung,exynos850-cmu-apm
- samsung,exynos850-cmu-aud
- samsung,exynos850-cmu-cmgp
- samsung,exynos850-cmu-core
- samsung,exynos850-cmu-dpu
- samsung,exynos850-cmu-g3d
- samsung,exynos850-cmu-hsi
- samsung,exynos850-cmu-is
- samsung,exynos850-cmu-mfcmscl
- samsung,exynos850-cmu-peri
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
"#clock-cells":
const: 1
reg:
maxItems: 1
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-top
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
clock-names:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-apm
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_APM bus clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_apm_bus
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-aud
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: AUD clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_aud
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-cmgp
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_CMGP bus clock (from CMU_APM)
clock-names:
items:
- const: oscclk
- const: gout_clkcmu_cmgp_bus
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-core
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_CORE bus clock (from CMU_TOP)
- description: CCI clock (from CMU_TOP)
- description: eMMC clock (from CMU_TOP)
- description: SSS clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_core_bus
- const: dout_core_cci
- const: dout_core_mmc_embd
- const: dout_core_sss
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-dpu
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: DPU clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_dpu
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-g3d
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: G3D clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_g3d_switch
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-hsi
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: External RTC clock (32768 Hz)
- description: CMU_HSI bus clock (from CMU_TOP)
- description: SD card clock (from CMU_TOP)
- description: USB 2.0 DRD clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: rtcclk
- const: dout_hsi_bus
- const: dout_hsi_mmc_card
- const: dout_hsi_usb20drd
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-is
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_IS bus clock (from CMU_TOP)
- description: Image Texture Processing core clock (from CMU_TOP)
- description: Visual Recognition Accelerator clock (from CMU_TOP)
- description: Geometric Distortion Correction clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_is_bus
- const: dout_is_itp
- const: dout_is_vra
- const: dout_is_gdc
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-mfcmscl
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: Multi-Format Codec clock (from CMU_TOP)
- description: Memory to Memory Scaler clock (from CMU_TOP)
- description: Multi-Channel Scaler clock (from CMU_TOP)
- description: JPEG codec clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_mfcmscl_mfc
- const: dout_mfcmscl_m2m
- const: dout_mfcmscl_mcsc
- const: dout_mfcmscl_jpeg
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-peri
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERI bus clock (from CMU_TOP)
- description: UART clock (from CMU_TOP)
- description: Parent clock for HSI2C and SPI (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_peri_bus
- const: dout_peri_uart
- const: dout_peri_ip
required:
- compatible
- "#clock-cells"
- clocks
- clock-names
- reg
additionalProperties: false
examples:
# Clock controller node for CMU_PERI
- |
#include <dt-bindings/clock/exynos850.h>
cmu_peri: clock-controller@10030000 {
compatible = "samsung,exynos850-cmu-peri";
reg = <0x10030000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
<&cmu_top CLK_DOUT_PERI_UART>,
<&cmu_top CLK_DOUT_PERI_IP>;
clock-names = "oscclk", "dout_peri_bus",
"dout_peri_uart", "dout_peri_ip";
};
...

162
doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
View File

@ -1,162 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung's Exynos USI (Universal Serial Interface)
maintainers:
- Sam Protsenko <semen.protsenko@linaro.org>
description: |
USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
USI shares almost all internal circuits within each protocol, so only one
protocol can be chosen at a time. USI is modeled as a node with zero or more
child nodes, each representing a serial sub-node device. The mode setting
selects which particular function will be used.
properties:
$nodename:
pattern: "^usi@[0-9a-f]+$"
compatible:
enum:
- samsung,exynos850-usi
reg: true
clocks: true
clock-names: true
ranges: true
"#address-cells":
const: 1
"#size-cells":
const: 1
samsung,sysreg:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to System Register syscon node
- description: offset of SW_CONF register for this USI controller
description:
Should be phandle/offset pair. The phandle to System Register syscon node
(for the same domain where this USI controller resides) and the offset
of SW_CONF register for this USI controller.
samsung,mode:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Selects USI function (which serial protocol to use). Refer to
<include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
samsung,clkreq-on:
type: boolean
description:
Enable this property if underlying protocol requires the clock to be
continuously provided without automatic gating. As suggested by SoC
manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
multi-master mode. Usually this property is needed if USI mode is set
to "UART".
This property is optional.
patternProperties:
"^i2c@[0-9a-f]+$":
$ref: /schemas/i2c/i2c-exynos5.yaml
description: Child node describing underlying I2C
"^serial@[0-9a-f]+$":
$ref: /schemas/serial/samsung_uart.yaml
description: Child node describing underlying UART/serial
"^spi@[0-9a-f]+$":
$ref: /schemas/spi/samsung,spi.yaml
description: Child node describing underlying SPI
required:
- compatible
- ranges
- "#address-cells"
- "#size-cells"
- samsung,sysreg
- samsung,mode
if:
properties:
compatible:
contains:
enum:
- samsung,exynos850-usi
then:
properties:
reg:
maxItems: 1
clocks:
items:
- description: Bus (APB) clock
- description: Operating clock for UART/SPI/I2C protocol
clock-names:
items:
- const: pclk
- const: ipclk
required:
- reg
- clocks
- clock-names
else:
properties:
reg: false
clocks: false
clock-names: false
samsung,clkreq-on: false
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/samsung,exynos-usi.h>
usi0: usi@138200c0 {
compatible = "samsung,exynos850-usi";
reg = <0x138200c0 0x20>;
samsung,sysreg = <&sysreg_peri 0x1010>;
samsung,mode = <USI_V2_UART>;
samsung,clkreq-on; /* needed for UART mode */
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_peri 32>, <&cmu_peri 31>;
clock-names = "pclk", "ipclk";
serial_0: serial@13820000 {
compatible = "samsung,exynos850-uart";
reg = <0x13820000 0xc0>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peri 32>, <&cmu_peri 31>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
hsi2c_0: i2c@13820000 {
compatible = "samsung,exynosautov9-hsi2c";
reg = <0x13820000 0xc0>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_peri 31>, <&cmu_peri 32>;
clock-names = "hsi2c", "hsi2c_pclk";
status = "disabled";
};
};

8
drivers/cache/cache-andes-l2.c vendored
View File

@ -29,7 +29,7 @@ struct l2cache {
volatile u64 cctl_command2;
volatile u64 cctl_access_line2;
volatile u64 cctl_command3;
volatile u64 cctl_access_line4;
volatile u64 cctl_access_line3;
volatile u64 cctl_status;
};
@ -96,13 +96,15 @@ static int andes_l2_disable(struct udevice *dev)
struct andes_l2_plat *plat = dev_get_plat(dev);
volatile struct l2cache *regs = plat->regs;
u8 hart = gd->arch.boot_hart;
void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
void __iomem *cctlstatus = (void __iomem *)CCTL_STATUS_REG(regs, hart);
if ((regs) && (readl(&regs->control) & L2_ENABLE)) {
writel(L2_WBINVAL_ALL, cctlcmd);
while ((readl(&regs->cctl_status) & CCTL_STATUS_MSK(hart))) {
if ((readl(&regs->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
while ((readl(cctlstatus) & CCTL_STATUS_MSK(hart))) {
if ((readl(cctlstatus) & CCTL_STATUS_ILLEGAL(hart))) {
printf("L2 flush illegal! hanging...");
hang();
}

30
drivers/clk/rockchip/clk_rk3588.c
View File

@ -36,6 +36,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
RK3588_PLL_RATE(742500000, 4, 495, 2, 0),
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
RK3588_PLL_RATE(702000000, 3, 351, 2, 0),
RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
RK3588_PLL_RATE(200000000, 3, 400, 4, 0),
@ -64,6 +65,15 @@ static struct rockchip_pll_clock rk3588_pll_clks[] = {
RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
[PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
#ifdef CONFIG_SPL_BUILD
/*
* The SPLL is part of the SBUSCRU, not the main CRU and as
* such only directly accessible during the SPL stage.
*/
[SPLL] = PLL(pll_rk3588, 0, RK3588_SBUSCRU_SPLL_CON(0),
RK3588_SBUSCRU_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
#endif
};
#ifndef CONFIG_SPL_BUILD
@ -2043,6 +2053,7 @@ U_BOOT_DRIVER(rockchip_rk3588_cru) = {
#ifdef CONFIG_SPL_BUILD
#define SCRU_BASE 0xfd7d0000
#define SBUSCRU_BASE 0xfd7d8000
static ulong rk3588_scru_clk_get_rate(struct clk *clk)
{
@ -2117,15 +2128,28 @@ static ulong rk3588_scru_clk_set_rate(struct clk *clk, ulong rate)
return rk3588_scru_clk_get_rate(clk);
}
static int rk3588_scru_clk_probe(struct udevice *dev)
{
int ret;
ret = rockchip_pll_set_rate(&rk3588_pll_clks[SPLL],
(void *)SBUSCRU_BASE, SPLL, SPLL_HZ);
if (ret)
debug("%s setting spll rate failed %d\n", __func__, ret);
return 0;
}
static const struct clk_ops rk3588_scru_clk_ops = {
.get_rate = rk3588_scru_clk_get_rate,
.set_rate = rk3588_scru_clk_set_rate,
};
U_BOOT_DRIVER(rockchip_rk3588_scru) = {
.name = "rockchip_rk3588_scru",
.id = UCLASS_CLK,
.ops = &rk3588_scru_clk_ops,
.name = "rockchip_rk3588_scru",
.id = UCLASS_CLK,
.ops = &rk3588_scru_clk_ops,
.probe = rk3588_scru_clk_probe,
};
static int rk3588_scmi_spl_glue_bind(struct udevice *dev)

21
drivers/tpm/tpm2_tis_spi.c
View File

@ -237,19 +237,22 @@ static int tpm_tis_spi_probe(struct udevice *dev)
/* legacy reset */
ret = gpio_request_by_name(dev, "gpio-reset", 0,
&reset_gpio, GPIOD_IS_OUT);
if (ret) {
if (!ret) {
log(LOGC_NONE, LOGL_NOTICE,
"%s: missing reset GPIO\n", __func__);
goto init;
"%s: gpio-reset is deprecated\n", __func__);
}
log(LOGC_NONE, LOGL_NOTICE,
"%s: gpio-reset is deprecated\n", __func__);
}
dm_gpio_set_value(&reset_gpio, 1);
mdelay(1);
dm_gpio_set_value(&reset_gpio, 0);
if (!ret) {
log(LOGC_NONE, LOGL_WARNING,
"%s: TPM gpio reset should not be used on secure production devices\n",
dev->name);
dm_gpio_set_value(&reset_gpio, 1);
mdelay(1);
dm_gpio_set_value(&reset_gpio, 0);
}
}
init:
/* Ensure a minimum amount of time elapsed since reset of the TPM */
mdelay(drv_data->time_before_first_cmd_ms);

4
dts/upstream/src/arm64/Makefile
View File

@ -7,6 +7,10 @@ targets += $(dtb-y)
# Add any required device tree compiler flags here
DTC_FLAGS += -a 0x8
ifdef CONFIG_RCAR_64
DTC_FLAGS += -R 4 -p 0x1000
endif
PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:

15
include/configs/nova-rk3588s.h Normal file
View File

@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2022 Collabora Ltd.
*/
#ifndef __NOVA_RK3588S_H
#define __NOVA_RK3588S_H
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#include <configs/rk3588_common.h>
#endif /* __NOVA_RK3588S_H */

12
include/configs/powkiddy-x55-rk3566.h Normal file
View File

@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __POWKIDDY_X55_RK3566_H
#define __POWKIDDY_X55_RK3566_H
#include <configs/rk3568_common.h>
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#endif

337
include/dt-bindings/clock/exynos850.h
View File

@ -1,337 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2021 Linaro Ltd.
* Author: Sam Protsenko <semen.protsenko@linaro.org>
*
* Device Tree binding constants for Exynos850 clock controller.
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H
#define _DT_BINDINGS_CLOCK_EXYNOS_850_H
/* CMU_TOP */
#define CLK_FOUT_SHARED0_PLL 1
#define CLK_FOUT_SHARED1_PLL 2
#define CLK_FOUT_MMC_PLL 3
#define CLK_MOUT_SHARED0_PLL 4
#define CLK_MOUT_SHARED1_PLL 5
#define CLK_MOUT_MMC_PLL 6
#define CLK_MOUT_CORE_BUS 7
#define CLK_MOUT_CORE_CCI 8
#define CLK_MOUT_CORE_MMC_EMBD 9
#define CLK_MOUT_CORE_SSS 10
#define CLK_MOUT_DPU 11
#define CLK_MOUT_HSI_BUS 12
#define CLK_MOUT_HSI_MMC_CARD 13
#define CLK_MOUT_HSI_USB20DRD 14
#define CLK_MOUT_PERI_BUS 15
#define CLK_MOUT_PERI_UART 16
#define CLK_MOUT_PERI_IP 17
#define CLK_DOUT_SHARED0_DIV3 18
#define CLK_DOUT_SHARED0_DIV2 19
#define CLK_DOUT_SHARED1_DIV3 20
#define CLK_DOUT_SHARED1_DIV2 21
#define CLK_DOUT_SHARED0_DIV4 22
#define CLK_DOUT_SHARED1_DIV4 23
#define CLK_DOUT_CORE_BUS 24
#define CLK_DOUT_CORE_CCI 25
#define CLK_DOUT_CORE_MMC_EMBD 26
#define CLK_DOUT_CORE_SSS 27
#define CLK_DOUT_DPU 28
#define CLK_DOUT_HSI_BUS 29
#define CLK_DOUT_HSI_MMC_CARD 30
#define CLK_DOUT_HSI_USB20DRD 31
#define CLK_DOUT_PERI_BUS 32
#define CLK_DOUT_PERI_UART 33
#define CLK_DOUT_PERI_IP 34
#define CLK_GOUT_CORE_BUS 35
#define CLK_GOUT_CORE_CCI 36
#define CLK_GOUT_CORE_MMC_EMBD 37
#define CLK_GOUT_CORE_SSS 38
#define CLK_GOUT_DPU 39
#define CLK_GOUT_HSI_BUS 40
#define CLK_GOUT_HSI_MMC_CARD 41
#define CLK_GOUT_HSI_USB20DRD 42
#define CLK_GOUT_PERI_BUS 43
#define CLK_GOUT_PERI_UART 44
#define CLK_GOUT_PERI_IP 45
#define CLK_MOUT_CLKCMU_APM_BUS 46
#define CLK_DOUT_CLKCMU_APM_BUS 47
#define CLK_GOUT_CLKCMU_APM_BUS 48
#define CLK_MOUT_AUD 49
#define CLK_GOUT_AUD 50
#define CLK_DOUT_AUD 51
#define CLK_MOUT_IS_BUS 52
#define CLK_MOUT_IS_ITP 53
#define CLK_MOUT_IS_VRA 54
#define CLK_MOUT_IS_GDC 55
#define CLK_GOUT_IS_BUS 56
#define CLK_GOUT_IS_ITP 57
#define CLK_GOUT_IS_VRA 58
#define CLK_GOUT_IS_GDC 59
#define CLK_DOUT_IS_BUS 60
#define CLK_DOUT_IS_ITP 61
#define CLK_DOUT_IS_VRA 62
#define CLK_DOUT_IS_GDC 63
#define CLK_MOUT_MFCMSCL_MFC 64
#define CLK_MOUT_MFCMSCL_M2M 65
#define CLK_MOUT_MFCMSCL_MCSC 66
#define CLK_MOUT_MFCMSCL_JPEG 67
#define CLK_GOUT_MFCMSCL_MFC 68
#define CLK_GOUT_MFCMSCL_M2M 69
#define CLK_GOUT_MFCMSCL_MCSC 70
#define CLK_GOUT_MFCMSCL_JPEG 71
#define CLK_DOUT_MFCMSCL_MFC 72
#define CLK_DOUT_MFCMSCL_M2M 73
#define CLK_DOUT_MFCMSCL_MCSC 74
#define CLK_DOUT_MFCMSCL_JPEG 75
#define CLK_MOUT_G3D_SWITCH 76
#define CLK_GOUT_G3D_SWITCH 77
#define CLK_DOUT_G3D_SWITCH 78
/* CMU_APM */
#define CLK_RCO_I3C_PMIC 1
#define OSCCLK_RCO_APM 2
#define CLK_RCO_APM__ALV 3
#define CLK_DLL_DCO 4
#define CLK_MOUT_APM_BUS_USER 5
#define CLK_MOUT_RCO_APM_I3C_USER 6
#define CLK_MOUT_RCO_APM_USER 7
#define CLK_MOUT_DLL_USER 8
#define CLK_MOUT_CLKCMU_CHUB_BUS 9
#define CLK_MOUT_APM_BUS 10
#define CLK_MOUT_APM_I3C 11
#define CLK_DOUT_CLKCMU_CHUB_BUS 12
#define CLK_DOUT_APM_BUS 13
#define CLK_DOUT_APM_I3C 14
#define CLK_GOUT_CLKCMU_CMGP_BUS 15
#define CLK_GOUT_CLKCMU_CHUB_BUS 16
#define CLK_GOUT_RTC_PCLK 17
#define CLK_GOUT_TOP_RTC_PCLK 18
#define CLK_GOUT_I3C_PCLK 19
#define CLK_GOUT_I3C_SCLK 20
#define CLK_GOUT_SPEEDY_PCLK 21
#define CLK_GOUT_GPIO_ALIVE_PCLK 22
#define CLK_GOUT_PMU_ALIVE_PCLK 23
#define CLK_GOUT_SYSREG_APM_PCLK 24
/* CMU_AUD */
#define CLK_DOUT_AUD_AUDIF 1
#define CLK_DOUT_AUD_BUSD 2
#define CLK_DOUT_AUD_BUSP 3
#define CLK_DOUT_AUD_CNT 4
#define CLK_DOUT_AUD_CPU 5
#define CLK_DOUT_AUD_CPU_ACLK 6
#define CLK_DOUT_AUD_CPU_PCLKDBG 7
#define CLK_DOUT_AUD_FM 8
#define CLK_DOUT_AUD_FM_SPDY 9
#define CLK_DOUT_AUD_MCLK 10
#define CLK_DOUT_AUD_UAIF0 11
#define CLK_DOUT_AUD_UAIF1 12
#define CLK_DOUT_AUD_UAIF2 13
#define CLK_DOUT_AUD_UAIF3 14
#define CLK_DOUT_AUD_UAIF4 15
#define CLK_DOUT_AUD_UAIF5 16
#define CLK_DOUT_AUD_UAIF6 17
#define CLK_FOUT_AUD_PLL 18
#define CLK_GOUT_AUD_ABOX_ACLK 19
#define CLK_GOUT_AUD_ASB_CCLK 20
#define CLK_GOUT_AUD_CA32_CCLK 21
#define CLK_GOUT_AUD_CNT_BCLK 22
#define CLK_GOUT_AUD_CODEC_MCLK 23
#define CLK_GOUT_AUD_DAP_CCLK 24
#define CLK_GOUT_AUD_GPIO_PCLK 25
#define CLK_GOUT_AUD_PPMU_ACLK 26
#define CLK_GOUT_AUD_PPMU_PCLK 27
#define CLK_GOUT_AUD_SPDY_BCLK 28
#define CLK_GOUT_AUD_SYSMMU_CLK 29
#define CLK_GOUT_AUD_SYSREG_PCLK 30
#define CLK_GOUT_AUD_TZPC_PCLK 31
#define CLK_GOUT_AUD_UAIF0_BCLK 32
#define CLK_GOUT_AUD_UAIF1_BCLK 33
#define CLK_GOUT_AUD_UAIF2_BCLK 34
#define CLK_GOUT_AUD_UAIF3_BCLK 35
#define CLK_GOUT_AUD_UAIF4_BCLK 36
#define CLK_GOUT_AUD_UAIF5_BCLK 37
#define CLK_GOUT_AUD_UAIF6_BCLK 38
#define CLK_GOUT_AUD_WDT_PCLK 39
#define CLK_MOUT_AUD_CPU 40
#define CLK_MOUT_AUD_CPU_HCH 41
#define CLK_MOUT_AUD_CPU_USER 42
#define CLK_MOUT_AUD_FM 43
#define CLK_MOUT_AUD_PLL 44
#define CLK_MOUT_AUD_TICK_USB_USER 45
#define CLK_MOUT_AUD_UAIF0 46
#define CLK_MOUT_AUD_UAIF1 47
#define CLK_MOUT_AUD_UAIF2 48
#define CLK_MOUT_AUD_UAIF3 49
#define CLK_MOUT_AUD_UAIF4 50
#define CLK_MOUT_AUD_UAIF5 51
#define CLK_MOUT_AUD_UAIF6 52
#define IOCLK_AUDIOCDCLK0 53
#define IOCLK_AUDIOCDCLK1 54
#define IOCLK_AUDIOCDCLK2 55
#define IOCLK_AUDIOCDCLK3 56
#define IOCLK_AUDIOCDCLK4 57
#define IOCLK_AUDIOCDCLK5 58
#define IOCLK_AUDIOCDCLK6 59
#define TICK_USB 60
#define CLK_GOUT_AUD_CMU_AUD_PCLK 61
/* CMU_CMGP */
#define CLK_RCO_CMGP 1
#define CLK_MOUT_CMGP_ADC 2
#define CLK_MOUT_CMGP_USI0 3
#define CLK_MOUT_CMGP_USI1 4
#define CLK_DOUT_CMGP_ADC 5
#define CLK_DOUT_CMGP_USI0 6
#define CLK_DOUT_CMGP_USI1 7
#define CLK_GOUT_CMGP_ADC_S0_PCLK 8
#define CLK_GOUT_CMGP_ADC_S1_PCLK 9
#define CLK_GOUT_CMGP_GPIO_PCLK 10
#define CLK_GOUT_CMGP_USI0_IPCLK 11
#define CLK_GOUT_CMGP_USI0_PCLK 12
#define CLK_GOUT_CMGP_USI1_IPCLK 13
#define CLK_GOUT_CMGP_USI1_PCLK 14
#define CLK_GOUT_SYSREG_CMGP_PCLK 15
/* CMU_G3D */
#define CLK_FOUT_G3D_PLL 1
#define CLK_MOUT_G3D_PLL 2
#define CLK_MOUT_G3D_SWITCH_USER 3
#define CLK_MOUT_G3D_BUSD 4
#define CLK_DOUT_G3D_BUSP 5
#define CLK_GOUT_G3D_CMU_G3D_PCLK 6
#define CLK_GOUT_G3D_GPU_CLK 7
#define CLK_GOUT_G3D_TZPC_PCLK 8
#define CLK_GOUT_G3D_GRAY2BIN_CLK 9
#define CLK_GOUT_G3D_BUSD_CLK 10
#define CLK_GOUT_G3D_BUSP_CLK 11
#define CLK_GOUT_G3D_SYSREG_PCLK 12
/* CMU_HSI */
#define CLK_MOUT_HSI_BUS_USER 1
#define CLK_MOUT_HSI_MMC_CARD_USER 2
#define CLK_MOUT_HSI_USB20DRD_USER 3
#define CLK_MOUT_HSI_RTC 4
#define CLK_GOUT_USB_RTC_CLK 5
#define CLK_GOUT_USB_REF_CLK 6
#define CLK_GOUT_USB_PHY_REF_CLK 7
#define CLK_GOUT_USB_PHY_ACLK 8
#define CLK_GOUT_USB_BUS_EARLY_CLK 9
#define CLK_GOUT_GPIO_HSI_PCLK 10
#define CLK_GOUT_MMC_CARD_ACLK 11
#define CLK_GOUT_MMC_CARD_SDCLKIN 12
#define CLK_GOUT_SYSREG_HSI_PCLK 13
#define CLK_GOUT_HSI_PPMU_ACLK 14
#define CLK_GOUT_HSI_PPMU_PCLK 15
#define CLK_GOUT_HSI_CMU_HSI_PCLK 16
/* CMU_IS */
#define CLK_MOUT_IS_BUS_USER 1
#define CLK_MOUT_IS_ITP_USER 2
#define CLK_MOUT_IS_VRA_USER 3
#define CLK_MOUT_IS_GDC_USER 4
#define CLK_DOUT_IS_BUSP 5
#define CLK_GOUT_IS_CMU_IS_PCLK 6
#define CLK_GOUT_IS_CSIS0_ACLK 7
#define CLK_GOUT_IS_CSIS1_ACLK 8
#define CLK_GOUT_IS_CSIS2_ACLK 9
#define CLK_GOUT_IS_TZPC_PCLK 10
#define CLK_GOUT_IS_CSIS_DMA_CLK 11
#define CLK_GOUT_IS_GDC_CLK 12
#define CLK_GOUT_IS_IPP_CLK 13
#define CLK_GOUT_IS_ITP_CLK 14
#define CLK_GOUT_IS_MCSC_CLK 15
#define CLK_GOUT_IS_VRA_CLK 16
#define CLK_GOUT_IS_PPMU_IS0_ACLK 17
#define CLK_GOUT_IS_PPMU_IS0_PCLK 18
#define CLK_GOUT_IS_PPMU_IS1_ACLK 19
#define CLK_GOUT_IS_PPMU_IS1_PCLK 20
#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
#define CLK_GOUT_IS_SYSREG_PCLK 23
/* CMU_MFCMSCL */
#define CLK_MOUT_MFCMSCL_MFC_USER 1
#define CLK_MOUT_MFCMSCL_M2M_USER 2
#define CLK_MOUT_MFCMSCL_MCSC_USER 3
#define CLK_MOUT_MFCMSCL_JPEG_USER 4
#define CLK_DOUT_MFCMSCL_BUSP 5
#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6
#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7
#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8
#define CLK_GOUT_MFCMSCL_M2M_ACLK 9
#define CLK_GOUT_MFCMSCL_MCSC_CLK 10
#define CLK_GOUT_MFCMSCL_MFC_ACLK 11
#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12
#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13
#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14
#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15
/* CMU_PERI */
#define CLK_MOUT_PERI_BUS_USER 1
#define CLK_MOUT_PERI_UART_USER 2
#define CLK_MOUT_PERI_HSI2C_USER 3
#define CLK_MOUT_PERI_SPI_USER 4
#define CLK_DOUT_PERI_HSI2C0 5
#define CLK_DOUT_PERI_HSI2C1 6
#define CLK_DOUT_PERI_HSI2C2 7
#define CLK_DOUT_PERI_SPI0 8
#define CLK_GOUT_PERI_HSI2C0 9
#define CLK_GOUT_PERI_HSI2C1 10
#define CLK_GOUT_PERI_HSI2C2 11
#define CLK_GOUT_GPIO_PERI_PCLK 12
#define CLK_GOUT_HSI2C0_IPCLK 13
#define CLK_GOUT_HSI2C0_PCLK 14
#define CLK_GOUT_HSI2C1_IPCLK 15
#define CLK_GOUT_HSI2C1_PCLK 16
#define CLK_GOUT_HSI2C2_IPCLK 17
#define CLK_GOUT_HSI2C2_PCLK 18
#define CLK_GOUT_I2C0_PCLK 19
#define CLK_GOUT_I2C1_PCLK 20
#define CLK_GOUT_I2C2_PCLK 21
#define CLK_GOUT_I2C3_PCLK 22
#define CLK_GOUT_I2C4_PCLK 23
#define CLK_GOUT_I2C5_PCLK 24
#define CLK_GOUT_I2C6_PCLK 25
#define CLK_GOUT_MCT_PCLK 26
#define CLK_GOUT_PWM_MOTOR_PCLK 27
#define CLK_GOUT_SPI0_IPCLK 28
#define CLK_GOUT_SPI0_PCLK 29
#define CLK_GOUT_SYSREG_PERI_PCLK 30
#define CLK_GOUT_UART_IPCLK 31
#define CLK_GOUT_UART_PCLK 32
#define CLK_GOUT_WDT0_PCLK 33
#define CLK_GOUT_WDT1_PCLK 34
/* CMU_CORE */
#define CLK_MOUT_CORE_BUS_USER 1
#define CLK_MOUT_CORE_CCI_USER 2
#define CLK_MOUT_CORE_MMC_EMBD_USER 3
#define CLK_MOUT_CORE_SSS_USER 4
#define CLK_MOUT_CORE_GIC 5
#define CLK_DOUT_CORE_BUSP 6
#define CLK_GOUT_CCI_ACLK 7
#define CLK_GOUT_GIC_CLK 8
#define CLK_GOUT_MMC_EMBD_ACLK 9
#define CLK_GOUT_MMC_EMBD_SDCLKIN 10
#define CLK_GOUT_SSS_ACLK 11
#define CLK_GOUT_SSS_PCLK 12
#define CLK_GOUT_GPIO_CORE_PCLK 13
#define CLK_GOUT_SYSREG_CORE_PCLK 14
/* CMU_DPU */
#define CLK_MOUT_DPU_USER 1
#define CLK_DOUT_DPU_BUSP 2
#define CLK_GOUT_DPU_CMU_DPU_PCLK 3
#define CLK_GOUT_DPU_DECON0_ACLK 4
#define CLK_GOUT_DPU_DMA_ACLK 5
#define CLK_GOUT_DPU_DPP_ACLK 6
#define CLK_GOUT_DPU_PPMU_ACLK 7
#define CLK_GOUT_DPU_PPMU_PCLK 8
#define CLK_GOUT_DPU_SMMU_CLK 9
#define CLK_GOUT_DPU_SYSREG_PCLK 10
#define DPU_NR_CLK 11
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */

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include/dt-bindings/clock/rockchip,rv1126-cru.h
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@ -1,632 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2019 Rockchip Electronics Co. Ltd.
* Author: Finley Xiao <finley.xiao@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
/* pmucru-clocks indices */
/* pll clocks */
#define PLL_GPLL 1
/* sclk (special clocks) */
#define CLK_OSC0_DIV32K 2
#define CLK_RTC32K 3
#define CLK_WIFI_DIV 4
#define CLK_WIFI_OSC0 5
#define CLK_WIFI 6
#define CLK_PMU 7
#define SCLK_UART1_DIV 8
#define SCLK_UART1_FRACDIV 9
#define SCLK_UART1_MUX 10
#define SCLK_UART1 11
#define CLK_I2C0 12
#define CLK_I2C2 13
#define CLK_CAPTURE_PWM0 14
#define CLK_PWM0 15
#define CLK_CAPTURE_PWM1 16
#define CLK_PWM1 17
#define CLK_SPI0 18
#define DBCLK_GPIO0 19
#define CLK_PMUPVTM 20
#define CLK_CORE_PMUPVTM 21
#define CLK_REF12M 22
#define CLK_USBPHY_OTG_REF 23
#define CLK_USBPHY_HOST_REF 24
#define CLK_REF24M 25
#define CLK_MIPIDSIPHY_REF 26
/* pclk */
#define PCLK_PDPMU 30
#define PCLK_PMU 31
#define PCLK_UART1 32
#define PCLK_I2C0 33
#define PCLK_I2C2 34
#define PCLK_PWM0 35
#define PCLK_PWM1 36
#define PCLK_SPI0 37
#define PCLK_GPIO0 38
#define PCLK_PMUSGRF 39
#define PCLK_PMUGRF 40
#define PCLK_PMUCRU 41
#define PCLK_CHIPVEROTP 42
#define PCLK_PDPMU_NIU 43
#define PCLK_PMUPVTM 44
#define PCLK_SCRKEYGEN 45
#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)
/* cru-clocks indices */
/* pll clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_CPLL 3
#define PLL_HPLL 4
/* sclk (special clocks) */
#define ARMCLK 5
#define USB480M 6
#define CLK_CORE_CPUPVTM 7
#define CLK_CPUPVTM 8
#define CLK_SCR1 9
#define CLK_SCR1_CORE 10
#define CLK_SCR1_RTC 11
#define CLK_SCR1_JTAG 12
#define SCLK_UART0_DIV 13
#define SCLK_UART0_FRAC 14
#define SCLK_UART0_MUX 15
#define SCLK_UART0 16
#define SCLK_UART2_DIV 17
#define SCLK_UART2_FRAC 18
#define SCLK_UART2_MUX 19
#define SCLK_UART2 20
#define SCLK_UART3_DIV 21
#define SCLK_UART3_FRAC 22
#define SCLK_UART3_MUX 23
#define SCLK_UART3 24
#define SCLK_UART4_DIV 25
#define SCLK_UART4_FRAC 26
#define SCLK_UART4_MUX 27
#define SCLK_UART4 28
#define SCLK_UART5_DIV 29
#define SCLK_UART5_FRAC 30
#define SCLK_UART5_MUX 31
#define SCLK_UART5 32
#define CLK_I2C1 33
#define CLK_I2C3 34
#define CLK_I2C4 35
#define CLK_I2C5 36
#define CLK_SPI1 37
#define CLK_CAPTURE_PWM2 38
#define CLK_PWM2 39
#define DBCLK_GPIO1 40
#define DBCLK_GPIO2 41
#define DBCLK_GPIO3 42
#define DBCLK_GPIO4 43
#define CLK_SARADC 44
#define CLK_TIMER0 45
#define CLK_TIMER1 46
#define CLK_TIMER2 47
#define CLK_TIMER3 48
#define CLK_TIMER4 49
#define CLK_TIMER5 50
#define CLK_CAN 51
#define CLK_NPU_TSADC 52
#define CLK_NPU_TSADCPHY 53
#define CLK_CPU_TSADC 54
#define CLK_CPU_TSADCPHY 55
#define CLK_CRYPTO_CORE 56
#define CLK_CRYPTO_PKA 57
#define MCLK_I2S0_TX_DIV 58
#define MCLK_I2S0_TX_FRACDIV 59
#define MCLK_I2S0_TX_MUX 60
#define MCLK_I2S0_TX 61
#define MCLK_I2S0_RX_DIV 62
#define MCLK_I2S0_RX_FRACDIV 63
#define MCLK_I2S0_RX_MUX 64
#define MCLK_I2S0_RX 65
#define MCLK_I2S0_TX_OUT2IO 66
#define MCLK_I2S0_RX_OUT2IO 67
#define MCLK_I2S1_DIV 68
#define MCLK_I2S1_FRACDIV 69
#define MCLK_I2S1_MUX 70
#define MCLK_I2S1 71
#define MCLK_I2S1_OUT2IO 72
#define MCLK_I2S2_DIV 73
#define MCLK_I2S2_FRACDIV 74
#define MCLK_I2S2_MUX 75
#define MCLK_I2S2 76
#define MCLK_I2S2_OUT2IO 77
#define MCLK_PDM 78
#define SCLK_ADUPWM_DIV 79
#define SCLK_AUDPWM_FRACDIV 80
#define SCLK_AUDPWM_MUX 81
#define SCLK_AUDPWM 82
#define CLK_ACDCDIG_ADC 83
#define CLK_ACDCDIG_DAC 84
#define CLK_ACDCDIG_I2C 85
#define CLK_VENC_CORE 86
#define CLK_VDEC_CORE 87
#define CLK_VDEC_CA 88
#define CLK_VDEC_HEVC_CA 89
#define CLK_RGA_CORE 90
#define CLK_IEP_CORE 91
#define CLK_ISP_DIV 92
#define CLK_ISP_NP5 93
#define CLK_ISP_NUX 94
#define CLK_ISP 95
#define CLK_CIF_OUT_DIV 96
#define CLK_CIF_OUT_FRACDIV 97
#define CLK_CIF_OUT_MUX 98
#define CLK_CIF_OUT 99
#define CLK_MIPICSI_OUT_DIV 100
#define CLK_MIPICSI_OUT_FRACDIV 101
#define CLK_MIPICSI_OUT_MUX 102
#define CLK_MIPICSI_OUT 103
#define CLK_ISPP_DIV 104
#define CLK_ISPP_NP5 105
#define CLK_ISPP_NUX 106
#define CLK_ISPP 107
#define CLK_SDMMC 108
#define SCLK_SDMMC_DRV 109
#define SCLK_SDMMC_SAMPLE 110
#define CLK_SDIO 111
#define SCLK_SDIO_DRV 112
#define SCLK_SDIO_SAMPLE 113
#define CLK_EMMC 114
#define SCLK_EMMC_DRV 115
#define SCLK_EMMC_SAMPLE 116
#define CLK_NANDC 117
#define SCLK_SFC 118
#define CLK_USBHOST_UTMI_OHCI 119
#define CLK_USBOTG_REF 120
#define CLK_GMAC_DIV 121
#define CLK_GMAC_RGMII_M0 122
#define CLK_GMAC_SRC_M0 123
#define CLK_GMAC_RGMII_M1 124
#define CLK_GMAC_SRC_M1 125
#define CLK_GMAC_SRC 126
#define CLK_GMAC_REF 127
#define CLK_GMAC_TX_SRC 128
#define CLK_GMAC_TX_DIV5 129
#define CLK_GMAC_TX_DIV50 130
#define RGMII_MODE_CLK 131
#define CLK_GMAC_RX_SRC 132
#define CLK_GMAC_RX_DIV2 133
#define CLK_GMAC_RX_DIV20 134
#define RMII_MODE_CLK 135
#define CLK_GMAC_TX_RX 136
#define CLK_GMAC_PTPREF 137
#define CLK_GMAC_ETHERNET_OUT 138
#define CLK_DDRPHY 139
#define CLK_DDR_MON 140
#define TMCLK_DDR_MON 141
#define CLK_NPU_DIV 142
#define CLK_NPU_NP5 143
#define CLK_CORE_NPU 144
#define CLK_CORE_NPUPVTM 145
#define CLK_NPUPVTM 146
#define SCLK_DDRCLK 147
#define CLK_OTP 148
/* dclk */
#define DCLK_DECOM 150
#define DCLK_VOP_DIV 151
#define DCLK_VOP_FRACDIV 152
#define DCLK_VOP_MUX 153
#define DCLK_VOP 154
#define DCLK_CIF 155
#define DCLK_CIFLITE 156
/* aclk */
#define ACLK_PDBUS 160
#define ACLK_DMAC 161
#define ACLK_DCF 162
#define ACLK_SPINLOCK 163
#define ACLK_DECOM 164
#define ACLK_PDCRYPTO 165
#define ACLK_CRYPTO 166
#define ACLK_PDVEPU 167
#define ACLK_VENC 168
#define ACLK_PDVDEC 169
#define ACLK_PDJPEG 170
#define ACLK_VDEC 171
#define ACLK_JPEG 172
#define ACLK_PDVO 173
#define ACLK_RGA 174
#define ACLK_VOP 175
#define ACLK_IEP 176
#define ACLK_PDVI_DIV 177
#define ACLK_PDVI_NP5 178
#define ACLK_PDVI 179
#define ACLK_ISP 180
#define ACLK_CIF 181
#define ACLK_CIFLITE 182
#define ACLK_PDISPP_DIV 183
#define ACLK_PDISPP_NP5 184
#define ACLK_PDISPP 185
#define ACLK_ISPP 186
#define ACLK_PDPHP 187
#define ACLK_PDUSB 188
#define ACLK_USBOTG 189
#define ACLK_PDGMAC 190
#define ACLK_GMAC 191
#define ACLK_PDNPU_DIV 192
#define ACLK_PDNPU_NP5 193
#define ACLK_PDNPU 194
#define ACLK_NPU 195
/* hclk */
#define HCLK_PDCORE_NIU 200
#define HCLK_PDUSB 201
#define HCLK_PDCRYPTO 202
#define HCLK_CRYPTO 203
#define HCLK_PDAUDIO 204
#define HCLK_I2S0 205
#define HCLK_I2S1 206
#define HCLK_I2S2 207
#define HCLK_PDM 208
#define HCLK_AUDPWM 209
#define HCLK_PDVEPU 210
#define HCLK_VENC 211
#define HCLK_PDVDEC 212
#define HCLK_PDJPEG 213
#define HCLK_VDEC 214
#define HCLK_JPEG 215
#define HCLK_PDVO 216
#define HCLK_RGA 217
#define HCLK_VOP 218
#define HCLK_IEP 219
#define HCLK_PDVI 220
#define HCLK_ISP 221
#define HCLK_CIF 222
#define HCLK_CIFLITE 223
#define HCLK_PDISPP 224
#define HCLK_ISPP 225
#define HCLK_PDPHP 226
#define HCLK_PDSDMMC 227
#define HCLK_SDMMC 228
#define HCLK_PDSDIO 229
#define HCLK_SDIO 230
#define HCLK_PDNVM 231
#define HCLK_EMMC 232
#define HCLK_NANDC 233
#define HCLK_SFC 234
#define HCLK_SFCXIP 235
#define HCLK_PDBUS 236
#define HCLK_USBHOST 237
#define HCLK_USBHOST_ARB 238
#define HCLK_PDNPU 239
#define HCLK_NPU 240
/* pclk */
#define PCLK_CPUPVTM 245
#define PCLK_PDBUS 246
#define PCLK_DCF 247
#define PCLK_WDT 248
#define PCLK_MAILBOX 249
#define PCLK_UART0 250
#define PCLK_UART2 251
#define PCLK_UART3 252
#define PCLK_UART4 253
#define PCLK_UART5 254
#define PCLK_I2C1 255
#define PCLK_I2C3 256
#define PCLK_I2C4 257
#define PCLK_I2C5 258
#define PCLK_SPI1 259
#define PCLK_PWM2 261
#define PCLK_GPIO1 262
#define PCLK_GPIO2 263
#define PCLK_GPIO3 264
#define PCLK_GPIO4 265
#define PCLK_SARADC 266
#define PCLK_TIMER 267
#define PCLK_DECOM 268
#define PCLK_CAN 269
#define PCLK_NPU_TSADC 270
#define PCLK_CPU_TSADC 271
#define PCLK_ACDCDIG 272
#define PCLK_PDVO 273
#define PCLK_DSIHOST 274
#define PCLK_PDVI 275
#define PCLK_CSIHOST 276
#define PCLK_PDGMAC 277
#define PCLK_GMAC 278
#define PCLK_PDDDR 279
#define PCLK_DDR_MON 280
#define PCLK_PDNPU 281
#define PCLK_NPUPVTM 282
#define PCLK_PDTOP 283
#define PCLK_TOPCRU 284
#define PCLK_TOPGRF 285
#define PCLK_CPUEMADET 286
#define PCLK_DDRPHY 287
#define PCLK_DSIPHY 289
#define PCLK_CSIPHY0 290
#define PCLK_CSIPHY1 291
#define PCLK_USBPHY_HOST 292
#define PCLK_USBPHY_OTG 293
#define PCLK_OTP 294
#define CLK_NR_CLKS (PCLK_OTP + 1)
/* pmu soft-reset indices */
/* pmu_cru_softrst_con0 */
#define SRST_PDPMU_NIU_P 0
#define SRST_PMU_SGRF_P 1
#define SRST_PMU_SGRF_REMAP_P 2
#define SRST_I2C0_P 3
#define SRST_I2C0 4
#define SRST_I2C2_P 7
#define SRST_I2C2 8
#define SRST_UART1_P 9
#define SRST_UART1 10
#define SRST_PWM0_P 11
#define SRST_PWM0 12
#define SRST_PWM1_P 13
#define SRST_PWM1 14
#define SRST_DDR_FAIL_SAFE 15
/* pmu_cru_softrst_con1 */
#define SRST_GPIO0_P 17
#define SRST_GPIO0_DB 18
#define SRST_SPI0_P 19
#define SRST_SPI0 20
#define SRST_PMUGRF_P 21
#define SRST_CHIPVEROTP_P 22
#define SRST_PMUPVTM 24
#define SRST_PMUPVTM_P 25
#define SRST_PMUCRU_P 30
/* soft-reset indices */
/* cru_softrst_con0 */
#define SRST_CORE0_PO 0
#define SRST_CORE1_PO 1
#define SRST_CORE2_PO 2
#define SRST_CORE3_PO 3
#define SRST_CORE0 4
#define SRST_CORE1 5
#define SRST_CORE2 6
#define SRST_CORE3 7
#define SRST_CORE0_DBG 8
#define SRST_CORE1_DBG 9
#define SRST_CORE2_DBG 10
#define SRST_CORE3_DBG 11
#define SRST_NL2 12
#define SRST_CORE_NIU_A 13
#define SRST_DBG_DAPLITE_P 14
#define SRST_DAPLITE_P 15
/* cru_softrst_con1 */
#define SRST_PDBUS_NIU1_A 16
#define SRST_PDBUS_NIU1_H 17
#define SRST_PDBUS_NIU1_P 18
#define SRST_PDBUS_NIU2_A 19
#define SRST_PDBUS_NIU2_H 20
#define SRST_PDBUS_NIU3_A 21
#define SRST_PDBUS_NIU3_H 22
#define SRST_PDBUS_HOLD_NIU1_A 23
#define SRST_DBG_NIU_P 24
#define SRST_PDCORE_NIIU_H 25
#define SRST_MUC_NIU 26
#define SRST_DCF_A 29
#define SRST_DCF_P 30
#define SRST_SYSTEM_SRAM_A 31
/* cru_softrst_con2 */
#define SRST_I2C1_P 32
#define SRST_I2C1 33
#define SRST_I2C3_P 34
#define SRST_I2C3 35
#define SRST_I2C4_P 36
#define SRST_I2C4 37
#define SRST_I2C5_P 38
#define SRST_I2C5 39
#define SRST_SPI1_P 40
#define SRST_SPI1 41
#define SRST_MCU_CORE 42
#define SRST_PWM2_P 44
#define SRST_PWM2 45
#define SRST_SPINLOCK_A 46
/* cru_softrst_con3 */
#define SRST_UART0_P 48
#define SRST_UART0 49
#define SRST_UART2_P 50
#define SRST_UART2 51
#define SRST_UART3_P 52
#define SRST_UART3 53
#define SRST_UART4_P 54
#define SRST_UART4 55
#define SRST_UART5_P 56
#define SRST_UART5 57
#define SRST_WDT_P 58
#define SRST_SARADC_P 59
#define SRST_GRF_P 61
#define SRST_TIMER_P 62
#define SRST_MAILBOX_P 63
/* cru_softrst_con4 */
#define SRST_TIMER0 64
#define SRST_TIMER1 65
#define SRST_TIMER2 66
#define SRST_TIMER3 67
#define SRST_TIMER4 68
#define SRST_TIMER5 69
#define SRST_INTMUX_P 70
#define SRST_GPIO1_P 72
#define SRST_GPIO1_DB 73
#define SRST_GPIO2_P 74
#define SRST_GPIO2_DB 75
#define SRST_GPIO3_P 76
#define SRST_GPIO3_DB 77
#define SRST_GPIO4_P 78
#define SRST_GPIO4_DB 79
/* cru_softrst_con5 */
#define SRST_CAN_P 80
#define SRST_CAN 81
#define SRST_DECOM_A 85
#define SRST_DECOM_P 86
#define SRST_DECOM_D 87
#define SRST_PDCRYPTO_NIU_A 88
#define SRST_PDCRYPTO_NIU_H 89
#define SRST_CRYPTO_A 90
#define SRST_CRYPTO_H 91
#define SRST_CRYPTO_CORE 92
#define SRST_CRYPTO_PKA 93
#define SRST_SGRF_P 95
/* cru_softrst_con6 */
#define SRST_PDAUDIO_NIU_H 96
#define SRST_PDAUDIO_NIU_P 97
#define SRST_I2S0_H 98
#define SRST_I2S0_TX_M 99
#define SRST_I2S0_RX_M 100
#define SRST_I2S1_H 101
#define SRST_I2S1_M 102
#define SRST_I2S2_H 103
#define SRST_I2S2_M 104
#define SRST_PDM_H 105
#define SRST_PDM_M 106
#define SRST_AUDPWM_H 107
#define SRST_AUDPWM 108
#define SRST_ACDCDIG_P 109
#define SRST_ACDCDIG 110
/* cru_softrst_con7 */
#define SRST_PDVEPU_NIU_A 112
#define SRST_PDVEPU_NIU_H 113
#define SRST_VENC_A 114
#define SRST_VENC_H 115
#define SRST_VENC_CORE 116
#define SRST_PDVDEC_NIU_A 117
#define SRST_PDVDEC_NIU_H 118
#define SRST_VDEC_A 119
#define SRST_VDEC_H 120
#define SRST_VDEC_CORE 121
#define SRST_VDEC_CA 122
#define SRST_VDEC_HEVC_CA 123
#define SRST_PDJPEG_NIU_A 124
#define SRST_PDJPEG_NIU_H 125
#define SRST_JPEG_A 126
#define SRST_JPEG_H 127
/* cru_softrst_con8 */
#define SRST_PDVO_NIU_A 128
#define SRST_PDVO_NIU_H 129
#define SRST_PDVO_NIU_P 130
#define SRST_RGA_A 131
#define SRST_RGA_H 132
#define SRST_RGA_CORE 133
#define SRST_VOP_A 134
#define SRST_VOP_H 135
#define SRST_VOP_D 136
#define SRST_TXBYTEHS_DSIHOST 137
#define SRST_DSIHOST_P 138
#define SRST_IEP_A 139
#define SRST_IEP_H 140
#define SRST_IEP_CORE 141
#define SRST_ISP_RX_P 142
/* cru_softrst_con9 */
#define SRST_PDVI_NIU_A 144
#define SRST_PDVI_NIU_H 145
#define SRST_PDVI_NIU_P 146
#define SRST_ISP 147
#define SRST_CIF_A 148
#define SRST_CIF_H 149
#define SRST_CIF_D 150
#define SRST_CIF_P 151
#define SRST_CIF_I 152
#define SRST_CIF_RX_P 153
#define SRST_PDISPP_NIU_A 154
#define SRST_PDISPP_NIU_H 155
#define SRST_ISPP_A 156
#define SRST_ISPP_H 157
#define SRST_ISPP 158
#define SRST_CSIHOST_P 159
/* cru_softrst_con10 */
#define SRST_PDPHPMID_NIU_A 160
#define SRST_PDPHPMID_NIU_H 161
#define SRST_PDNVM_NIU_H 163
#define SRST_SDMMC_H 164
#define SRST_SDIO_H 165
#define SRST_EMMC_H 166
#define SRST_SFC_H 167
#define SRST_SFCXIP_H 168
#define SRST_SFC 169
#define SRST_NANDC_H 170
#define SRST_NANDC 171
#define SRST_PDSDMMC_H 173
#define SRST_PDSDIO_H 174
/* cru_softrst_con11 */
#define SRST_PDUSB_NIU_A 176
#define SRST_PDUSB_NIU_H 177
#define SRST_USBHOST_H 178
#define SRST_USBHOST_ARB_H 179
#define SRST_USBHOST_UTMI 180
#define SRST_USBOTG_A 181
#define SRST_USBPHY_OTG_P 182
#define SRST_USBPHY_HOST_P 183
#define SRST_USBPHYPOR_OTG 184
#define SRST_USBPHYPOR_HOST 185
#define SRST_PDGMAC_NIU_A 188
#define SRST_PDGMAC_NIU_P 189
#define SRST_GMAC_A 190
/* cru_softrst_con12 */
#define SRST_DDR_DFICTL_P 193
#define SRST_DDR_MON_P 194
#define SRST_DDR_STANDBY_P 195
#define SRST_DDR_GRF_P 196
#define SRST_DDR_MSCH_P 197
#define SRST_DDR_SPLIT_A 198
#define SRST_DDR_MSCH 199
#define SRST_DDR_DFICTL 202
#define SRST_DDR_STANDBY 203
#define SRST_NPUMCU_NIU 205
#define SRST_DDRPHY_P 206
#define SRST_DDRPHY 207
/* cru_softrst_con13 */
#define SRST_PDNPU_NIU_A 208
#define SRST_PDNPU_NIU_H 209
#define SRST_PDNPU_NIU_P 210
#define SRST_NPU_A 211
#define SRST_NPU_H 212
#define SRST_NPU 213
#define SRST_NPUPVTM_P 214
#define SRST_NPUPVTM 215
#define SRST_NPU_TSADC_P 216
#define SRST_NPU_TSADC 217
#define SRST_NPU_TSADCPHY 218
#define SRST_CIFLITE_A 220
#define SRST_CIFLITE_H 221
#define SRST_CIFLITE_D 222
#define SRST_CIFLITE_RX_P 223
/* cru_softrst_con14 */
#define SRST_TOPNIU_P 224
#define SRST_TOPCRU_P 225
#define SRST_TOPGRF_P 226
#define SRST_CPUEMADET_P 227
#define SRST_CSIPHY0_P 228
#define SRST_CSIPHY1_P 229
#define SRST_DSIPHY_P 230
#define SRST_CPU_TSADC_P 232
#define SRST_CPU_TSADC 233
#define SRST_CPU_TSADCPHY 234
#define SRST_CPUPVTM_P 235
#define SRST_CPUPVTM 236
#endif

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include/dt-bindings/clock/rv1108-cru.h
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@ -1,356 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
* Author: Shawn Lin <shawn.lin@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
/* pll id */
#define PLL_APLL 0
#define PLL_DPLL 1
#define PLL_GPLL 2
#define ARMCLK 3
/* sclk gates (special clocks) */
#define SCLK_SPI0 65
#define SCLK_NANDC 67
#define SCLK_SDMMC 68
#define SCLK_SDIO 69
#define SCLK_EMMC 71
#define SCLK_UART0 72
#define SCLK_UART1 73
#define SCLK_UART2 74
#define SCLK_I2S0 75
#define SCLK_I2S1 76
#define SCLK_I2S2 77
#define SCLK_TIMER0 78
#define SCLK_TIMER1 79
#define SCLK_SFC 80
#define SCLK_SDMMC_DRV 81
#define SCLK_SDIO_DRV 82
#define SCLK_EMMC_DRV 83
#define SCLK_SDMMC_SAMPLE 84
#define SCLK_SDIO_SAMPLE 85
#define SCLK_EMMC_SAMPLE 86
#define SCLK_VENC_CORE 87
#define SCLK_HEVC_CORE 88
#define SCLK_HEVC_CABAC 89
#define SCLK_PWM0_PMU 90
#define SCLK_I2C0_PMU 91
#define SCLK_WIFI 92
#define SCLK_CIFOUT 93
#define SCLK_MIPI_CSI_OUT 94
#define SCLK_CIF0 95
#define SCLK_CIF1 96
#define SCLK_CIF2 97
#define SCLK_CIF3 98
#define SCLK_DSP 99
#define SCLK_DSP_IOP 100
#define SCLK_DSP_EPP 101
#define SCLK_DSP_EDP 102
#define SCLK_DSP_EDAP 103
#define SCLK_CVBS_HOST 104
#define SCLK_HDMI_SFR 105
#define SCLK_HDMI_CEC 106
#define SCLK_CRYPTO 107
#define SCLK_SPI 108
#define SCLK_SARADC 109
#define SCLK_TSADC 110
#define SCLK_MAC_PRE 111
#define SCLK_MAC 112
#define SCLK_MAC_RX 113
#define SCLK_MAC_REF 114
#define SCLK_MAC_REFOUT 115
#define SCLK_DSP_PFM 116
#define SCLK_RGA 117
#define SCLK_I2C1 118
#define SCLK_I2C2 119
#define SCLK_I2C3 120
#define SCLK_PWM 121
#define SCLK_ISP 122
#define SCLK_USBPHY 123
#define SCLK_I2S0_SRC 124
#define SCLK_I2S1_SRC 125
#define SCLK_I2S2_SRC 126
#define SCLK_UART0_SRC 127
#define SCLK_UART1_SRC 128
#define SCLK_UART2_SRC 129
#define SCLK_MAC_TX 130
#define SCLK_MACREF 131
#define SCLK_MACREF_OUT 132
#define DCLK_VOP_SRC 185
#define DCLK_HDMIPHY 186
#define DCLK_VOP 187
/* aclk gates */
#define ACLK_DMAC 192
#define ACLK_PRE 193
#define ACLK_CORE 194
#define ACLK_ENMCORE 195
#define ACLK_RKVENC 196
#define ACLK_RKVDEC 197
#define ACLK_VPU 198
#define ACLK_CIF0 199
#define ACLK_VIO0 200
#define ACLK_VIO1 201
#define ACLK_VOP 202
#define ACLK_IEP 203
#define ACLK_RGA 204
#define ACLK_ISP 205
#define ACLK_CIF1 206
#define ACLK_CIF2 207
#define ACLK_CIF3 208
#define ACLK_PERI 209
#define ACLK_GMAC 210
/* pclk gates */
#define PCLK_GPIO1 256
#define PCLK_GPIO2 257
#define PCLK_GPIO3 258
#define PCLK_GRF 259
#define PCLK_I2C1 260
#define PCLK_I2C2 261
#define PCLK_I2C3 262
#define PCLK_SPI 263
#define PCLK_SFC 264
#define PCLK_UART0 265
#define PCLK_UART1 266
#define PCLK_UART2 267
#define PCLK_TSADC 268
#define PCLK_PWM 269
#define PCLK_TIMER 270
#define PCLK_PERI 271
#define PCLK_GPIO0_PMU 272
#define PCLK_I2C0_PMU 273
#define PCLK_PWM0_PMU 274
#define PCLK_ISP 275
#define PCLK_VIO 276
#define PCLK_MIPI_DSI 277
#define PCLK_HDMI_CTRL 278
#define PCLK_SARADC 279
#define PCLK_DSP_CFG 280
#define PCLK_BUS 281
#define PCLK_EFUSE0 282
#define PCLK_EFUSE1 283
#define PCLK_WDT 284
#define PCLK_GMAC 285
/* hclk gates */
#define HCLK_I2S0_8CH 320
#define HCLK_I2S1_2CH 321
#define HCLK_I2S2_2CH 322
#define HCLK_NANDC 323
#define HCLK_SDMMC 324
#define HCLK_SDIO 325
#define HCLK_EMMC 326
#define HCLK_PERI 327
#define HCLK_SFC 328
#define HCLK_RKVENC 329
#define HCLK_RKVDEC 330
#define HCLK_CIF0 331
#define HCLK_VIO 332
#define HCLK_VOP 333
#define HCLK_IEP 334
#define HCLK_RGA 335
#define HCLK_ISP 336
#define HCLK_CRYPTO_MST 337
#define HCLK_CRYPTO_SLV 338
#define HCLK_HOST0 339
#define HCLK_OTG 340
#define HCLK_CIF1 341
#define HCLK_CIF2 342
#define HCLK_CIF3 343
#define HCLK_BUS 344
#define HCLK_VPU 345
#define CLK_NR_CLKS (HCLK_VPU + 1)
/* reset id */
#define SRST_CORE_PO_AD 0
#define SRST_CORE_AD 1
#define SRST_L2_AD 2
#define SRST_CPU_NIU_AD 3
#define SRST_CORE_PO 4
#define SRST_CORE 5
#define SRST_L2 6
#define SRST_CORE_DBG 8
#define PRST_DBG 9
#define RST_DAP 10
#define PRST_DBG_NIU 11
#define ARST_STRC_SYS_AD 15
#define SRST_DDRPHY_CLKDIV 16
#define SRST_DDRPHY 17
#define PRST_DDRPHY 18
#define PRST_HDMIPHY 19
#define PRST_VDACPHY 20
#define PRST_VADCPHY 21
#define PRST_MIPI_CSI_PHY 22
#define PRST_MIPI_DSI_PHY 23
#define PRST_ACODEC 24
#define ARST_BUS_NIU 25
#define PRST_TOP_NIU 26
#define ARST_INTMEM 27
#define HRST_ROM 28
#define ARST_DMAC 29
#define SRST_MSCH_NIU 30
#define PRST_MSCH_NIU 31
#define PRST_DDRUPCTL 32
#define NRST_DDRUPCTL 33
#define PRST_DDRMON 34
#define HRST_I2S0_8CH 35
#define MRST_I2S0_8CH 36
#define HRST_I2S1_2CH 37
#define MRST_IS21_2CH 38
#define HRST_I2S2_2CH 39
#define MRST_I2S2_2CH 40
#define HRST_CRYPTO 41
#define SRST_CRYPTO 42
#define PRST_SPI 43
#define SRST_SPI 44
#define PRST_UART0 45
#define PRST_UART1 46
#define PRST_UART2 47
#define SRST_UART0 48
#define SRST_UART1 49
#define SRST_UART2 50
#define PRST_I2C1 51
#define PRST_I2C2 52
#define PRST_I2C3 53
#define SRST_I2C1 54
#define SRST_I2C2 55
#define SRST_I2C3 56
#define PRST_PWM1 58
#define SRST_PWM1 60
#define PRST_WDT 61
#define PRST_GPIO1 62
#define PRST_GPIO2 63
#define PRST_GPIO3 64
#define PRST_GRF 65
#define PRST_EFUSE 66
#define PRST_EFUSE512 67
#define PRST_TIMER0 68
#define SRST_TIMER0 69
#define SRST_TIMER1 70
#define PRST_TSADC 71
#define SRST_TSADC 72
#define PRST_SARADC 73
#define SRST_SARADC 74
#define HRST_SYSBUS 75
#define PRST_USBGRF 76
#define ARST_PERIPH_NIU 80
#define HRST_PERIPH_NIU 81
#define PRST_PERIPH_NIU 82
#define HRST_PERIPH 83
#define HRST_SDMMC 84
#define HRST_SDIO 85
#define HRST_EMMC 86
#define HRST_NANDC 87
#define NRST_NANDC 88
#define HRST_SFC 89
#define SRST_SFC 90
#define ARST_GMAC 91
#define HRST_OTG 92
#define SRST_OTG 93
#define SRST_OTG_ADP 94
#define HRST_HOST0 95
#define HRST_HOST0_AUX 96
#define HRST_HOST0_ARB 97
#define SRST_HOST0_EHCIPHY 98
#define SRST_HOST0_UTMI 99
#define SRST_USBPOR 100
#define SRST_UTMI0 101
#define SRST_UTMI1 102
#define ARST_VIO0_NIU 102
#define ARST_VIO1_NIU 103
#define HRST_VIO_NIU 104
#define PRST_VIO_NIU 105
#define ARST_VOP 106
#define HRST_VOP 107
#define DRST_VOP 108
#define ARST_IEP 109
#define HRST_IEP 110
#define ARST_RGA 111
#define HRST_RGA 112
#define SRST_RGA 113
#define PRST_CVBS 114
#define PRST_HDMI 115
#define SRST_HDMI 116
#define PRST_MIPI_DSI 117
#define ARST_ISP_NIU 118
#define HRST_ISP_NIU 119
#define HRST_ISP 120
#define SRST_ISP 121
#define ARST_VIP0 122
#define HRST_VIP0 123
#define PRST_VIP0 124
#define ARST_VIP1 125
#define HRST_VIP1 126
#define PRST_VIP1 127
#define ARST_VIP2 128
#define HRST_VIP2 129
#define PRST_VIP2 120
#define ARST_VIP3 121
#define HRST_VIP3 122
#define PRST_VIP4 123
#define PRST_CIF1TO4 124
#define SRST_CVBS_CLK 125
#define HRST_CVBS 126
#define ARST_VPU_NIU 140
#define HRST_VPU_NIU 141
#define ARST_VPU 142
#define HRST_VPU 143
#define ARST_RKVDEC_NIU 144
#define HRST_RKVDEC_NIU 145
#define ARST_RKVDEC 146
#define HRST_RKVDEC 147
#define SRST_RKVDEC_CABAC 148
#define SRST_RKVDEC_CORE 149
#define ARST_RKVENC_NIU 150
#define HRST_RKVENC_NIU 151
#define ARST_RKVENC 152
#define HRST_RKVENC 153
#define SRST_RKVENC_CORE 154
#define SRST_DSP_CORE 156
#define SRST_DSP_SYS 157
#define SRST_DSP_GLOBAL 158
#define SRST_DSP_OECM 159
#define PRST_DSP_IOP_NIU 160
#define ARST_DSP_EPP_NIU 161
#define ARST_DSP_EDP_NIU 162
#define PRST_DSP_DBG_NIU 163
#define PRST_DSP_CFG_NIU 164
#define PRST_DSP_GRF 165
#define PRST_DSP_MAILBOX 166
#define PRST_DSP_INTC 167
#define PRST_DSP_PFM_MON 169
#define SRST_DSP_PFM_MON 170
#define ARST_DSP_EDAP_NIU 171
#define SRST_PMU 172
#define SRST_PMU_I2C0 173
#define PRST_PMU_I2C0 174
#define PRST_PMU_GPIO0 175
#define PRST_PMU_INTMEM 176
#define PRST_PMU_PWM0 177
#define SRST_PMU_PWM0 178
#define PRST_PMU_GRF 179
#define SRST_PMU_NIU 180
#define SRST_PMU_PVTM 181
#define ARST_DSP_EDP_PERF 184
#define ARST_DSP_EPP_PERF 185
#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */

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