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AT91: Makes AT91SAM9RL-EK build correctly against u-boot-atmel/master
Rework for AT91SAM9RL-EK, makes it build again. Based on the work for AT91SAM9260-EK. V4: added changes to MAKEALL Signed-off-by: Hong Xu <hong.xu@atmel.com> Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
This commit is contained in:
Xu, Hong
U-Boot
parent
f87353f0d9
commit
21d671d0c4
1
MAKEALL
1
MAKEALL
@ -450,7 +450,6 @@ LIST_at91="$(boards_by_soc at91)\
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at91sam9g10ek \
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at91sam9g20ek \
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at91sam9m10g45ek \
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at91sam9rlek \
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pm9g45 \
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SBC35_A9G20 \
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TNY_A9260 \
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12
Makefile
12
Makefile
@ -844,18 +844,6 @@ at91sam9263ek_config : unconfig
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fi;
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@$(MKCONFIG) -n $@ -a at91sam9263ek arm arm926ejs at91sam9263ek atmel at91
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at91sam9rlek_nandflash_config \
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at91sam9rlek_dataflash_config \
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at91sam9rlek_dataflash_cs0_config \
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at91sam9rlek_config : unconfig
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@mkdir -p $(obj)include
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@if [ "$(findstring _nandflash,$@)" ] ; then \
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echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
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else \
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echo "#define CONFIG_SYS_USE_DATAFLASH 1" >>$(obj)include/config.h ; \
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fi;
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@$(MKCONFIG) -n $@ -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
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at91sam9m10g45ek_nandflash_config \
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at91sam9m10g45ek_dataflash_config \
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at91sam9m10g45ek_dataflash_cs0_config \
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@ -23,6 +23,7 @@
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/at91sam9rl.h>
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#include <asm/arch/at91sam9rl_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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@ -31,7 +32,7 @@
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <lcd.h>
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#include <atmel_lcdc.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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@ -48,33 +49,37 @@ DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_CMD_NAND
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static void at91sam9rlek_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_DBW_16 |
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_TDF_(2));
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
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writel(1 << ATMEL_ID_PIOD, &pmc->pcer);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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@ -102,7 +107,7 @@ vidinfo_t panel_info = {
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vl_vsync_len: 1,
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vl_upper_margin:1,
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vl_lower_margin:0,
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mmio: AT91SAM9RL_LCDC_BASE,
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mmio: ATMEL_BASE_LCDC,
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};
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void lcd_enable(void)
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@ -116,6 +121,8 @@ void lcd_disable(void)
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}
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static void at91sam9rlek_lcd_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
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at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
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at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
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@ -138,9 +145,7 @@ static void at91sam9rlek_lcd_hw_init(void)
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at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
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at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
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gd->fb_base = 0;
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writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
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}
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#ifdef CONFIG_LCD_INFO
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@ -157,7 +162,7 @@ void lcd_show_board_info(void)
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lcd_printf ("(C) 2008 ATMEL Corp\n");
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lcd_printf ("at91support@atmel.com\n");
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lcd_printf ("%s CPU at %s MHz\n",
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CONFIG_SYS_AT91_CPU_NAME,
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ATMEL_CPU_NAME,
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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@ -173,6 +178,17 @@ void lcd_show_board_info(void)
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#endif /* CONFIG_LCD_INFO */
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#endif
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int board_early_init_f(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable clocks for all PIOs */
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writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
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(1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD),
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&pmc->pcer);
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return 0;
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}
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int board_init(void)
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{
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@ -182,9 +198,9 @@ int board_init(void)
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/* arch number of AT91SAM9RLEK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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at91_serial_hw_init();
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at91_seriald_hw_init();
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#ifdef CONFIG_CMD_NAND
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at91sam9rlek_nand_hw_init();
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#endif
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@ -199,7 +215,8 @@ int board_init(void)
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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gd->ram_size = get_ram_size(
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(void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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@ -1 +0,0 @@
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CONFIG_SYS_TEXT_BASE = 0x23f00000
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@ -26,12 +26,14 @@
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#include <asm/arch/at91sam9rl.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/io.h>
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void coloured_LED_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
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writel(ATMEL_ID_PIOD, &pmc->pcer);
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at91_set_gpio_output(CONFIG_RED_LED, 1);
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at91_set_gpio_output(CONFIG_GREEN_LED, 1);
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@ -80,6 +80,8 @@ at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel
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at91sam9g20ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH
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at91sam9g20ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0
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at91sam9g20ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1
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at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH
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at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH
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at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH
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at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0
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at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1
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@ -27,33 +27,42 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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#include <asm/hardware.h>
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#define CONFIG_SYS_TEXT_BASE 0x21F00000
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_AT91SAM9RLEK 1 /* It's an AT91SAM9RLEK Board */
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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#define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/
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#define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */
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#define CONFIG_ARCH_CPU_INIT
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_BOARD_EARLY_INIT_F
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_ATMEL_LEGACY
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#define CONFIG_AT91_GPIO 1
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#define CONFIG_AT91_GPIO_PULLUP 1
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/*
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* Hardware drivers
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*/
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#define CONFIG_AT91_GPIO 1
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#define CONFIG_ATMEL_USART 1
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#undef CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_USART2
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#define CONFIG_USART3 1 /* USART 3 is DBGU */
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/* serial console */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600}
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/* LCD */
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#define CONFIG_LCD 1
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@ -62,10 +71,13 @@
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#undef LCD_TEST_PATTERN
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#define CONFIG_LCD_INFO 1
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#define CONFIG_LCD_INFO_BELOW_LOGO 1
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#define CONFIG_SYS_WHITE_ON_BLACK 1
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#define CONFIG_SYS_WHITE_ON_BLACK 1
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#define CONFIG_ATMEL_LCD 1
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#define CONFIG_ATMEL_LCD_RGB565 1
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
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/* Let board_init_f handle the framebuffer allocation */
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#undef CONFIG_FB_ADDR
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
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/* LED */
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#define CONFIG_AT91_LED
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@ -85,25 +97,29 @@
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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#undef CONFIG_CMD_SOURCE
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#undef CONFIG_CMD_USB
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#define CONFIG_CMD_NAND 1
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#define CONFIG_CMD_NAND 1
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000
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#define CONFIG_SYS_INIT_SP_ADDR \
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(ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
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/* DataFlash */
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#define CONFIG_ATMEL_DATAFLASH_SPI
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#define CONFIG_HAS_DATAFLASH 1
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#define CONFIG_HAS_DATAFLASH 1
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#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
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#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
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#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
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#define AT91_SPI_CLK 15000000
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#define DATAFLASH_TCSS (0x1a << 16)
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#define DATAFLASH_TCHS (0x1 << 24)
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#define AT91_SPI_CLK 15000000
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#define DATAFLASH_TCSS (0x1a << 16)
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#define DATAFLASH_TCHS (0x1 << 24)
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/* NOR flash - not present */
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#define CONFIG_SYS_NO_FLASH 1
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@ -112,7 +128,7 @@
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_DBW_8 1
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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@ -129,7 +145,7 @@
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END 0x23e00000
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#ifdef CONFIG_SYS_USE_DATAFLASH
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@ -149,7 +165,7 @@
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#else /* CONFIG_SYS_USE_NANDFLASH */
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/* bootstrap + u-boot + env + linux in nandflash */
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_OFFSET 0x60000
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#define CONFIG_ENV_OFFSET_REDUND 0x80000
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#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
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@ -161,25 +177,20 @@
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP 1
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_CMDLINE_EDITING 1
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
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#define CONFIG_STACKSIZE (32*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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||||
#error CONFIG_USE_IRQ not supported
|
||||
#endif
|
||||
#undef CONFIG_USE_IRQ
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user