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imx: mx6sllevk: select DM_SERIAL
Select DM_SERIAL Signed-off-by: Peng Fan <peng.fan@nxp.com>
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8
arch/arm/dts/imx6sll-evk-u-boot.dtsi
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8
arch/arm/dts/imx6sll-evk-u-boot.dtsi
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@ -0,0 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019, 2021 NXP
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*/
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&pinctrl_uart1 {
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u-boot,dm-pre-reloc;
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};
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@ -24,10 +24,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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@ -35,20 +31,10 @@ int dram_init(void)
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const wdog_pads[] = {
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MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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#ifdef CONFIG_DM_PMIC_PFUZE100
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int power_init_board(void)
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{
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@ -94,8 +80,6 @@ int power_init_board(void)
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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@ -51,6 +51,7 @@ CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_PFUZE100=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_DM_SERIAL=y
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CONFIG_MXC_UART=y
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CONFIG_IMX_THERMAL=y
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CONFIG_USB=y
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@ -52,6 +52,7 @@ CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_PFUZE100=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_DM_SERIAL=y
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CONFIG_MXC_UART=y
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CONFIG_IMX_THERMAL=y
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CONFIG_USB=y
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