Prepare v2024.04-rc4

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Merge tag 'v2024.04-rc4' into next

Prepare v2024.04-rc4

.azure-pipelines.yml

@@ -2,7 +2,7 @@ variables:
   windows_vm: windows-2019
   ubuntu_vm: ubuntu-22.04
   macos_vm: macOS-12
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240111-17Jan2024
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240125-12Feb2024
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
@@ -237,10 +237,9 @@ stages:
               cp images/spi-nor.img \${UBOOT_TRAVIS_BUILD_DIR}/;
           fi
           if [[ "\${TEST_PY_BD}" == "coreboot" ]]; then
-              wget -O - "https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |xz -dc >\${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
+              cp /opt/coreboot/coreboot.rom \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
-              wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >cbfstool;
+              /opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
-              chmod a+x cbfstool;
+              /opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
-              ./cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
           fi
           virtualenv -p /usr/bin/python3 /tmp/venv
           . /tmp/venv/bin/activate

.gitlab-ci.yml

@@ -10,7 +10,7 @@ default:
 
 # Grab our configured image.  The source for this is found
 # in the u-boot tree at tools/docker/Dockerfile
-image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240111-17Jan2024
+image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240125-12Feb2024
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -70,14 +70,9 @@ stages:
         cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
       fi
     - if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
-        wget -O -
+        cp /opt/coreboot/coreboot.rom ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
-          "https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |
+        /opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
-          xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
+        /opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
-        wget -O -
-          "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >
-          cbfstool;
-        chmod a+x cbfstool;
-        ./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
       fi
     - virtualenv -p /usr/bin/python3 /tmp/venv
     - . /tmp/venv/bin/activate

MAINTAINERS

@@ -497,7 +497,7 @@ M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 M:	Marek Vasut <marek.vasut+renesas@mailbox.org>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-sh.git
-F:	arch/arm/mach-rmobile/
+F:	arch/arm/mach-renesas/
 F:	drivers/clk/renesas/
 F:	drivers/gpio/gpio-rcar.c
 F:	drivers/i2c/rcar_*

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2024
 PATCHLEVEL = 04
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
 NAME =
 
 # *DOCUMENTATION*
@@ -1293,7 +1293,7 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
 	$(call if_changed,objcopy)
 
 %.scif: %.srec
-	$(Q)$(MAKE) $(build)=arch/arm/mach-rmobile $@
+	$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
 
 OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
 		$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \

arch/arm/Kconfig

@@ -1062,7 +1062,7 @@ config ARCH_QEMU
 	imply USB_KEYBOARD
 	imply CMD_USB
 
-config ARCH_RMOBILE
+config ARCH_RENESAS
 	bool "Renesas ARM SoCs"
 	select DM
 	select DM_SERIAL
@@ -2264,7 +2264,7 @@ source "arch/arm/mach-orion5x/Kconfig"
 
 source "arch/arm/mach-owl/Kconfig"
 
-source "arch/arm/mach-rmobile/Kconfig"
+source "arch/arm/mach-renesas/Kconfig"
 
 source "arch/arm/mach-meson/Kconfig"
 

arch/arm/Makefile

@@ -75,7 +75,7 @@ machine-$(CONFIG_ARCH_NPCM)             += npcm
 machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
 machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
 machine-$(CONFIG_ARCH_OWL)		+= owl
-machine-$(CONFIG_ARCH_RMOBILE)		+= rmobile
+machine-$(CONFIG_ARCH_RENESAS)		+= renesas
 machine-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip
 machine-$(CONFIG_ARCH_S5PC1XX)		+= s5pc1xx
 machine-$(CONFIG_ARCH_SNAPDRAGON)	+= snapdragon

arch/arm/dts/Makefile

@@ -832,6 +832,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
 	sun50i-h6-tanix-tx6-mini.dtb
 dtb-$(CONFIG_MACH_SUN50I_H616) += \
 	sun50i-h616-orangepi-zero2.dtb \
+	sun50i-h618-orangepi-zero2w.dtb \
 	sun50i-h618-orangepi-zero3.dtb \
 	sun50i-h618-transpeed-8k618-t.dtb \
 	sun50i-h616-x96-mate.dtb

arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi

@@ -35,6 +35,57 @@
 	};
 };
 
+&mdio {
+	switch@10 {
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			sw_phy0: ethernet-phy@0 {
+				reg = <0x0>;
+			};
+
+			sw_phy1: ethernet-phy@1 {
+				reg = <0x1>;
+			};
+
+			sw_phy2: ethernet-phy@2 {
+				reg = <0x2>;
+			};
+
+			sw_phy3: ethernet-phy@3 {
+				reg = <0x3>;
+			};
+
+			sw_phy4: ethernet-phy@4 {
+				reg = <0x4>;
+			};
+		};
+		ports {
+			ports@0 {
+				phy-handle = <&sw_phy0>;
+				phy-mode = "internal";
+			};
+			ports@1 {
+				phy-handle = <&sw_phy1>;
+				phy-mode = "internal";
+			};
+			ports@2 {
+				phy-handle = <&sw_phy2>;
+				phy-mode = "internal";
+			};
+			ports@3 {
+				phy-handle = <&sw_phy3>;
+				phy-mode = "internal";
+			};
+			ports@4 {
+				phy-handle = <&sw_phy4>;
+				phy-mode = "internal";
+			};
+		};
+	};
+};
+
 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
 &spi0 {
 	flash@0 {

arch/arm/dts/armada-38x-solidrun-microsom.dtsi

@@ -99,6 +99,11 @@
 };
 
 &i2c0 {
+	clock-frequency = <400000>;
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
 	eeprom@53 {
 		compatible = "atmel,24c02";
 		reg = <0x53>;

arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi

@@ -3,6 +3,12 @@
  * Copyright 2019 Toradex AG
  */
 
+/ {
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+};
+
 &mu {
 	bootph-some-ram;
 };

arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi

@@ -3,6 +3,12 @@
  * Copyright 2019 Toradex AG
  */
 
+/ {
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+};
+
 &{/imx8qx-pm} {
 
 	bootph-some-ram;

arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi

@@ -5,13 +5,27 @@
 
 #include "imx6qdl-u-boot.dtsi"
 
-&{/aliases} {
+/ {
-	/* U-Boot won't find PMIC otherwise */
+	aliases {
-	i2c0 = &i2c3;
+		/* U-Boot won't find PMIC otherwise */
-	i2c1 = &i2c2;
+		i2c0 = &i2c3;
-	/* SDHCI instance order: eMMC, 4-bit SD/MMC (U-Boot won't find ConfigBlock otherwise) */
+		i2c1 = &i2c2;
-	mmc0 = &usdhc3;
+		/* SDHCI instance order: eMMC, 4-bit SD/MMC
-	mmc1 = &usdhc1;
+		 * (U-Boot won't find ConfigBlock otherwise)
+		 */
+		mmc0 = &usdhc3;
+		mmc1 = &usdhc1;
+	};
+
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		bootph-pre-ram;
+	};
 };
 
 &wdog1 {

arch/arm/dts/imx6q-apalis-eval-u-boot.dtsi

@@ -5,18 +5,30 @@
 
 #include "imx6qdl-u-boot.dtsi"
 
-&{/aliases} {
+/ {
-	/* U-Boot won't find PMIC otherwise */
+	aliases {
-	i2c0 = &i2c1;
+		/* U-Boot won't find PMIC otherwise */
-	i2c1 = &i2c2;
+		i2c0 = &i2c1;
-	i2c2 = &i2c3;
+		i2c1 = &i2c2;
-	/*
+		i2c2 = &i2c3;
-	 * SDHCI instance order: eMMC, 8-bit SD/MMC, 4-bit SD
+		/*
-	 * (U-Boot won't find ConfigBlock otherwise)
+		 * SDHCI instance order: eMMC, 8-bit SD/MMC, 4-bit SD
-	 */
+		 * (U-Boot won't find ConfigBlock otherwise)
-	mmc0 = &usdhc3;
+		 */
-	mmc1 = &usdhc1;
+		mmc0 = &usdhc3;
-	mmc2 = &usdhc2;
+		mmc1 = &usdhc1;
+		mmc2 = &usdhc2;
+	};
+
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		bootph-pre-ram;
+	};
 };
 
 &wdog1 {

arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi

@@ -7,12 +7,6 @@
 
 #include "imx6ul-opos6ul-u-boot.dtsi"
 
-/ {
-	aliases {
-		display0 = &lcdif;
-	};
-};
-
 &aips1 {
 	bootph-pre-ram;
 
@@ -22,7 +16,29 @@
 };
 
 &lcdif {
+	display = <&display0>;
 	bootph-some-ram;
+
+	display0: display0 {
+		bits-per-pixel = <18>;
+		bus-width = <18>;
+
+		display-timings {
+			timing0 {
+				clock-frequency = <33300000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <36>;
+				hfront-porch = <210>;
+				vback-porch = <13>;
+				vfront-porch = <22>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
 };
 
 &pinctrl_uart1 {

arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi

@@ -9,6 +9,16 @@
 		usb0 = &usbotg1; /* required for ums */
 		display0 = &lcdif;
 	};
+
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		bootph-pre-ram;
+	};
 };
 
 &pinctrl_uart1 {
@@ -54,3 +64,7 @@
 		};
 	};
 };
+
+&wdog1 {
+	bootph-pre-ram;
+};

arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi

@@ -5,10 +5,16 @@
 
 #include "imx7s-u-boot.dtsi"
 
-&{/aliases} {
+/ {
-	/* SDHCI instance order: eMMC, SD/MMC */
+	aliases {
-	mmc0 = &usdhc3;
+		/* SDHCI instance order: eMMC, SD/MMC */
-	mmc1 = &usdhc1;
+		mmc0 = &usdhc3;
+		mmc1 = &usdhc1;
+	};
+
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
 };
 
 &lcdif {

arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi

@@ -6,6 +6,16 @@
 #include "imx8mm-u-boot.dtsi"
 
 / {
+	aliases {
+		eeprom0 = &eeprom_module;
+		eeprom1 = &eeprom_carrier_board;
+		eeprom2 = &eeprom_display_adapter;
+	};
+
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+
 	wdt-reboot {
 		compatible = "wdt-reboot";
 		bootph-pre-ram;
@@ -13,12 +23,6 @@
 	};
 };
 
-&{/aliases} {
-	eeprom0 = &eeprom_module;
-	eeprom1 = &eeprom_carrier_board;
-	eeprom2 = &eeprom_display_adapter;
-};
-
 &{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
 	bootph-pre-ram;
 };

arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi

@@ -6,6 +6,13 @@
 #include "imx8mp-u-boot.dtsi"
 
 / {
+	/* U-Boot does not yet have a proper PCIe clk driver */
+	pcie0_refclk: clock-pcie {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
 	wdt-reboot {
 		compatible = "wdt-reboot";
 		wdt = <&wdog1>;
@@ -13,6 +20,10 @@
 	};
 };
 
+&pcie_phy {
+	clocks = <&pcie0_refclk>;
+};
+
 &{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
 	bootph-pre-ram;
 };

arch/arm/dts/imx8mp-beacon-kit.dts

@@ -23,6 +23,12 @@
 		stdout-path = &uart2;
 	};
 
+	clk_xtal25: clock-xtal25 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
 	connector {
 		compatible = "usb-c-connector";
 		label = "USB-C";
@@ -49,6 +55,12 @@
 		};
 	};
 
+	dmic_codec: dmic-codec {
+		compatible = "dmic-codec";
+		num-channels = <1>;
+		#sound-dai-cells = <0>;
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -82,6 +94,17 @@
 		};
 	};
 
+	bridge-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&adv7535_out>;
+			};
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
@@ -112,10 +135,13 @@
 		};
 	};
 
-	pcie0_refclk: clock-pcie {
+	reg_audio: regulator-wm8962 {
-		compatible = "fixed-clock";
+		compatible = "regulator-fixed";
-		#clock-cells = <0>;
+		regulator-name = "3v3_aud";
-		clock-frequency = <100000000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
 	};
 
 	reg_usdhc2_vmmc: regulator-usdhc2 {
@@ -137,6 +163,68 @@
 		gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 	};
+
+	sound-adv7535 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "sound-adv7535";
+		simple-audio-card,format = "i2s";
+
+		simple-audio-card,cpu {
+			sound-dai = <&sai5>;
+			system-clock-direction-out;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&adv_bridge>;
+		};
+	};
+
+	sound-dmic {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "sound-pdm";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&dailink_master>;
+		simple-audio-card,frame-master = <&dailink_master>;
+
+		dailink_master: simple-audio-card,cpu {
+			sound-dai = <&micfil>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&dmic_codec>;
+		};
+	};
+
+	sound-wm8962 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "wm8962";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,widgets = "Headphone", "Headphones",
+					    "Microphone", "Headset Mic",
+					    "Speaker", "Speaker";
+		simple-audio-card,routing = "Headphones", "HPOUTL",
+					    "Headphones", "HPOUTR",
+					    "Speaker", "SPKOUTL",
+					    "Speaker", "SPKOUTR",
+					    "Headset Mic", "MICBIAS",
+					    "IN3R", "Headset Mic";
+
+		simple-audio-card,cpu {
+			sound-dai = <&sai3>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&wm8962>;
+			clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
+			frame-master;
+			bitclock-master;
+		};
+	};
+};
+
+&audio_blk_ctrl {
+	assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>;
+	assigned-clock-rates = <393216000>, <135475200>;
 };
 
 &ecspi2 {
@@ -146,7 +234,7 @@
 	status = "okay";
 
 	tpm: tpm@0 {
-		compatible = "infineon,slb9670";
+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
 		reg = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_tpm>;
@@ -211,6 +299,42 @@
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
+
+	adv_bridge: hdmi@3d {
+		compatible = "adi,adv7535";
+		reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
+		reg-names = "main", "cec", "edid", "packet";
+		adi,dsi-lanes = <4>;
+		#sound-dai-cells = <0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				adv7535_in: endpoint {
+					remote-endpoint = <&dsi_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				adv7535_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
+
+	pcieclk: clock-generator@68 {
+		compatible = "renesas,9fgv0241";
+		reg = <0x68>;
+		clocks = <&clk_xtal25>;
+		#clock-cells = <1>;
+	};
 };
 
 &i2c3 {
@@ -239,6 +363,34 @@
 	clock-frequency = <384000>;
 	status = "okay";
 
+	wm8962: audio-codec@1a {
+		compatible = "wlf,wm8962";
+		reg = <0x1a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_wm8962>;
+		clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
+		assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
+		assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
+		assigned-clock-rates = <22576000>;
+		DCVDD-supply = <&reg_audio>;
+		DBVDD-supply = <&reg_audio>;
+		AVDD-supply = <&reg_audio>;
+		CPVDD-supply = <&reg_audio>;
+		MICVDD-supply = <&reg_audio>;
+		PLLVDD-supply = <&reg_audio>;
+		SPKVDD1-supply = <&reg_audio>;
+		SPKVDD2-supply = <&reg_audio>;
+		gpio-cfg = <
+			0x0000 /* 0:Default */
+			0x0000 /* 1:Default */
+			0x0000 /* 2:FN_DMICCLK */
+			0x0000 /* 3:Default */
+			0x0000 /* 4:FN_DMICCDAT */
+			0x0000 /* 5:Default */
+		>;
+		#sound-dai-cells = <0>;
+	};
+
 	pca6416: gpio@20 {
 		compatible = "nxp,pcal6416";
 		reg = <0x20>;
@@ -301,6 +453,34 @@
 	};
 };
 
+&lcdif1 {
+	status = "okay";
+};
+
+&micfil {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pdm>;
+	assigned-clocks = <&clk IMX8MP_CLK_PDM>;
+	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <49152000>;
+	status = "okay";
+};
+
+&mipi_dsi {
+	samsung,esc-clock-frequency = <10000000>;
+	status = "okay";
+
+	ports {
+		port@1 {
+			reg = <1>;
+
+			dsi_out: endpoint {
+				remote-endpoint = <&adv7535_in>;
+			};
+		};
+	};
+};
+
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie>;
@@ -309,12 +489,34 @@
 };
 
 &pcie_phy {
+	fsl,clkreq-unsupported;
 	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
-	clocks = <&pcie0_refclk>;
+	clocks = <&pcieclk 1>;
 	clock-names = "ref";
 	status = "okay";
 };
 
+&sai3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai3>;
+	assigned-clocks = <&clk IMX8MP_CLK_SAI3>,
+			  <&clk IMX8MP_AUDIO_PLL2> ;
+	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
+	assigned-clock-rates = <12288000>, <361267200>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
+
+&sai5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai5>;
+	assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
+	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <12288000>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
@@ -471,12 +673,37 @@
 		>;
 	};
 
+	pinctrl_pdm: pdmgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK		0xd6
+			MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00	0xd6
+		>;
+	};
+
 	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
 		>;
 	};
 
+	pinctrl_sai3: sai3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6
+			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6
+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6
+			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6
+			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0xd6
+		>;
+	};
+
+	pinctrl_sai5: sai5grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00	0xd6
+			MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK	0xd6
+			MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC	0xd6
+		>;
+	};
+
 	pinctrl_tpm: tpmgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00	0x19 /* Reset */
@@ -547,4 +774,10 @@
 			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
 		>;
 	};
+
+	pinctrl_wm8962: wm8962grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1	0x59
+		>;
+	};
 };

arch/arm/dts/imx8mp-beacon-som.dtsi

@@ -50,6 +50,8 @@
 	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy0>;
 	snps,force_thresh_dma_mode;
+	snps,mtl-rx-config = <&mtl_rx_setup>;
+	snps,mtl-tx-config = <&mtl_tx_setup>;
 	status = "okay";
 
 	mdio {
@@ -66,6 +68,71 @@
 			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 		};
 	};
+
+	mtl_rx_setup: rx-queues-config {
+		snps,rx-queues-to-use = <5>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,priority = <0x1>;
+			snps,map-to-dma-channel = <0>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,priority = <0x2>;
+			snps,map-to-dma-channel = <1>;
+		};
+
+		queue2 {
+			snps,dcb-algorithm;
+			snps,priority = <0x4>;
+			snps,map-to-dma-channel = <2>;
+		};
+
+		queue3 {
+			snps,dcb-algorithm;
+			snps,priority = <0x8>;
+			snps,map-to-dma-channel = <3>;
+		};
+
+		queue4 {
+			snps,dcb-algorithm;
+			snps,priority = <0xf0>;
+			snps,map-to-dma-channel = <4>;
+		};
+	};
+
+	mtl_tx_setup: tx-queues-config {
+		snps,tx-queues-to-use = <5>;
+		snps,tx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,priority = <0x2>;
+		};
+
+		queue2 {
+			snps,dcb-algorithm;
+			snps,priority = <0x4>;
+		};
+
+		queue3 {
+			snps,dcb-algorithm;
+			snps,priority = <0x8>;
+		};
+
+		queue4 {
+			snps,dcb-algorithm;
+			snps,priority = <0xf0>;
+		};
+	};
 };
 
 &flexspi {
@@ -206,6 +273,10 @@
 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
 	uart-has-rtscts;
 	status = "okay";
+
+	bluetooth {
+		compatible = "nxp,88w8997-bt";
+	};
 };
 
 &usdhc1 {

arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi

@@ -6,6 +6,16 @@
 #include "imx8mp-u-boot.dtsi"
 
 / {
+	aliases {
+		eeprom0 = &eeprom_module;
+		eeprom1 = &eeprom_carrier_board;
+		eeprom2 = &eeprom_display_adapter;
+	};
+
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+
 	wdt-reboot {
 		compatible = "wdt-reboot";
 		bootph-pre-ram;
@@ -13,12 +23,6 @@
 	};
 };
 
-&{/aliases} {
-	eeprom0 = &eeprom_module;
-	eeprom1 = &eeprom_carrier_board;
-	eeprom2 = &eeprom_display_adapter;
-};
-
 &clk {
 	bootph-all;
 	bootph-pre-ram;

arch/arm/dts/k3-am625-verdin-r5.dts

@@ -23,7 +23,7 @@
 		 */
 		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>;
 		assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>;
-		assigned-clock-rates = <200000000>, <1200000000>, <25000000>;
+		assigned-clock-rates = <200000000>, <1000000000>, <25000000>;
 		clocks = <&k3_clks 61 0>;
 		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
 				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,

arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi

@@ -19,6 +19,10 @@
 	memory@80000000 {
 		bootph-all;
 	};
+
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
 };
 
 &main_timer0 {

arch/arm/dts/r9a07g044.dtsi

@@ -223,20 +223,20 @@
 				     <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
 				     <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
-					  "tgiv0", "tgie0", "tgif0",
+					  "tciv0", "tgie0", "tgif0",
-					  "tgia1", "tgib1", "tgiv1", "tgiu1",
+					  "tgia1", "tgib1", "tciv1", "tciu1",
-					  "tgia2", "tgib2", "tgiv2", "tgiu2",
+					  "tgia2", "tgib2", "tciv2", "tciu2",
 					  "tgia3", "tgib3", "tgic3", "tgid3",
-					  "tgiv3",
+					  "tciv3",
 					  "tgia4", "tgib4", "tgic4", "tgid4",
-					  "tgiv4",
+					  "tciv4",
 					  "tgiu5", "tgiv5", "tgiw5",
 					  "tgia6", "tgib6", "tgic6", "tgid6",
-					  "tgiv6",
+					  "tciv6",
 					  "tgia7", "tgib7", "tgic7", "tgid7",
-					  "tgiv7",
+					  "tciv7",
 					  "tgia8", "tgib8", "tgic8", "tgid8",
-					  "tgiv8", "tgiu8";
+					  "tciv8", "tciu8";
 			clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
 			power-domains = <&cpg>;
 			resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;

arch/arm/dts/r9a07g044l2-smarc.dts

@@ -6,6 +6,27 @@
  */
 
 /dts-v1/;
+
+/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0	1
+
+/*
+ * To enable MTU3a PWM on PMOD0,
+ * Disable PMOD1_SER0 by setting "#define PMOD1_SER0	0" above and
+ * enable PMOD_MTU3 by setting "#define PMOD_MTU3	1" below.
+ */
+#define PMOD_MTU3	0
+
+#if (PMOD_MTU3 && PMOD1_SER0)
+#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
+#endif
+
+#define MTU3_COUNTER_Z_PHASE_SIGNAL	0
+
+#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
+#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
+#endif
+
 #include "r9a07g044l2.dtsi"
 #include "rzg2l-smarc-som.dtsi"
 #include "rzg2l-smarc-pinfunction.dtsi"

arch/arm/dts/rz-smarc-common.dtsi

@@ -32,12 +32,6 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	audio_mclock: audio_mclock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <11289600>;
-	};
-
 	snd_rzg2l: sound {
 		compatible = "simple-audio-card";
 		simple-audio-card,format = "i2s";
@@ -55,7 +49,7 @@
 		};
 
 		codec_dai: simple-audio-card,codec {
-			clocks = <&audio_mclock>;
+			clocks = <&versa3 2>;
 			sound-dai = <&wm8978>;
 		};
 	};
@@ -76,13 +70,19 @@
 		gpios-states = <1>;
 		states = <3300000 1>, <1800000 0>;
 	};
+
+	x1: x1-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+	};
 };
 
-&audio_clk1{
+&audio_clk1 {
 	clock-frequency = <11289600>;
 };
 
-&audio_clk2{
+&audio_clk2 {
 	clock-frequency = <12288000>;
 };
 

arch/arm/dts/rzg2l-smarc-pinfunction.dtsi

@@ -53,6 +53,26 @@
 			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
 	};
 
+	mtu3_pins: mtu3 {
+		mtu3-ext-clk-input-pin {
+			pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
+				 <RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */
+		};
+
+		mtu3-pwm {
+			pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
+				 <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
+				 <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
+				 <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
+		};
+
+#if MTU3_COUNTER_Z_PHASE_SIGNAL
+		mtu3-zphase-clk {
+			pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */
+		};
+#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
+	};
+
 	scif0_pins: scif0 {
 		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
 			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */

arch/arm/dts/rzg2l-smarc-som.dtsi

@@ -73,6 +73,13 @@
 		gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
 		regulator-always-on;
 	};
+
+	/* 32.768kHz crystal */
+	x2: x2-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+	};
 };
 
 &adc {
@@ -100,7 +107,7 @@
 		rxc-skew-psec = <2400>;
 		txc-skew-psec = <2400>;
 		rxdv-skew-psec = <0>;
-		txdv-skew-psec = <0>;
+		txen-skew-psec = <0>;
 		rxd0-skew-psec = <0>;
 		rxd1-skew-psec = <0>;
 		rxd2-skew-psec = <0>;
@@ -128,7 +135,7 @@
 		rxc-skew-psec = <2400>;
 		txc-skew-psec = <2400>;
 		rxdv-skew-psec = <0>;
-		txdv-skew-psec = <0>;
+		txen-skew-psec = <0>;
 		rxd0-skew-psec = <0>;
 		rxd1-skew-psec = <0>;
 		rxd2-skew-psec = <0>;
@@ -148,6 +155,17 @@
 	mali-supply = <&reg_1p1v>;
 };
 
+&i2c3 {
+	raa215300: pmic@12 {
+		compatible = "renesas,raa215300";
+		reg = <0x12>, <0x6f>;
+		reg-names = "main", "rtc";
+
+		clocks = <&x2>;
+		clock-names = "xin";
+	};
+};
+
 &ostm1 {
 	status = "okay";
 };

arch/arm/dts/rzg2l-smarc.dtsi

@@ -8,9 +8,6 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 
-/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
-#define PMOD1_SER0	1
-
 / {
 	aliases {
 		serial1 = &scif2;
@@ -113,8 +110,48 @@
 		#sound-dai-cells = <0>;
 		reg = <0x1a>;
 	};
+
+	versa3: clock-generator@68 {
+		compatible = "renesas,5p35023";
+		reg = <0x68>;
+		#clock-cells = <1>;
+		clocks = <&x1>;
+
+		renesas,settings = [
+			80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
+			00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
+			80 b0 45 c4 95
+		];
+
+		assigned-clocks = <&versa3 0>, <&versa3 1>,
+				  <&versa3 2>, <&versa3 3>,
+				  <&versa3 4>, <&versa3 5>;
+		assigned-clock-rates = <24000000>, <11289600>,
+				       <11289600>, <12000000>,
+				       <25000000>, <12288000>;
+	};
 };
 
+#if PMOD_MTU3
+&mtu3 {
+	pinctrl-0 = <&mtu3_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+#if MTU3_COUNTER_Z_PHASE_SIGNAL
+/* SDHI cd pin is muxed with counter Z phase signal */
+&sdhi1 {
+	status = "disabled";
+};
+#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
+
+&spi1 {
+	status = "disabled";
+};
+#endif /* PMOD_MTU3 */
+
 /*
  * To enable SCIF2 (SER0) on PMOD1 (CN7)
  * SW1 should be at position 2->3 so that SER0_CTS# line is activated

arch/arm/dts/tegra124-apalis-u-boot.dtsi

@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ */
+
+#include "tegra124-u-boot.dtsi"
+
+/ {
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+};

arch/arm/dts/tegra20-colibri-u-boot.dtsi

@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ */
+
+#include "tegra20-u-boot.dtsi"
+
+/ {
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+};

arch/arm/dts/tegra30-apalis-u-boot.dtsi

@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ */
+
+#include "tegra30-u-boot.dtsi"
+
+/ {
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+};

arch/arm/dts/tegra30-colibri-u-boot.dtsi

@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ */
+
+#include "tegra30-u-boot.dtsi"
+
+/ {
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+};

arch/arm/dts/vf610-colibri-eval-v3-u-boot.dtsi

@@ -7,6 +7,10 @@
 	soc {
 		bootph-all;
 	};
+
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
 };
 
 &aips0 {

arch/arm/include/asm/arch-sunxi/dram.h

@@ -40,5 +40,6 @@
 unsigned long sunxi_dram_init(void);
 void mctl_await_completion(u32 *reg, u32 mask, u32 val);
 bool mctl_mem_matches(u32 offset);
+bool mctl_mem_matches_base(u32 offset, ulong base);
 
 #endif /* _SUNXI_DRAM_H */

arch/arm/mach-imx/imx9/container.cfg

@@ -7,4 +7,5 @@ BOOT_FROM SD 0x400
 SOC_TYPE IMX9
 CONTAINER
 IMAGE A55 bl31.bin 0x204E0000
-IMAGE A55 u-boot.bin CONFIG_TEXT_BASE
+IMAGE A55 u-boot.bin CONFIG_TEXT_BASE
+IMAGE A55 tee.bin 0x96000000

arch/arm/mach-imx/imx9/imximage.cfg

@@ -5,6 +5,6 @@
 
 BOOT_FROM SD 0x400
 SOC_TYPE IMX9
-APPEND mx93a0-ahab-container.img
+APPEND mx93a1-ahab-container.img
 CONTAINER
 IMAGE A55 u-boot-spl-ddr.bin 0x2049A000

arch/arm/mach-k3/am62a7_init.c

@@ -69,20 +69,6 @@ static void ctrl_mmr_unlock(void)
 	mmr_unlock(PADCFG_MMR1_BASE, 1);
 }
 
-#if (IS_ENABLED(CONFIG_CPU_V7R))
-static void setup_qos(void)
-{
-	u32 i;
-
-	for (i = 0; i < am62a_qos_count; i++)
-		writel(am62a_qos_data[i].val, (uintptr_t)am62a_qos_data[i].reg);
-}
-#else
-static void setup_qos(void)
-{
-}
-#endif
-
 void board_init_f(ulong dummy)
 {
 	struct udevice *dev;

arch/arm/mach-k3/common.c

@@ -28,6 +28,8 @@
 #include <elf.h>
 #include <soc.h>
 
+#include <asm/arch/k3-qos.h>
+
 struct ti_sci_handle *get_ti_sci_handle(void)
 {
 	struct udevice *dev;
@@ -284,3 +286,13 @@ int misc_init_r(void)
 void __weak do_board_detect(void)
 {
 }
+
+#if (IS_ENABLED(CONFIG_K3_QOS))
+void setup_qos(void)
+{
+	u32 i;
+
+	for (i = 0; i < qos_count; i++)
+		writel(qos_data[i].val, (uintptr_t)qos_data[i].reg);
+}
+#endif

arch/arm/mach-k3/common.h

@@ -45,3 +45,11 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size);
 struct ti_sci_handle *get_ti_sci_handle(void);
 void do_board_detect(void);
 void ti_secure_image_check_binary(void **p_image, size_t *p_size);
+
+#if (IS_ENABLED(CONFIG_K3_QOS))
+void setup_qos(void);
+#else
+static inline void setup_qos(void)
+{
+}
+#endif

arch/arm/mach-k3/include/mach/hardware.h

@@ -30,7 +30,6 @@
 
 #ifdef CONFIG_SOC_K3_AM62A7
 #include "am62a_hardware.h"
-#include "am62a_qos.h"
 #endif
 
 #ifdef CONFIG_SOC_K3_J784S4
@@ -102,12 +101,4 @@ struct rom_extended_boot_data {
 	u32 num_components;
 };
 
-struct k3_qos_data {
-	u32 reg;
-	u32 val;
-};
-
-extern struct k3_qos_data am62a_qos_data[];
-extern u32 am62a_qos_count;
-
 #endif /* _ASM_ARCH_HARDWARE_H_ */

arch/arm/mach-k3/include/mach/k3-qos.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Quality of Service (QoS) Configuration Header File
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#ifndef _K3_QOS_H_
+#define _K3_QOS_H_
+
+#include <linux/kernel.h>
+
+struct k3_qos_data {
+	u32 reg;
+	u32 val;
+};
+
+#if (IS_ENABLED(CONFIG_K3_QOS))
+extern struct k3_qos_data qos_data[];
+extern u32 qos_count;
+#endif
+
+#endif /* _K3_QOS_H_ */

arch/arm/mach-k3/r5/Kconfig

@@ -1,6 +1,14 @@
 config K3_LOAD_SYSFW
 	bool
 
+config K3_QOS
+	bool "Enable Quality of Service (QoS) Settings for TI K3 SoCs"
+	default y if SOC_K3_AM62A7
+	help
+	  This option enables the R5 SPL to apply QoS settings for various
+	  HW controllers inside the TI K3 SoCs. The files for QoS settings are
+	  generated from Sysconfig and k3-resource-partitioning tools.
+
 config K3_SYSFW_IMAGE_NAME
 	string "File name of SYSFW firmware and configuration blob"
 	depends on K3_LOAD_SYSFW

arch/arm/mach-k3/r5/am62ax/Makefile

@@ -4,4 +4,4 @@
 
 obj-y += clk-data.o
 obj-y += dev-data.o
-obj-y += am62a_qos_data.o
+obj-y += am62a_qos_uboot.o

arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c

@@ -5,10 +5,11 @@
  *
  * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
  */
-#include <asm/arch/hardware.h>
-#include "common.h"
 
-struct k3_qos_data am62a_qos_data[] = {
+#include <asm/arch/k3-qos.h>
+#include "am62a_qos.h"
+
+struct k3_qos_data qos_data[] = {
 	/* modules_qosConfig0 - 1 endpoints, 4 channels */
 	{
 		.reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0,
@@ -43,4 +44,4 @@ struct k3_qos_data am62a_qos_data[] = {
 	},
 };
 
-uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]);
+u32 qos_count = ARRAY_SIZE(qos_data);

arch/arm/mach-renesas/Kconfig

@@ -1,4 +1,4 @@
-if ARCH_RMOBILE
+if ARCH_RENESAS
 
 # Renesas ARM SoCs R-Car Gen3/Gen4 (64bit)
 config RCAR_64
@@ -78,6 +78,7 @@ config RZG2L
 	imply RENESAS_SDHI
 	imply RZG2L_GPIO
 	imply SCIF_CONSOLE
+	imply SYS_I2C_RZ_RIIC
 	imply SYS_MALLOC_F
 	help
 	  Enable support for the Renesas RZ/G2L family of SoCs. Currently
@@ -88,12 +89,12 @@ config RZG2L
 endchoice
 
 config SYS_SOC
-	default "rmobile" if ARCH_RMOBILE
+	default "renesas" if ARCH_RENESAS
 
-source "arch/arm/mach-rmobile/Kconfig.32"
+source "arch/arm/mach-renesas/Kconfig.32"
-source "arch/arm/mach-rmobile/Kconfig.64"
+source "arch/arm/mach-renesas/Kconfig.64"
-source "arch/arm/mach-rmobile/Kconfig.rza1"
+source "arch/arm/mach-renesas/Kconfig.rza1"
-source "arch/arm/mach-rmobile/Kconfig.rzn1"
+source "arch/arm/mach-renesas/Kconfig.rzn1"
-source "arch/arm/mach-rmobile/Kconfig.rzg2l"
+source "arch/arm/mach-renesas/Kconfig.rzg2l"
 
 endif

arch/arm/mach-renesas/Kconfig.32

@@ -1,6 +1,6 @@
 if RCAR_32
 
-config ARCH_RMOBILE_BOARD_STRING
+config ARCH_RENESAS_BOARD_STRING
 	string "Renesas RCar Gen2 board name"
 	default "Board"
 
@@ -10,9 +10,6 @@ config RCAR_GEN2
 	select PHY_RCAR_GEN2
 	select TMU_TIMER
 
-config R8A7740
-	bool "Renesas SoC R8A7740"
-
 config R8A7790
 	bool "Renesas SoC R8A7790"
 	select RCAR_GEN2
@@ -125,7 +122,7 @@ endchoice
 config TMU_TIMER
 	bool
 
-config RMOBILE_EXTRAM_BOOT
+config RENESAS_EXTRAM_BOOT
 	bool "Enable boot from RAM"
 	depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
 

arch/arm/mach-renesas/Kconfig.64

@@ -6,7 +6,7 @@ config SYS_MALLOC_F_LEN
 config OF_LIBFDT_OVERLAY
 	default y if RCAR_64
 
-source "arch/arm/mach-rmobile/Kconfig.rcar3"
+source "arch/arm/mach-renesas/Kconfig.rcar3"
-source "arch/arm/mach-rmobile/Kconfig.rcar4"
+source "arch/arm/mach-renesas/Kconfig.rcar4"
 
 endif

arch/arm/mach-renesas/Makefile

@@ -8,7 +8,6 @@ obj-y += emac.o
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
 obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
-obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o
 obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o

arch/arm/mach-renesas/board.c

@@ -7,10 +7,10 @@
 #include <init.h>
 #include <asm/io.h>
 
-#ifdef CONFIG_ARCH_RMOBILE_BOARD_STRING
+#ifdef CONFIG_ARCH_RENESAS_BOARD_STRING
 int checkboard(void)
 {
-	printf("Board: %s\n", CONFIG_ARCH_RMOBILE_BOARD_STRING);
+	printf("Board: %s\n", CONFIG_ARCH_RENESAS_BOARD_STRING);
 	return 0;
 }
 #endif

arch/arm/mach-renesas/cpu_info-rcar.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
+ * arch/arm/mach-renesas/cpu_info-rcar.c
  *
  * Copyright (C) 2013,2014 Renesas Electronics Corporation
  */
@@ -13,7 +13,7 @@
 #define R8A7796_REV_1_3		0x5211
 #define R8A77995_REV_1_1	0x5810
 
-static u32 rmobile_get_prr(void)
+static u32 renesas_get_prr(void)
 {
 	if (IS_ENABLED(CONFIG_RCAR_64))
 		return readl(0xFFF00044);
@@ -21,14 +21,14 @@ static u32 rmobile_get_prr(void)
 	return readl(0xFF000044);
 }
 
-u32 rmobile_get_cpu_type(void)
+u32 renesas_get_cpu_type(void)
 {
-	return (rmobile_get_prr() & 0x00007F00) >> 8;
+	return (renesas_get_prr() & 0x00007F00) >> 8;
 }
 
-u32 rmobile_get_cpu_rev_integer(void)
+u32 renesas_get_cpu_rev_integer(void)
 {
-	const u32 prr = rmobile_get_prr();
+	const u32 prr = renesas_get_prr();
 	const u32 rev = prr & PRR_MASK;
 
 	if (rev == R8A7796_REV_1_1 || rev == R8A7796_REV_1_3 ||
@@ -38,9 +38,9 @@ u32 rmobile_get_cpu_rev_integer(void)
 		return ((prr & 0x000000F0) >> 4) + 1;
 }
 
-u32 rmobile_get_cpu_rev_fraction(void)
+u32 renesas_get_cpu_rev_fraction(void)
 {
-	const u32 prr = rmobile_get_prr();
+	const u32 prr = renesas_get_prr();
 	const u32 rev = prr & PRR_MASK;
 
 	if (rev == R8A7796_REV_1_1 || rev == R8A77995_REV_1_1)

arch/arm/mach-renesas/cpu_info-rzg2l.c

@@ -4,7 +4,7 @@
  *
  */
 
-#include <mach/rmobile.h>
+#include <mach/renesas.h>
 #include <asm/io.h>
 #include <linux/libfdt.h>
 
@@ -21,7 +21,7 @@ struct tfa_info {
 };
 
 static const struct tfa_info tfa_info[] = {
-	{ "renesas,r9a07g044l2", "R9A07G044L", RMOBILE_CPU_TYPE_R9A07G044L },
+	{ "renesas,r9a07g044l2", "R9A07G044L", RENESAS_CPU_TYPE_R9A07G044L },
 };
 
 static const struct tfa_info invalid_tfa_info = { NULL, "(invalid)", 0 };
@@ -47,17 +47,17 @@ const u8 *rzg_get_cpu_name(void)
 	return get_tfa_info()->cpu_name;
 }
 
-u32 rmobile_get_cpu_type(void)
+u32 renesas_get_cpu_type(void)
 {
 	return get_tfa_info()->cpu_type;
 }
 
-u32 rmobile_get_cpu_rev_integer(void)
+u32 renesas_get_cpu_rev_integer(void)
 {
 	return (readl(SYSC_LSI_DEVID) >> 28) + 1;
 }
 
-u32 rmobile_get_cpu_rev_fraction(void)
+u32 renesas_get_cpu_rev_fraction(void)
 {
 	return 0;
 }

arch/arm/mach-renesas/cpu_info.c

@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012-2021 Renesas Solutions Corp.
+ */
+
+#include <cpu_func.h>
+#include <asm/cache.h>
+#include <init.h>
+#include <asm/io.h>
+#include <env.h>
+#include <linux/ctype.h>
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	icache_enable();
+	return 0;
+}
+#endif
+
+/* R-Car Gen3 and Gen4 D-cache is enabled in memmap-gen3.c */
+#ifndef CONFIG_RCAR_64
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+	dcache_enable();
+}
+#endif
+#endif
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+#if !defined(CONFIG_RZA1) && !defined(CONFIG_RZN1)
+__weak const u8 *rzg_get_cpu_name(void)
+{
+	return 0;
+}
+
+__weak u32 renesas_get_cpu_type(void)
+{
+	return 0x0;
+}
+
+__weak u32 renesas_get_cpu_rev_integer(void)
+{
+	return 0;
+}
+
+__weak u32 renesas_get_cpu_rev_fraction(void)
+{
+	return 0;
+}
+
+/* CPU information table */
+static const struct {
+	u16 cpu_type;
+	u8 cpu_name[10];
+} renesas_cpuinfo[] = {
+	{ RENESAS_CPU_TYPE_R8A7790, "R8A7790" },
+	{ RENESAS_CPU_TYPE_R8A7791, "R8A7791" },
+	{ RENESAS_CPU_TYPE_R8A7792, "R8A7792" },
+	{ RENESAS_CPU_TYPE_R8A7793, "R8A7793" },
+	{ RENESAS_CPU_TYPE_R8A7794, "R8A7794" },
+	{ RENESAS_CPU_TYPE_R8A7795, "R8A7795" },
+	{ RENESAS_CPU_TYPE_R8A7796, "R8A7796" },
+	{ RENESAS_CPU_TYPE_R8A77965, "R8A77965" },
+	{ RENESAS_CPU_TYPE_R8A77970, "R8A77970" },
+	{ RENESAS_CPU_TYPE_R8A77980, "R8A77980" },
+	{ RENESAS_CPU_TYPE_R8A77990, "R8A77990" },
+	{ RENESAS_CPU_TYPE_R8A77995, "R8A77995" },
+	{ RENESAS_CPU_TYPE_R8A779A0, "R8A779A0" },
+	{ RENESAS_CPU_TYPE_R8A779F0, "R8A779F0" },
+	{ RENESAS_CPU_TYPE_R8A779G0, "R8A779G0" },
+	{ RENESAS_CPU_TYPE_R8A779H0, "R8A779H0" },
+	{ 0x0, "CPU" },
+};
+
+static int renesas_cpuinfo_idx(void)
+{
+	u32 cpu_type = renesas_get_cpu_type();
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(renesas_cpuinfo) - 1; i++)
+		if (renesas_cpuinfo[i].cpu_type == cpu_type)
+			return i;
+
+	/* Unknown "CPU" entry */
+	return ARRAY_SIZE(renesas_cpuinfo) - 1;
+}
+
+static const u8 *get_cpu_name(int idx)
+{
+	const  u8 *cpu_name = rzg_get_cpu_name();
+
+	return cpu_name ? cpu_name : renesas_cpuinfo[idx].cpu_name;
+}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	int i, idx = renesas_cpuinfo_idx();
+	const u8 *cpu_name = get_cpu_name(idx);
+	char cpu[10] = { 0 };
+
+	for (i = 0; i < sizeof(cpu); i++)
+		cpu[i] = tolower(cpu_name[i]);
+
+	env_set("platform", cpu);
+
+	return 0;
+}
+#endif
+
+int print_cpuinfo(void)
+{
+	int i = renesas_cpuinfo_idx();
+
+	if (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A7796 &&
+	    renesas_get_cpu_rev_integer() == 1 &&
+	    renesas_get_cpu_rev_fraction() == 1) {
+		printf("CPU:   Renesas Electronics %s rev 1.1/1.2\n", get_cpu_name(i));
+		return 0;
+	}
+
+	printf("CPU:   Renesas Electronics %s rev %d.%d\n",
+		get_cpu_name(i), renesas_get_cpu_rev_integer(),
+		renesas_get_cpu_rev_fraction());
+
+	return 0;
+}
+#elif defined(CONFIG_RZA1)
+int print_cpuinfo(void)
+{
+	printf("CPU: Renesas Electronics RZ/A1\n");
+	return 0;
+}
+#else /* CONFIG_RZN1 */
+int print_cpuinfo(void)
+{
+	printf("CPU: Renesas Electronics RZ/N1\n");
+	return 0;
+}
+#endif
+#endif /* CONFIG_DISPLAY_CPUINFO */

arch/arm/mach-renesas/emac.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * RMOBILE EtherMAC initialization.
+ * Renesas EtherMAC initialization.
  *
  * Copyright (C) 2012  Renesas Solutions Corp.
  * Copyright (C) 2012  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

arch/arm/mach-renesas/include/mach/gpio.h

@@ -0,0 +1,4 @@
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#endif /* __ASM_ARCH_GPIO_H */

arch/arm/mach-renesas/include/mach/r8a7790.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * arch/arm/include/asm/arch-rmobile/r8a7790.h
+ * arch/arm/include/asm/arch-renesas/r8a7790.h
  *
  * Copyright (C) 2013,2014 Renesas Electronics Corporation
  */
@@ -28,6 +28,6 @@
 
 #define R8A7790_CUT_ES2X	2
 #define IS_R8A7790_ES2()	\
-	(rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
+	(renesas_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
 
 #endif /* __ASM_ARCH_R8A7790_H */

arch/arm/mach-renesas/include/mach/r8a7791.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * arch/arm/include/asm/arch-rmobile/r8a7791.h
+ * arch/arm/include/asm/arch-renesas/r8a7791.h
  *
  * Copyright (C) 2013,2014 Renesas Electronics Corporation
  */
@@ -65,6 +65,6 @@
 
 #define R8A7791_CUT_ES2X	2
 #define IS_R8A7791_ES2()	\
-	(rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
+	(renesas_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
 
 #endif /* __ASM_ARCH_R8A7791_H */

arch/arm/mach-renesas/include/mach/r8a7792.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * arch/arm/include/asm/arch-rmobile/r8a7792.h
+ * arch/arm/include/asm/arch-renesas/r8a7792.h
  *
  * Copyright (C) 2016 Renesas Electronics Corporation
  */

arch/arm/mach-renesas/include/mach/r8a7793.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * arch/arm/include/asm/arch-rmobile/r8a7793.h
+ * arch/arm/include/asm/arch-renesas/r8a7793.h
  *
  * Copyright (C) 2014 Renesas Electronics Corporation
  */
@@ -71,6 +71,6 @@
 
 #define R8A7793_CUT_ES2X	2
 #define IS_R8A7793_ES2() \
-	(rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
+	(renesas_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
 
 #endif /* __ASM_ARCH_R8A7793_H */

arch/arm/mach-renesas/include/mach/r8a7794.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * arch/arm/include/asm/arch-rmobile/r8a7794.h
+ * arch/arm/include/asm/arch-renesas/r8a7794.h
  *
  * Copyright (C) 2014 Renesas Electronics Corporation
  */
@@ -28,6 +28,6 @@
 
 #define R8A7794_CUT_ES2		2
 #define IS_R8A7794_ES2()	\
-	(rmobile_get_cpu_rev_integer() == R8A7794_CUT_ES2)
+	(renesas_get_cpu_rev_integer() == R8A7794_CUT_ES2)
 
 #endif /* __ASM_ARCH_R8A7794_H */

arch/arm/mach-renesas/include/mach/rcar-base.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * arch/arm/include/asm/arch-rmobile/rcar-base.h
+ * arch/arm/include/asm/arch-renesas/rcar-base.h
  *
  * Copyright (C) 2013,2014 Renesas Electronics Corporation
  */

arch/arm/mach-renesas/include/mach/rcar-gen3-base.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
+ * ./arch/arm/mach-renesas/include/mach/rcar-gen3-base.h
  *
  * Copyright (C) 2015 Renesas Electronics Corporation
  */

arch/arm/mach-renesas/include/mach/rcar-gen4-base.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * ./arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h
+ * ./arch/arm/mach-renesas/include/mach/rcar-gen4-base.h
  *
  * Copyright (C) 2021 Renesas Electronics Corp.
  */

arch/arm/mach-renesas/include/mach/rcar-mstp.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * arch/arm/include/asm/arch-rmobile/rcar-mstp.h
+ * arch/arm/include/asm/arch-renesas/rcar-mstp.h
  *
  * Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  * Copyright (C) 2013, 2014 Renesas Electronics Corporation

arch/arm/mach-renesas/include/mach/renesas.h

@@ -0,0 +1,56 @@
+#ifndef __ASM_ARCH_RENESAS_H
+#define __ASM_ARCH_RENESAS_H
+
+#if defined(CONFIG_ARCH_RENESAS)
+#if defined(CONFIG_R8A7790)
+#include <asm/arch/r8a7790.h>
+#elif defined(CONFIG_R8A7791)
+#include <asm/arch/r8a7791.h>
+#elif defined(CONFIG_R8A7792)
+#include <asm/arch/r8a7792.h>
+#elif defined(CONFIG_R8A7793)
+#include <asm/arch/r8a7793.h>
+#elif defined(CONFIG_R8A7794)
+#include <asm/arch/r8a7794.h>
+#elif defined(CONFIG_RCAR_GEN3)
+#include <asm/arch/rcar-gen3-base.h>
+#elif defined(CONFIG_RCAR_GEN4)
+#include <asm/arch/rcar-gen4-base.h>
+#elif defined(CONFIG_R7S72100)
+#elif defined(CONFIG_RZG2L)
+#include <asm/arch/rzg2l.h>
+#else
+#error "SOC Name not defined"
+#endif
+#endif /* CONFIG_ARCH_RENESAS */
+
+/* PRR CPU IDs */
+#define RENESAS_CPU_TYPE_R8A7740	0x40
+#define RENESAS_CPU_TYPE_R8A7790	0x45
+#define RENESAS_CPU_TYPE_R8A7791	0x47
+#define RENESAS_CPU_TYPE_R8A7792	0x4A
+#define RENESAS_CPU_TYPE_R8A7793	0x4B
+#define RENESAS_CPU_TYPE_R8A7794	0x4C
+#define RENESAS_CPU_TYPE_R8A7795	0x4F
+#define RENESAS_CPU_TYPE_R8A7796	0x52
+#define RENESAS_CPU_TYPE_R8A77965	0x55
+#define RENESAS_CPU_TYPE_R8A77970	0x54
+#define RENESAS_CPU_TYPE_R8A77980	0x56
+#define RENESAS_CPU_TYPE_R8A77990	0x57
+#define RENESAS_CPU_TYPE_R8A77995	0x58
+#define RENESAS_CPU_TYPE_R8A779A0	0x59
+#define RENESAS_CPU_TYPE_R8A779F0	0x5A
+#define RENESAS_CPU_TYPE_R8A779G0	0x5C
+#define RENESAS_CPU_TYPE_R8A779H0	0x5D
+#define RENESAS_CPU_TYPE_R9A07G044L	0x9A070440
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+const u8 *rzg_get_cpu_name(void);
+u32 renesas_get_cpu_type(void);
+u32 renesas_get_cpu_rev_integer(void);
+u32 renesas_get_cpu_rev_fraction(void);
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_RENESAS_H */

arch/arm/mach-renesas/lowlevel_init_ca15.S

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+ * arch/arm/mach-renesas/lowlevel_init_ca15.S
  *     This file is lager low level initialize.
  *
  * Copyright (C) 2013, 2014 Renesas Electronics Corporation

arch/arm/mach-rmobile/cpu_info-r8a7740.c

@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * (C) Copyright 2012 Renesas Solutions Corp.
- */
-
-#include <asm/io.h>
-
-u32 rmobile_get_cpu_type(void)
-{
-	u32 id;
-	u32 type;
-	struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
-
-	id = readl(hpb->cccr);
-	type = (id >> 8) & 0xFF;
-
-	return type;
-}
-
-u32 rmobile_get_cpu_rev(void)
-{
-	u32 id;
-	u32 rev;
-	struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
-
-	id = readl(hpb->cccr);
-	rev = (id >> 4) & 0xF;
-
-	return rev;
-}

arch/arm/mach-rmobile/cpu_info.c

@@ -1,151 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * (C) Copyright 2012-2021 Renesas Solutions Corp.
- */
-
-#include <cpu_func.h>
-#include <asm/cache.h>
-#include <init.h>
-#include <asm/io.h>
-#include <env.h>
-#include <linux/ctype.h>
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
-	icache_enable();
-	return 0;
-}
-#endif
-
-/* R-Car Gen3 and Gen4 D-cache is enabled in memmap-gen3.c */
-#ifndef CONFIG_RCAR_64
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void enable_caches(void)
-{
-	dcache_enable();
-}
-#endif
-#endif
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-#if !defined(CONFIG_RZA1) && !defined(CONFIG_RZN1)
-__weak const u8 *rzg_get_cpu_name(void)
-{
-	return 0;
-}
-
-static u32 __rmobile_get_cpu_type(void)
-{
-	return 0x0;
-}
-u32 rmobile_get_cpu_type(void)
-		__attribute__((weak, alias("__rmobile_get_cpu_type")));
-
-static u32 __rmobile_get_cpu_rev_integer(void)
-{
-	return 0;
-}
-u32 rmobile_get_cpu_rev_integer(void)
-		__attribute__((weak, alias("__rmobile_get_cpu_rev_integer")));
-
-static u32 __rmobile_get_cpu_rev_fraction(void)
-{
-	return 0;
-}
-u32 rmobile_get_cpu_rev_fraction(void)
-		__attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
-
-/* CPU information table */
-static const struct {
-	u16 cpu_type;
-	u8 cpu_name[10];
-} rmobile_cpuinfo[] = {
-	{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
-	{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
-	{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },
-	{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
-	{ RMOBILE_CPU_TYPE_R8A7793, "R8A7793" },
-	{ RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
-	{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
-	{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
-	{ RMOBILE_CPU_TYPE_R8A77965, "R8A77965" },
-	{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
-	{ RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
-	{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
-	{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
-	{ RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
-	{ RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" },
-	{ RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" },
-	{ RMOBILE_CPU_TYPE_R8A779H0, "R8A779H0" },
-	{ 0x0, "CPU" },
-};
-
-static int rmobile_cpuinfo_idx(void)
-{
-	u32 cpu_type = rmobile_get_cpu_type();
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(rmobile_cpuinfo) - 1; i++)
-		if (rmobile_cpuinfo[i].cpu_type == cpu_type)
-			return i;
-
-	/* Unknown "CPU" entry */
-	return ARRAY_SIZE(rmobile_cpuinfo) - 1;
-}
-
-static const u8 *get_cpu_name(int idx)
-{
-	const  u8 *cpu_name = rzg_get_cpu_name();
-
-	return cpu_name ? cpu_name : rmobile_cpuinfo[idx].cpu_name;
-}
-
-#ifdef CONFIG_ARCH_MISC_INIT
-int arch_misc_init(void)
-{
-	int i, idx = rmobile_cpuinfo_idx();
-	const u8 *cpu_name = get_cpu_name(idx);
-	char cpu[10] = { 0 };
-
-	for (i = 0; i < sizeof(cpu); i++)
-		cpu[i] = tolower(cpu_name[i]);
-
-	env_set("platform", cpu);
-
-	return 0;
-}
-#endif
-
-int print_cpuinfo(void)
-{
-	int i = rmobile_cpuinfo_idx();
-
-	if (rmobile_cpuinfo[i].cpu_type == RMOBILE_CPU_TYPE_R8A7796 &&
-	    rmobile_get_cpu_rev_integer() == 1 &&
-	    rmobile_get_cpu_rev_fraction() == 1) {
-		printf("CPU:   Renesas Electronics %s rev 1.1/1.2\n", get_cpu_name(i));
-		return 0;
-	}
-
-	printf("CPU:   Renesas Electronics %s rev %d.%d\n",
-		get_cpu_name(i), rmobile_get_cpu_rev_integer(),
-		rmobile_get_cpu_rev_fraction());
-
-	return 0;
-}
-#elif defined(CONFIG_RZA1)
-int print_cpuinfo(void)
-{
-	printf("CPU: Renesas Electronics RZ/A1\n");
-	return 0;
-}
-#else /* CONFIG_RZN1 */
-int print_cpuinfo(void)
-{
-	printf("CPU: Renesas Electronics RZ/N1\n");
-	return 0;
-}
-#endif
-#endif /* CONFIG_DISPLAY_CPUINFO */

arch/arm/mach-rmobile/include/mach/gpio.h

@@ -1,9 +0,0 @@
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#if defined(CONFIG_R8A7740)
-#include "r8a7740-gpio.h"
-void r8a7740_pinmux_init(void);
-#endif
-
-#endif /* __ASM_ARCH_GPIO_H */

arch/arm/mach-rmobile/include/mach/mmc.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Renesas SuperH MMCIF driver.
- *
- * Copyright (C)  2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * Copyright (C)  2014 Renesas Electronics Corporation
- */
-#ifndef _RMOBILE_MMC_H_
-#define _RMOBILE_MMC_H_
-
-int mmcif_mmc_init(void);
-
-#endif /* _RMOBILE_MMC_H_ */

arch/arm/mach-rmobile/include/mach/r8a7740-gpio.h

@@ -1,572 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2011  Renesas Solutions Corp.
- * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- */
-
-#ifndef __ASM_R8A7740_H__
-#define __ASM_R8A7740_H__
-
-/*
- * MD_CKx pin
- */
-#define MD_CK2	(1 << 2)
-#define MD_CK1	(1 << 1)
-#define MD_CK0	(1 << 0)
-
-/*
- * Pin Function Controller:
- *	GPIO_FN_xx - GPIO used to select pin function
- *	GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-	/* PORT */
-	GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-	GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-	GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-	GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-	GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-	GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-	GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-	GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-	GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-	GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-	GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-	GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-	GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-	GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-	GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-	GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-	GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-	GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-	GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-	GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-	GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-	GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-	GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-	GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-	GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-	GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-
-	GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-	GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-	GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-	GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-	GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-	GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-	GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-	GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-	GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-	GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-
-	GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-	GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-
-	GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-	GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-
-	GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-	GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-
-	GPIO_PORT210, GPIO_PORT211,
-
-	/* IRQ */
-	GPIO_FN_IRQ0_PORT2,	GPIO_FN_IRQ0_PORT13,
-	GPIO_FN_IRQ1,
-	GPIO_FN_IRQ2_PORT11,	GPIO_FN_IRQ2_PORT12,
-	GPIO_FN_IRQ3_PORT10,	GPIO_FN_IRQ3_PORT14,
-	GPIO_FN_IRQ4_PORT15,	GPIO_FN_IRQ4_PORT172,
-	GPIO_FN_IRQ5_PORT0,	GPIO_FN_IRQ5_PORT1,
-	GPIO_FN_IRQ6_PORT121,	GPIO_FN_IRQ6_PORT173,
-	GPIO_FN_IRQ7_PORT120,	GPIO_FN_IRQ7_PORT209,
-	GPIO_FN_IRQ8,
-	GPIO_FN_IRQ9_PORT118,	GPIO_FN_IRQ9_PORT210,
-	GPIO_FN_IRQ10,
-	GPIO_FN_IRQ11,
-	GPIO_FN_IRQ12_PORT42,	GPIO_FN_IRQ12_PORT97,
-	GPIO_FN_IRQ13_PORT64,	GPIO_FN_IRQ13_PORT98,
-	GPIO_FN_IRQ14_PORT63,	GPIO_FN_IRQ14_PORT99,
-	GPIO_FN_IRQ15_PORT62,	GPIO_FN_IRQ15_PORT100,
-	GPIO_FN_IRQ16_PORT68,	GPIO_FN_IRQ16_PORT211,
-	GPIO_FN_IRQ17,
-	GPIO_FN_IRQ18,
-	GPIO_FN_IRQ19,
-	GPIO_FN_IRQ20,
-	GPIO_FN_IRQ21,
-	GPIO_FN_IRQ22,
-	GPIO_FN_IRQ23,
-	GPIO_FN_IRQ24,
-	GPIO_FN_IRQ25,
-	GPIO_FN_IRQ26_PORT58,	GPIO_FN_IRQ26_PORT81,
-	GPIO_FN_IRQ27_PORT57,	GPIO_FN_IRQ27_PORT168,
-	GPIO_FN_IRQ28_PORT56,	GPIO_FN_IRQ28_PORT169,
-	GPIO_FN_IRQ29_PORT50,	GPIO_FN_IRQ29_PORT170,
-	GPIO_FN_IRQ30_PORT49,	GPIO_FN_IRQ30_PORT171,
-	GPIO_FN_IRQ31_PORT41,	GPIO_FN_IRQ31_PORT167,
-
-	/* Function */
-
-	/* DBGT */
-	GPIO_FN_DBGMDT2,	GPIO_FN_DBGMDT1,	GPIO_FN_DBGMDT0,
-	GPIO_FN_DBGMD10,	GPIO_FN_DBGMD11,	GPIO_FN_DBGMD20,
-	GPIO_FN_DBGMD21,
-
-	/* FSI */
-	GPIO_FN_FSIAISLD_PORT0,		/* FSIAISLD Port 0/5 */
-	GPIO_FN_FSIAISLD_PORT5,
-	GPIO_FN_FSIASPDIF_PORT9,	/* FSIASPDIF Port 9/18 */
-	GPIO_FN_FSIASPDIF_PORT18,
-	GPIO_FN_FSIAOSLD1,	GPIO_FN_FSIAOSLD2,
-	GPIO_FN_FSIAOLR,	GPIO_FN_FSIAOBT,
-	GPIO_FN_FSIAOSLD,	GPIO_FN_FSIAOMC,
-	GPIO_FN_FSIACK,		GPIO_FN_FSIAILR,
-	GPIO_FN_FSIAIBT,
-
-	/* FMSI */
-	GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
-	GPIO_FN_FMSISLD_PORT6,
-	GPIO_FN_FMSIILR,	GPIO_FN_FMSIIBT,
-	GPIO_FN_FMSIOLR,	GPIO_FN_FMSIOBT,
-	GPIO_FN_FMSICK,		GPIO_FN_FMSOILR,
-	GPIO_FN_FMSOIBT,	GPIO_FN_FMSOOLR,
-	GPIO_FN_FMSOOBT,	GPIO_FN_FMSOSLD,
-	GPIO_FN_FMSOCK,
-
-	/* SCIFA0 */
-	GPIO_FN_SCIFA0_SCK,	GPIO_FN_SCIFA0_CTS,
-	GPIO_FN_SCIFA0_RTS,	GPIO_FN_SCIFA0_RXD,
-	GPIO_FN_SCIFA0_TXD,
-
-	/* SCIFA1 */
-	GPIO_FN_SCIFA1_CTS,	GPIO_FN_SCIFA1_SCK,
-	GPIO_FN_SCIFA1_RXD,	GPIO_FN_SCIFA1_TXD,
-	GPIO_FN_SCIFA1_RTS,
-
-	/* SCIFA2 */
-	GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
-	GPIO_FN_SCIFA2_SCK_PORT199,
-	GPIO_FN_SCIFA2_RXD,	GPIO_FN_SCIFA2_TXD,
-	GPIO_FN_SCIFA2_CTS,	GPIO_FN_SCIFA2_RTS,
-
-	/* SCIFA3 */
-	GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
-	GPIO_FN_SCIFA3_SCK_PORT116,
-	GPIO_FN_SCIFA3_CTS_PORT117,
-	GPIO_FN_SCIFA3_RXD_PORT174,
-	GPIO_FN_SCIFA3_TXD_PORT175,
-
-	GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
-	GPIO_FN_SCIFA3_SCK_PORT158,
-	GPIO_FN_SCIFA3_CTS_PORT162,
-	GPIO_FN_SCIFA3_RXD_PORT159,
-	GPIO_FN_SCIFA3_TXD_PORT160,
-
-	/* SCIFA4 */
-	GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
-	GPIO_FN_SCIFA4_TXD_PORT13,
-
-	GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
-	GPIO_FN_SCIFA4_TXD_PORT203,
-
-	GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
-	GPIO_FN_SCIFA4_TXD_PORT93,
-
-	GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
-	GPIO_FN_SCIFA4_SCK_PORT205,
-
-	/* SCIFA5 */
-	GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
-	GPIO_FN_SCIFA5_RXD_PORT10,
-
-	GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
-	GPIO_FN_SCIFA5_TXD_PORT208,
-
-	GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
-	GPIO_FN_SCIFA5_RXD_PORT92,
-
-	GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
-	GPIO_FN_SCIFA5_SCK_PORT206,
-
-	/* SCIFA6 */
-	GPIO_FN_SCIFA6_SCK,	GPIO_FN_SCIFA6_RXD,	GPIO_FN_SCIFA6_TXD,
-
-	/* SCIFA7 */
-	GPIO_FN_SCIFA7_TXD,	GPIO_FN_SCIFA7_RXD,
-
-	/* SCIFAB */
-	GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
-	GPIO_FN_SCIFB_RXD_PORT191,
-	GPIO_FN_SCIFB_TXD_PORT192,
-	GPIO_FN_SCIFB_RTS_PORT186,
-	GPIO_FN_SCIFB_CTS_PORT187,
-
-	GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
-	GPIO_FN_SCIFB_RXD_PORT3,
-	GPIO_FN_SCIFB_TXD_PORT4,
-	GPIO_FN_SCIFB_RTS_PORT172,
-	GPIO_FN_SCIFB_CTS_PORT173,
-
-	/* LCD0 */
-	GPIO_FN_LCDC0_SELECT,
-	GPIO_FN_LCD0_D0,	GPIO_FN_LCD0_D1,	GPIO_FN_LCD0_D2,
-	GPIO_FN_LCD0_D3,	GPIO_FN_LCD0_D4,	GPIO_FN_LCD0_D5,
-	GPIO_FN_LCD0_D6,	GPIO_FN_LCD0_D7,	GPIO_FN_LCD0_D8,
-	GPIO_FN_LCD0_D9,	GPIO_FN_LCD0_D10,	GPIO_FN_LCD0_D11,
-	GPIO_FN_LCD0_D12,	GPIO_FN_LCD0_D13,	GPIO_FN_LCD0_D14,
-	GPIO_FN_LCD0_D15,	GPIO_FN_LCD0_D16,	GPIO_FN_LCD0_D17,
-	GPIO_FN_LCD0_DON,	GPIO_FN_LCD0_VCPWC,	GPIO_FN_LCD0_VEPWC,
-
-	GPIO_FN_LCD0_DCK,	GPIO_FN_LCD0_VSYN, /* for RGB */
-	GPIO_FN_LCD0_HSYN,	GPIO_FN_LCD0_DISP, /* for RGB */
-
-	GPIO_FN_LCD0_WR,	GPIO_FN_LCD0_RD, /* for SYS */
-	GPIO_FN_LCD0_CS,	GPIO_FN_LCD0_RS, /* for SYS */
-
-	GPIO_FN_LCD0_D18_PORT163,	GPIO_FN_LCD0_D19_PORT162,
-	GPIO_FN_LCD0_D20_PORT161,	GPIO_FN_LCD0_D21_PORT158,
-	GPIO_FN_LCD0_D22_PORT160,	GPIO_FN_LCD0_D23_PORT159,
-	GPIO_FN_LCD0_LCLK_PORT165,	 /* MSEL5CR_6_1 */
-
-	GPIO_FN_LCD0_D18_PORT40,	GPIO_FN_LCD0_D19_PORT4,
-	GPIO_FN_LCD0_D20_PORT3,		GPIO_FN_LCD0_D21_PORT2,
-	GPIO_FN_LCD0_D22_PORT0,		GPIO_FN_LCD0_D23_PORT1,
-	GPIO_FN_LCD0_LCLK_PORT102,	/* MSEL5CR_6_0 */
-
-	/* LCD1 */
-	GPIO_FN_LCDC1_SELECT,
-	GPIO_FN_LCD1_D0,	GPIO_FN_LCD1_D1,	GPIO_FN_LCD1_D2,
-	GPIO_FN_LCD1_D3,	GPIO_FN_LCD1_D4,	GPIO_FN_LCD1_D5,
-	GPIO_FN_LCD1_D6,	GPIO_FN_LCD1_D7,	GPIO_FN_LCD1_D8,
-	GPIO_FN_LCD1_D9,	GPIO_FN_LCD1_D10,	GPIO_FN_LCD1_D11,
-	GPIO_FN_LCD1_D12,	GPIO_FN_LCD1_D13,	GPIO_FN_LCD1_D14,
-	GPIO_FN_LCD1_D15,	GPIO_FN_LCD1_D16,	GPIO_FN_LCD1_D17,
-	GPIO_FN_LCD1_D18,	GPIO_FN_LCD1_D19,	GPIO_FN_LCD1_D20,
-	GPIO_FN_LCD1_D21,	GPIO_FN_LCD1_D22,	GPIO_FN_LCD1_D23,
-	GPIO_FN_LCD1_DON,	GPIO_FN_LCD1_VCPWC,
-	GPIO_FN_LCD1_LCLK,	GPIO_FN_LCD1_VEPWC,
-
-	GPIO_FN_LCD1_DCK,	GPIO_FN_LCD1_VSYN, /* for RGB */
-	GPIO_FN_LCD1_HSYN,	GPIO_FN_LCD1_DISP, /* for RGB */
-
-	GPIO_FN_LCD1_WR,	GPIO_FN_LCD1_RD, /* for SYS */
-	GPIO_FN_LCD1_CS,	GPIO_FN_LCD1_RS, /* for SYS */
-
-	/* RSPI */
-	GPIO_FN_RSPI_SSL0_A,	GPIO_FN_RSPI_SSL1_A,
-	GPIO_FN_RSPI_SSL2_A,	GPIO_FN_RSPI_SSL3_A,
-	GPIO_FN_RSPI_MOSI_A,	GPIO_FN_RSPI_MISO_A,
-	GPIO_FN_RSPI_CK_A,
-
-	/* VIO CKO */
-	GPIO_FN_VIO_CKO1,
-	GPIO_FN_VIO_CKO2,
-	GPIO_FN_VIO_CKO_1,
-	GPIO_FN_VIO_CKO,
-
-	/* VIO0 */
-	GPIO_FN_VIO0_D0,	GPIO_FN_VIO0_D1,	GPIO_FN_VIO0_D2,
-	GPIO_FN_VIO0_D3,	GPIO_FN_VIO0_D4,	GPIO_FN_VIO0_D5,
-	GPIO_FN_VIO0_D6,	GPIO_FN_VIO0_D7,	GPIO_FN_VIO0_D8,
-	GPIO_FN_VIO0_D9,	GPIO_FN_VIO0_D10,	GPIO_FN_VIO0_D11,
-	GPIO_FN_VIO0_D12,	GPIO_FN_VIO0_VD,	GPIO_FN_VIO0_HD,
-	GPIO_FN_VIO0_CLK,	GPIO_FN_VIO0_FIELD,
-
-	GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
-	GPIO_FN_VIO0_D14_PORT25,
-	GPIO_FN_VIO0_D15_PORT24,
-
-	GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
-	GPIO_FN_VIO0_D14_PORT95,
-	GPIO_FN_VIO0_D15_PORT96,
-
-	/* VIO1 */
-	GPIO_FN_VIO1_D0,	GPIO_FN_VIO1_D1,	GPIO_FN_VIO1_D2,
-	GPIO_FN_VIO1_D3,	GPIO_FN_VIO1_D4,	GPIO_FN_VIO1_D5,
-	GPIO_FN_VIO1_D6,	GPIO_FN_VIO1_D7,	GPIO_FN_VIO1_VD,
-	GPIO_FN_VIO1_HD,	GPIO_FN_VIO1_CLK,	GPIO_FN_VIO1_FIELD,
-
-	/* TPU0 */
-	GPIO_FN_TPU0TO0,	GPIO_FN_TPU0TO1,
-	GPIO_FN_TPU0TO3,
-	GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
-	GPIO_FN_TPU0TO2_PORT202,
-
-	/* SSP1 0 */
-	GPIO_FN_STP0_IPD0,	GPIO_FN_STP0_IPD1,	GPIO_FN_STP0_IPD2,
-	GPIO_FN_STP0_IPD3,	GPIO_FN_STP0_IPD4,	GPIO_FN_STP0_IPD5,
-	GPIO_FN_STP0_IPD6,	GPIO_FN_STP0_IPD7,	GPIO_FN_STP0_IPEN,
-	GPIO_FN_STP0_IPCLK,	GPIO_FN_STP0_IPSYNC,
-
-	/* SSP1 1 */
-	GPIO_FN_STP1_IPD1,	GPIO_FN_STP1_IPD2,	GPIO_FN_STP1_IPD3,
-	GPIO_FN_STP1_IPD4,	GPIO_FN_STP1_IPD5,	GPIO_FN_STP1_IPD6,
-	GPIO_FN_STP1_IPD7,	GPIO_FN_STP1_IPCLK,	GPIO_FN_STP1_IPSYNC,
-
-	GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
-	GPIO_FN_STP1_IPEN_PORT187,
-
-	GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
-	GPIO_FN_STP1_IPEN_PORT193,
-
-	/* SIM */
-	GPIO_FN_SIM_RST,	GPIO_FN_SIM_CLK,
-	GPIO_FN_SIM_D_PORT22, /* SIM_D  Port 22/199 */
-	GPIO_FN_SIM_D_PORT199,
-
-	/* SDHI0 */
-	GPIO_FN_SDHI0_D0,	GPIO_FN_SDHI0_D1,	GPIO_FN_SDHI0_D2,
-	GPIO_FN_SDHI0_D3,	GPIO_FN_SDHI0_CD,	GPIO_FN_SDHI0_WP,
-	GPIO_FN_SDHI0_CMD,	GPIO_FN_SDHI0_CLK,
-
-	/* SDHI1 */
-	GPIO_FN_SDHI1_D0,	GPIO_FN_SDHI1_D1,	GPIO_FN_SDHI1_D2,
-	GPIO_FN_SDHI1_D3,	GPIO_FN_SDHI1_CD,	GPIO_FN_SDHI1_WP,
-	GPIO_FN_SDHI1_CMD,	GPIO_FN_SDHI1_CLK,
-
-	/* SDHI2 */
-	GPIO_FN_SDHI2_D0,	GPIO_FN_SDHI2_D1,	GPIO_FN_SDHI2_D2,
-	GPIO_FN_SDHI2_D3,	GPIO_FN_SDHI2_CLK,	GPIO_FN_SDHI2_CMD,
-
-	GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
-	GPIO_FN_SDHI2_WP_PORT25,
-
-	GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
-	GPIO_FN_SDHI2_CD_PORT202,
-
-	/* MSIOF2 */
-	GPIO_FN_MSIOF2_TXD,	GPIO_FN_MSIOF2_RXD,	GPIO_FN_MSIOF2_TSCK,
-	GPIO_FN_MSIOF2_SS2,	GPIO_FN_MSIOF2_TSYNC,	GPIO_FN_MSIOF2_SS1,
-	GPIO_FN_MSIOF2_MCK1,	GPIO_FN_MSIOF2_MCK0,	GPIO_FN_MSIOF2_RSYNC,
-	GPIO_FN_MSIOF2_RSCK,
-
-	/* KEYSC */
-	GPIO_FN_KEYIN4,		GPIO_FN_KEYIN5,
-	GPIO_FN_KEYIN6,		GPIO_FN_KEYIN7,
-	GPIO_FN_KEYOUT0,	GPIO_FN_KEYOUT1,	GPIO_FN_KEYOUT2,
-	GPIO_FN_KEYOUT3,	GPIO_FN_KEYOUT4,	GPIO_FN_KEYOUT5,
-	GPIO_FN_KEYOUT6,	GPIO_FN_KEYOUT7,
-
-	GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
-	GPIO_FN_KEYIN1_PORT44,
-	GPIO_FN_KEYIN2_PORT45,
-	GPIO_FN_KEYIN3_PORT46,
-
-	GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
-	GPIO_FN_KEYIN1_PORT57,
-	GPIO_FN_KEYIN2_PORT56,
-	GPIO_FN_KEYIN3_PORT55,
-
-	/* VOU */
-	GPIO_FN_DV_D0,	GPIO_FN_DV_D1,	GPIO_FN_DV_D2,	GPIO_FN_DV_D3,
-	GPIO_FN_DV_D4,	GPIO_FN_DV_D5,	GPIO_FN_DV_D6,	GPIO_FN_DV_D7,
-	GPIO_FN_DV_D8,	GPIO_FN_DV_D9,	GPIO_FN_DV_D10,	GPIO_FN_DV_D11,
-	GPIO_FN_DV_D12,	GPIO_FN_DV_D13,	GPIO_FN_DV_D14,	GPIO_FN_DV_D15,
-	GPIO_FN_DV_CLK,
-	GPIO_FN_DV_VSYNC,
-	GPIO_FN_DV_HSYNC,
-
-	/* MEMC */
-	GPIO_FN_MEMC_AD0,	GPIO_FN_MEMC_AD1,	GPIO_FN_MEMC_AD2,
-	GPIO_FN_MEMC_AD3,	GPIO_FN_MEMC_AD4,	GPIO_FN_MEMC_AD5,
-	GPIO_FN_MEMC_AD6,	GPIO_FN_MEMC_AD7,	GPIO_FN_MEMC_AD8,
-	GPIO_FN_MEMC_AD9,	GPIO_FN_MEMC_AD10,	GPIO_FN_MEMC_AD11,
-	GPIO_FN_MEMC_AD12,	GPIO_FN_MEMC_AD13,	GPIO_FN_MEMC_AD14,
-	GPIO_FN_MEMC_AD15,	GPIO_FN_MEMC_CS0,	GPIO_FN_MEMC_INT,
-	GPIO_FN_MEMC_NWE,	GPIO_FN_MEMC_NOE,
-
-	GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
-	GPIO_FN_MEMC_ADV,
-	GPIO_FN_MEMC_WAIT,
-	GPIO_FN_MEMC_BUSCLK,
-
-	GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
-	GPIO_FN_MEMC_DREQ0,
-	GPIO_FN_MEMC_DREQ1,
-	GPIO_FN_MEMC_A0,
-
-	/* MMC */
-	GPIO_FN_MMC0_D0_PORT68,		GPIO_FN_MMC0_D1_PORT69,
-	GPIO_FN_MMC0_D2_PORT70,		GPIO_FN_MMC0_D3_PORT71,
-	GPIO_FN_MMC0_D4_PORT72,		GPIO_FN_MMC0_D5_PORT73,
-	GPIO_FN_MMC0_D6_PORT74,		GPIO_FN_MMC0_D7_PORT75,
-	GPIO_FN_MMC0_CLK_PORT66,
-	GPIO_FN_MMC0_CMD_PORT67,	/* MSEL4CR_15_0 */
-
-	GPIO_FN_MMC1_D0_PORT149,	GPIO_FN_MMC1_D1_PORT148,
-	GPIO_FN_MMC1_D2_PORT147,	GPIO_FN_MMC1_D3_PORT146,
-	GPIO_FN_MMC1_D4_PORT145,	GPIO_FN_MMC1_D5_PORT144,
-	GPIO_FN_MMC1_D6_PORT143,	GPIO_FN_MMC1_D7_PORT142,
-	GPIO_FN_MMC1_CLK_PORT103,
-	GPIO_FN_MMC1_CMD_PORT104,	/* MSEL4CR_15_1 */
-
-	/* MSIOF0 */
-	GPIO_FN_MSIOF0_SS1,	GPIO_FN_MSIOF0_SS2,
-	GPIO_FN_MSIOF0_RXD,	GPIO_FN_MSIOF0_TXD,
-	GPIO_FN_MSIOF0_MCK0,	GPIO_FN_MSIOF0_MCK1,
-	GPIO_FN_MSIOF0_RSYNC,	GPIO_FN_MSIOF0_RSCK,
-	GPIO_FN_MSIOF0_TSCK,	GPIO_FN_MSIOF0_TSYNC,
-
-	/* MSIOF1 */
-	GPIO_FN_MSIOF1_RSCK,	GPIO_FN_MSIOF1_RSYNC,
-	GPIO_FN_MSIOF1_MCK0,	GPIO_FN_MSIOF1_MCK1,
-
-	GPIO_FN_MSIOF1_SS2_PORT116,	GPIO_FN_MSIOF1_SS1_PORT117,
-	GPIO_FN_MSIOF1_RXD_PORT118,	GPIO_FN_MSIOF1_TXD_PORT119,
-	GPIO_FN_MSIOF1_TSYNC_PORT120,
-	GPIO_FN_MSIOF1_TSCK_PORT121,	/* MSEL4CR_10_0 */
-
-	GPIO_FN_MSIOF1_SS1_PORT67,	GPIO_FN_MSIOF1_TSCK_PORT72,
-	GPIO_FN_MSIOF1_TSYNC_PORT73,	GPIO_FN_MSIOF1_TXD_PORT74,
-	GPIO_FN_MSIOF1_RXD_PORT75,
-	GPIO_FN_MSIOF1_SS2_PORT202,	/* MSEL4CR_10_1 */
-
-	/* GPIO */
-	GPIO_FN_GPO0,	GPIO_FN_GPI0,
-	GPIO_FN_GPO1,	GPIO_FN_GPI1,
-
-	/* USB0 */
-	GPIO_FN_USB0_OCI,	GPIO_FN_USB0_PPON,	GPIO_FN_VBUS,
-
-	/* USB1 */
-	GPIO_FN_USB1_OCI,	GPIO_FN_USB1_PPON,
-
-	/* BBIF1 */
-	GPIO_FN_BBIF1_RXD,	GPIO_FN_BBIF1_TXD,	GPIO_FN_BBIF1_TSYNC,
-	GPIO_FN_BBIF1_TSCK,	GPIO_FN_BBIF1_RSCK,	GPIO_FN_BBIF1_RSYNC,
-	GPIO_FN_BBIF1_FLOW,	GPIO_FN_BBIF1_RX_FLOW_N,
-
-	/* BBIF2 */
-	GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
-	GPIO_FN_BBIF2_RXD2_PORT60,
-	GPIO_FN_BBIF2_TSYNC2_PORT6,
-	GPIO_FN_BBIF2_TSCK2_PORT59,
-
-	GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
-	GPIO_FN_BBIF2_TXD2_PORT183,
-	GPIO_FN_BBIF2_TSCK2_PORT89,
-	GPIO_FN_BBIF2_TSYNC2_PORT184,
-
-	/* BSC / FLCTL / PCMCIA */
-	GPIO_FN_CS0,	GPIO_FN_CS2,	GPIO_FN_CS4,
-	GPIO_FN_CS5B,	GPIO_FN_CS6A,
-	GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
-	GPIO_FN_CS5A_PORT19,
-	GPIO_FN_IOIS16, /* ? */
-
-	GPIO_FN_A0,	GPIO_FN_A1,	GPIO_FN_A2,	GPIO_FN_A3,
-	GPIO_FN_A4_FOE,		/* share with FLCTL */
-	GPIO_FN_A5_FCDE,	/* share with FLCTL */
-	GPIO_FN_A6,	GPIO_FN_A7,	GPIO_FN_A8,	GPIO_FN_A9,
-	GPIO_FN_A10,	GPIO_FN_A11,	GPIO_FN_A12,	GPIO_FN_A13,
-	GPIO_FN_A14,	GPIO_FN_A15,	GPIO_FN_A16,	GPIO_FN_A17,
-	GPIO_FN_A18,	GPIO_FN_A19,	GPIO_FN_A20,	GPIO_FN_A21,
-	GPIO_FN_A22,	GPIO_FN_A23,	GPIO_FN_A24,	GPIO_FN_A25,
-	GPIO_FN_A26,
-
-	GPIO_FN_D0_NAF0,	GPIO_FN_D1_NAF1,	/* share with FLCTL */
-	GPIO_FN_D2_NAF2,	GPIO_FN_D3_NAF3,	/* share with FLCTL */
-	GPIO_FN_D4_NAF4,	GPIO_FN_D5_NAF5,	/* share with FLCTL */
-	GPIO_FN_D6_NAF6,	GPIO_FN_D7_NAF7,	/* share with FLCTL */
-	GPIO_FN_D8_NAF8,	GPIO_FN_D9_NAF9,	/* share with FLCTL */
-	GPIO_FN_D10_NAF10,	GPIO_FN_D11_NAF11,	/* share with FLCTL */
-	GPIO_FN_D12_NAF12,	GPIO_FN_D13_NAF13,	/* share with FLCTL */
-	GPIO_FN_D14_NAF14,	GPIO_FN_D15_NAF15,	/* share with FLCTL */
-
-	GPIO_FN_D16,	GPIO_FN_D17,	GPIO_FN_D18,	GPIO_FN_D19,
-	GPIO_FN_D20,	GPIO_FN_D21,	GPIO_FN_D22,	GPIO_FN_D23,
-	GPIO_FN_D24,	GPIO_FN_D25,	GPIO_FN_D26,	GPIO_FN_D27,
-	GPIO_FN_D28,	GPIO_FN_D29,	GPIO_FN_D30,	GPIO_FN_D31,
-
-	GPIO_FN_WE0_FWE,	/* share with FLCTL */
-	GPIO_FN_WE1,
-	GPIO_FN_WE2_ICIORD,	/* share with PCMCIA */
-	GPIO_FN_WE3_ICIOWR,	/* share with PCMCIA */
-	GPIO_FN_CKO,	GPIO_FN_BS,	GPIO_FN_RDWR,
-	GPIO_FN_RD_FSC,		/* share with FLCTL */
-	GPIO_FN_WAIT_PORT177,	/* WAIT Port 90/177 */
-	GPIO_FN_WAIT_PORT90,
-
-	GPIO_FN_FCE0,	GPIO_FN_FCE1,	GPIO_FN_FRB, /* FLCTL */
-
-	/* IRDA */
-	GPIO_FN_IRDA_FIRSEL,	GPIO_FN_IRDA_IN,	GPIO_FN_IRDA_OUT,
-
-	/* ATAPI */
-	GPIO_FN_IDE_D0,		GPIO_FN_IDE_D1,		GPIO_FN_IDE_D2,
-	GPIO_FN_IDE_D3,		GPIO_FN_IDE_D4,		GPIO_FN_IDE_D5,
-	GPIO_FN_IDE_D6,		GPIO_FN_IDE_D7,		GPIO_FN_IDE_D8,
-	GPIO_FN_IDE_D9,		GPIO_FN_IDE_D10,	GPIO_FN_IDE_D11,
-	GPIO_FN_IDE_D12,	GPIO_FN_IDE_D13,	GPIO_FN_IDE_D14,
-	GPIO_FN_IDE_D15,	GPIO_FN_IDE_A0,		GPIO_FN_IDE_A1,
-	GPIO_FN_IDE_A2,		GPIO_FN_IDE_CS0,	GPIO_FN_IDE_CS1,
-	GPIO_FN_IDE_IOWR,	GPIO_FN_IDE_IORD,	GPIO_FN_IDE_IORDY,
-	GPIO_FN_IDE_INT,	GPIO_FN_IDE_RST,	GPIO_FN_IDE_DIRECTION,
-	GPIO_FN_IDE_EXBUF_ENB,	GPIO_FN_IDE_IODACK,	GPIO_FN_IDE_IODREQ,
-
-	/* RMII */
-	GPIO_FN_RMII_CRS_DV,	GPIO_FN_RMII_RX_ER,	GPIO_FN_RMII_RXD0,
-	GPIO_FN_RMII_RXD1,	GPIO_FN_RMII_TX_EN,	GPIO_FN_RMII_TXD0,
-	GPIO_FN_RMII_MDC,	GPIO_FN_RMII_TXD1,	GPIO_FN_RMII_MDIO,
-	GPIO_FN_RMII_REF50CK,	/* for RMII */
-	GPIO_FN_RMII_REF125CK,	/* for GMII */
-
-	/* GEther */
-	GPIO_FN_ET_TX_CLK,	GPIO_FN_ET_TX_EN,	GPIO_FN_ET_ETXD0,
-	GPIO_FN_ET_ETXD1,	GPIO_FN_ET_ETXD2,	GPIO_FN_ET_ETXD3,
-	GPIO_FN_ET_ETXD4,	GPIO_FN_ET_ETXD5, /* for GEther */
-	GPIO_FN_ET_ETXD6,	GPIO_FN_ET_ETXD7, /* for GEther */
-	GPIO_FN_ET_COL,		GPIO_FN_ET_TX_ER,
-	GPIO_FN_ET_RX_CLK,	GPIO_FN_ET_RX_DV,
-	GPIO_FN_ET_ERXD0,	GPIO_FN_ET_ERXD1,
-	GPIO_FN_ET_ERXD2,	GPIO_FN_ET_ERXD3,
-	GPIO_FN_ET_ERXD4,	GPIO_FN_ET_ERXD5, /* for GEther */
-	GPIO_FN_ET_ERXD6,	GPIO_FN_ET_ERXD7, /* for GEther */
-	GPIO_FN_ET_RX_ER,	GPIO_FN_ET_CRS,
-	GPIO_FN_ET_MDC,		GPIO_FN_ET_MDIO,
-	GPIO_FN_ET_LINK,	GPIO_FN_ET_PHY_INT,
-	GPIO_FN_ET_WOL,		GPIO_FN_ET_GTX_CLK,
-
-	/* DMA0 */
-	GPIO_FN_DREQ0,		GPIO_FN_DACK0,
-
-	/* DMA1 */
-	GPIO_FN_DREQ1,		GPIO_FN_DACK1,
-
-	/* SYSC */
-	GPIO_FN_RESETOUTS,
-	GPIO_FN_RESETP_PULLUP,
-	GPIO_FN_RESETP_PLAIN,
-
-	/* SDENC */
-	GPIO_FN_SDENC_CPG,
-	GPIO_FN_SDENC_DV_CLKI,
-
-	/* IRREM */
-	GPIO_FN_IROUT,
-
-	/* DEBUG */
-	GPIO_FN_EDEBGREQ_PULLDOWN,
-	GPIO_FN_EDEBGREQ_PULLUP,
-
-	GPIO_FN_TRACEAUD_FROM_VIO,
-	GPIO_FN_TRACEAUD_FROM_LCDC0,
-	GPIO_FN_TRACEAUD_FROM_MEMC,
-};
-
-#endif /* __ASM_R8A7740_H__ */

arch/arm/mach-rmobile/include/mach/r8a7740.h

@@ -1,274 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#ifndef __ASM_ARCH_R8A7740_H
-#define __ASM_ARCH_R8A7740_H
-
-/*
- * R8A7740 I/O Addresses
- */
-
-#define MERAM_BASE	0xE5580000
-#define DDRP_BASE	0xC12A0000
-#define HPB_BASE	0xE6000000
-#define RWDT0_BASE	0xE6020000
-#define RWDT1_BASE	0xE6030000
-#define GPIO_BASE	0xE6050000
-#define CMT1_BASE	0xE6138000
-#define CPG_BASE	0xE6150000
-#define SYSC_BASE	0xE6180000
-#define SDHI0_BASE	0xE6850000
-#define SDHI1_BASE	0xE6860000
-#define MMCIF_BASE	0xE6BD0000
-#define SCIF5_BASE	0xE6CB0000
-#define SCIF6_BASE	0xE6CC0000
-#define DBSC_BASE	0xFE400000
-#define BSC_BASE	0xFEC10000
-#define I2C0_BASE	0xFFF20000
-#define I2C1_BASE	0xE6C20000
-#define TMU_BASE	0xFFF80000
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-/* RWDT */
-struct r8a7740_rwdt {
-	u16 rwtcnt0;	/* 0x00 */
-	u16 dummy0;		/* 0x02 */
-	u16 rwtcsra0;	/* 0x04 */
-	u16 dummy1;		/* 0x06 */
-	u16 rwtcsrb0;	/* 0x08 */
-	u16 dummy2;		/* 0x0A */
-};
-
-/* HPB Semaphore Control Registers */
-struct r8a7740_hpb {
-	u32 hpbctrl0;
-	u32 hpbctrl1;
-	u32 hpbctrl2;
-	u32 cccr;
-	u32 dummy0; /* 0x20 */
-	u32 hpbctrl4;
-	u32 hpbctrl5;
-};
-
-/* CPG */
-struct r8a7740_cpg {
-	u32 frqcra;
-	u32 frqcrb;
-	u32 vclkcr1;
-	u32 vclkcr2;
-	u32 fmsickcr;
-	u32 fmsockcr;
-	u32 fsiackcr;
-	u32 dummy0; /* 0x1c */
-	u32 rtstbcr;
-	u32 systbcr;
-	u32 pllc01cr;
-	u32 pllc2cr;
-	u32 mstpsr0;
-	u32 dummy1; /* 0x34 */
-	u32 mstpsr1;
-	u32 mstpsr5;
-	u32 mstpsr2;
-	u32 dummy2; /* 0x44 */
-	u32 mstpsr3;
-	u32 mstpsr4;
-	u32 dummy3; /* 0x50 */
-	u32 astat;
-	u32 dummy4[4]; /* 0x58 .. 0x64 */
-	u32 ztrckcr;
-	u32 dummy5[5]; /* 0x6c .. 0x7c */
-	u32 subckcr;
-	u32 spuckcr;
-	u32 vouckcr;
-	u32 usbckcr;
-	u32 dummy6[3]; /* 0x90 .. 0x98 */
-	u32 stprckcr;
-	u32 srcr0;
-	u32 dummy7; /* 0xa4 */
-	u32 srcr1;
-	u32 dummy8; /* 0xac */
-	u32 srcr2;
-	u32 dummy9; /* 0xb4 */
-	u32 srcr3;
-	u32 srcr4;
-	u32 dummy10; /* 0xc0 */
-	u32 srcr5;
-	u32 pllc01stpcr;
-	u32 dummy11[5]; /* 0xcc .. 0xdc */
-	u32 frqcrc;
-	u32 frqcrd;
-	u32 dummy12[10]; /* 0xe8 .. 0x10c */
-	u32 rmstpcr0;
-	u32 rmstpcr1;
-	u32 rmstpcr2;
-	u32 rmstpcr3;
-	u32 rmstpcr4;
-	u32 rmstpcr5;
-	u32 dummy13[2]; /* 0x128 .. 0x12c */
-	u32 smstpcr0;
-	u32 smstpcr1;
-	u32 smstpcr2;
-	u32 smstpcr3;
-	u32 smstpcr4;
-	u32 smstpcr5;
-};
-
-/* BSC */
-struct r8a7740_bsc {
-	u32 cmncr;
-	u32 cs0bcr;
-	u32 cs2bcr;
-	u32 dummy0; /* 0x0c */
-	u32 cs4bcr;
-	u32 cs5abcr;
-	u32 cs5bbcr;
-	u32 cs6abcr;
-	u32 dummy1; /* 0x20 */
-	u32 cs0wcr;
-	u32 cs2wcr;
-	u32 dummy2; /* 0x2c */
-	u32 cs4wcr;
-	u32 cs5awcr;
-	u32 cs5bwcr;
-	u32 cs6awcr;
-	u32 dummy3[5]; /* 0x40 .. 0x50 */
-	u32 rbwtcnt;
-	u32 busycr;
-	u32 dummy4[5]; /* 0x5c .. 0x6c */
-	u32 bromtimcr;
-	u32 dummy5[7]; /* 0x74 .. 0x8c */
-	u32 bptcr00;
-	u32 bptcr01;
-	u32 bptcr02;
-	u32 bptcr03;
-	u32 bptcr04;
-	u32 bptcr05;
-	u32 bptcr06;
-	u32 bptcr07;
-	u32 bptcr08;
-	u32 bptcr09;
-	u32 bptcr10;
-	u32 bptcr11;
-	u32 bptcr12;
-	u32 bptcr13;
-	u32 bptcr14;
-	u32 bptcr15;
-	u32 bptcr16;
-	u32 bptcr17;
-	u32 bptcr18;
-	u32 bptcr19;
-	u32 bptcr20;
-	u32 bptcr21;
-	u32 bptcr22;
-	u32 bptcr23;
-	u32 bptcr24;
-	u32 bptcr25;
-	u32 bptcr26;
-	u32 bptcr27;
-	u32 bptcr28;
-	u32 bptcr29;
-	u32 bptcr30;
-	u32 bptcr31;
-	u32 bswcr;
-	u32 dummy6[68]; /* 0x114 .. 0x220 */
-	u32 cs0wcr2;
-	u32 cs2wcr2;
-	u32 dummy7; /* 0x22c */
-	u32 cs4wcr2;
-};
-
-#define CS0WCR2 0xFEC10224
-#define CS2WCR2 0xFEC10228
-#define CS4WCR2 0xFEC10230
-
-/* DDRP */
-struct r8a7740_ddrp {
-	u32 funcctrl;
-	u32 dllctrl;
-	u32 zqcalctrl;
-	u32 zqodtctrl;
-	u32 rdctrl;
-	u32 rdtmg;
-	u32 fifoinit;
-	u32 outctrl;
-	u32 dummy0[50]; /* 0x20 .. 0xe4 */
-	u32 dqcalofs1;
-	u32 dqcalofs2;
-	u32 dummy1[2]; /* 0xf0 .. 0xf4 */
-	u32 dqcalexp;
-};
-
-#define DDRPNCNT 0xE605803C
-#define DDRVREFCNT 0xE61500EC
-
-/* DBSC */
-struct r8a7740_dbsc {
-	u32 dummy0;
-	u32 dbsvcr;
-	u32 dbstate0;
-	u32 dbstate1;
-	u32 dbacen;
-	u32 dbrfen;
-	u32 dbcmd;
-	u32 dbwait;
-	u32 dbkind;
-	u32 dbconf0;
-	u32 dummy1[2]; /* 0x28 .. 0x2c */
-	u32 dbphytype;
-	u32 dummy2[3]; /* 0x34 .. 0x3c */
-	u32 dbtr0;
-	u32 dbtr1;
-	u32 dbtr2;
-	u32 dummy3; /* 0x4c */
-	u32 dbtr3;
-	u32 dbtr4;
-	u32 dbtr5;
-	u32 dbtr6;
-	u32 dbtr7;
-	u32 dbtr8;
-	u32 dbtr9;
-	u32 dbtr10;
-	u32 dbtr11;
-	u32 dbtr12;
-	u32 dbtr13;
-	u32 dbtr14;
-	u32 dbtr15;
-	u32 dbtr16;
-	u32 dbtr17;
-	u32 dbtr18;
-	u32 dbtr19;
-	u32 dummy4[7]; /* 0x94 .. 0xac */
-	u32 dbbl;
-	u32 dummy5[3]; /* 0xb4 .. 0xbc */
-	u32 dbadj0;
-	u32 dbadj1;
-	u32 dbadj2;
-	u32 dummy6[5]; /* 0xcc .. 0xdc */
-	u32 dbrfcnf0;
-	u32 dbrfcnf1;
-	u32 dbrfcnf2;
-	u32 dbrfcnf3;
-	u32 dummy7; /* 0xf0 */
-	u32 dbcalcnf;
-	u32 dbcaltr;
-	u32 dummy8; /* 0xfc */;
-	u32 dbrnk0;
-	u32 dummy9[31]; /* 0x104 .. 0x17C */
-	u32 dbpdncnf;
-	u32 dummy10[7]; /* 0x184 .. 0x19C */
-	u32 dbmrrdr;
-	u32 dummy11[39]; /* 0x1A4 .. 0x23C */
-	u32 dbdfistat;
-	u32 dbdficnt;
-	u32 dummy12[46]; /* 0x248 .. 0x2FC */
-	u32 dbbs0cnt0;
-	u32 dbbs0cnt1;
-};
-
-#endif
-
-#endif /* __ASM_ARCH_R8A7740_H */

arch/arm/mach-rmobile/include/mach/rmobile.h

@@ -1,58 +0,0 @@
-#ifndef __ASM_ARCH_RMOBILE_H
-#define __ASM_ARCH_RMOBILE_H
-
-#if defined(CONFIG_ARCH_RMOBILE)
-#if defined(CONFIG_R8A7740)
-#include <asm/arch/r8a7740.h>
-#elif defined(CONFIG_R8A7790)
-#include <asm/arch/r8a7790.h>
-#elif defined(CONFIG_R8A7791)
-#include <asm/arch/r8a7791.h>
-#elif defined(CONFIG_R8A7792)
-#include <asm/arch/r8a7792.h>
-#elif defined(CONFIG_R8A7793)
-#include <asm/arch/r8a7793.h>
-#elif defined(CONFIG_R8A7794)
-#include <asm/arch/r8a7794.h>
-#elif defined(CONFIG_RCAR_GEN3)
-#include <asm/arch/rcar-gen3-base.h>
-#elif defined(CONFIG_RCAR_GEN4)
-#include <asm/arch/rcar-gen4-base.h>
-#elif defined(CONFIG_R7S72100)
-#elif defined(CONFIG_RZG2L)
-#include <asm/arch/rzg2l.h>
-#else
-#error "SOC Name not defined"
-#endif
-#endif /* CONFIG_ARCH_RMOBILE */
-
-/* PRR CPU IDs */
-#define RMOBILE_CPU_TYPE_R8A7740	0x40
-#define RMOBILE_CPU_TYPE_R8A7790	0x45
-#define RMOBILE_CPU_TYPE_R8A7791	0x47
-#define RMOBILE_CPU_TYPE_R8A7792	0x4A
-#define RMOBILE_CPU_TYPE_R8A7793	0x4B
-#define RMOBILE_CPU_TYPE_R8A7794	0x4C
-#define RMOBILE_CPU_TYPE_R8A7795	0x4F
-#define RMOBILE_CPU_TYPE_R8A7796	0x52
-#define RMOBILE_CPU_TYPE_R8A77965	0x55
-#define RMOBILE_CPU_TYPE_R8A77970	0x54
-#define RMOBILE_CPU_TYPE_R8A77980	0x56
-#define RMOBILE_CPU_TYPE_R8A77990	0x57
-#define RMOBILE_CPU_TYPE_R8A77995	0x58
-#define RMOBILE_CPU_TYPE_R8A779A0	0x59
-#define RMOBILE_CPU_TYPE_R8A779F0	0x5A
-#define RMOBILE_CPU_TYPE_R8A779G0	0x5C
-#define RMOBILE_CPU_TYPE_R8A779H0	0x5D
-#define RMOBILE_CPU_TYPE_R9A07G044L	0x9A070440
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-const u8 *rzg_get_cpu_name(void);
-u32 rmobile_get_cpu_type(void);
-u32 rmobile_get_cpu_rev_integer(void);
-u32 rmobile_get_cpu_rev_fraction(void);
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_ARCH_RMOBILE_H */

arch/arm/mach-rmobile/include/mach/sh_sdhi.h

@@ -1,170 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * drivers/mmc/sh-sdhi.h
- *
- * SD/MMC driver for Renesas rmobile ARM SoCs
- *
- * Copyright (C) 2013-2017 Renesas Electronics Corporation
- * Copyright (C) 2008-2009 Renesas Solutions Corp.
- */
-
-#ifndef _SH_SDHI_H
-#define _SH_SDHI_H
-
-#include <linux/bitops.h>
-#define SDHI_CMD			(0x0000 >> 1)
-#define SDHI_PORTSEL			(0x0004 >> 1)
-#define SDHI_ARG0			(0x0008 >> 1)
-#define SDHI_ARG1			(0x000C >> 1)
-#define SDHI_STOP			(0x0010 >> 1)
-#define SDHI_SECCNT			(0x0014 >> 1)
-#define SDHI_RSP00			(0x0018 >> 1)
-#define SDHI_RSP01			(0x001C >> 1)
-#define SDHI_RSP02			(0x0020 >> 1)
-#define SDHI_RSP03			(0x0024 >> 1)
-#define SDHI_RSP04			(0x0028 >> 1)
-#define SDHI_RSP05			(0x002C >> 1)
-#define SDHI_RSP06			(0x0030 >> 1)
-#define SDHI_RSP07			(0x0034 >> 1)
-#define SDHI_INFO1			(0x0038 >> 1)
-#define SDHI_INFO2			(0x003C >> 1)
-#define SDHI_INFO1_MASK			(0x0040 >> 1)
-#define SDHI_INFO2_MASK			(0x0044 >> 1)
-#define SDHI_CLK_CTRL			(0x0048 >> 1)
-#define SDHI_SIZE			(0x004C >> 1)
-#define SDHI_OPTION			(0x0050 >> 1)
-#define SDHI_ERR_STS1			(0x0058 >> 1)
-#define SDHI_ERR_STS2			(0x005C >> 1)
-#define SDHI_BUF0			(0x0060 >> 1)
-#define SDHI_SDIO_MODE			(0x0068 >> 1)
-#define SDHI_SDIO_INFO1			(0x006C >> 1)
-#define SDHI_SDIO_INFO1_MASK		(0x0070 >> 1)
-#define SDHI_CC_EXT_MODE		(0x01B0 >> 1)
-#define SDHI_SOFT_RST			(0x01C0 >> 1)
-#define SDHI_VERSION			(0x01C4 >> 1)
-#define SDHI_HOST_MODE			(0x01C8 >> 1)
-#define SDHI_SDIF_MODE			(0x01CC >> 1)
-#define SDHI_EXT_SWAP			(0x01E0 >> 1)
-#define SDHI_SD_DMACR			(0x0324 >> 1)
-
-/* SDHI CMD VALUE */
-#define CMD_MASK			0x0000ffff
-
-/* SDHI_PORTSEL */
-#define USE_1PORT			(1 << 8) /* 1 port */
-
-/* SDHI_ARG */
-#define ARG0_MASK			0x0000ffff
-#define ARG1_MASK			0x0000ffff
-
-/* SDHI_STOP */
-#define STOP_SEC_ENABLE			(1 << 8)
-
-/* SDHI_INFO1 */
-#define INFO1_RESP_END			(1 << 0)
-#define INFO1_ACCESS_END		(1 << 2)
-#define INFO1_CARD_RE			(1 << 3)
-#define INFO1_CARD_IN			(1 << 4)
-#define INFO1_ISD0CD			(1 << 5)
-#define INFO1_WRITE_PRO			(1 << 7)
-#define INFO1_DATA3_CARD_RE		(1 << 8)
-#define INFO1_DATA3_CARD_IN		(1 << 9)
-#define INFO1_DATA3			(1 << 10)
-
-/* SDHI_INFO2 */
-#define INFO2_CMD_ERROR			(1 << 0)
-#define INFO2_CRC_ERROR			(1 << 1)
-#define INFO2_END_ERROR			(1 << 2)
-#define INFO2_TIMEOUT			(1 << 3)
-#define INFO2_BUF_ILL_WRITE		(1 << 4)
-#define INFO2_BUF_ILL_READ		(1 << 5)
-#define INFO2_RESP_TIMEOUT		(1 << 6)
-#define INFO2_SDDAT0			(1 << 7)
-#define INFO2_BRE_ENABLE		(1 << 8)
-#define INFO2_BWE_ENABLE		(1 << 9)
-#define INFO2_CBUSY			(1 << 14)
-#define INFO2_ILA			(1 << 15)
-#define INFO2_ALL_ERR			(0x807f)
-
-/* SDHI_INFO1_MASK */
-#define INFO1M_RESP_END			(1 << 0)
-#define INFO1M_ACCESS_END		(1 << 2)
-#define INFO1M_CARD_RE			(1 << 3)
-#define INFO1M_CARD_IN			(1 << 4)
-#define INFO1M_DATA3_CARD_RE		(1 << 8)
-#define INFO1M_DATA3_CARD_IN		(1 << 9)
-#define INFO1M_ALL			(0xffff)
-#define INFO1M_SET			(INFO1M_RESP_END |	\
-					INFO1M_ACCESS_END |	\
-					INFO1M_DATA3_CARD_RE |	\
-					INFO1M_DATA3_CARD_IN)
-
-/* SDHI_INFO2_MASK */
-#define INFO2M_CMD_ERROR		(1 << 0)
-#define INFO2M_CRC_ERROR		(1 << 1)
-#define INFO2M_END_ERROR		(1 << 2)
-#define INFO2M_TIMEOUT			(1 << 3)
-#define INFO2M_BUF_ILL_WRITE		(1 << 4)
-#define INFO2M_BUF_ILL_READ		(1 << 5)
-#define INFO2M_RESP_TIMEOUT		(1 << 6)
-#define INFO2M_BRE_ENABLE		(1 << 8)
-#define INFO2M_BWE_ENABLE		(1 << 9)
-#define INFO2M_ILA			(1 << 15)
-#define INFO2M_ALL			(0xffff)
-#define INFO2M_ALL_ERR			(0x807f)
-
-/* SDHI_CLK_CTRL */
-#define CLK_ENABLE			(1 << 8)
-
-/* SDHI_OPTION */
-#define OPT_BUS_WIDTH_M			(5 << 13)	/* 101b (15-13bit) */
-#define OPT_BUS_WIDTH_1			(4 << 13)	/* bus width = 1 bit */
-#define OPT_BUS_WIDTH_4			(0 << 13)	/* bus width = 4 bit */
-#define OPT_BUS_WIDTH_8			(1 << 13)	/* bus width = 8 bit */
-
-/* SDHI_ERR_STS1 */
-#define ERR_STS1_CRC_ERROR		((1 << 11) | (1 << 10) | (1 << 9) | \
-					(1 << 8) | (1 << 5))
-#define ERR_STS1_CMD_ERROR		((1 << 4) | (1 << 3) | (1 << 2) | \
-					(1 << 1) | (1 << 0))
-
-/* SDHI_ERR_STS2 */
-#define ERR_STS2_RES_TIMEOUT		(1 << 0)
-#define ERR_STS2_RES_STOP_TIMEOUT	((1 << 0) | (1 << 1))
-#define ERR_STS2_SYS_ERROR		((1 << 6) | (1 << 5) | (1 << 4) | \
-					(1 << 3) | (1 << 2) | (1 << 1) | \
-					(1 << 0))
-
-/* SDHI_SDIO_MODE */
-#define SDIO_MODE_ON			(1 << 0)
-#define SDIO_MODE_OFF			(0 << 0)
-
-/* SDHI_SDIO_INFO1 */
-#define SDIO_INFO1_IOIRQ		(1 << 0)
-#define SDIO_INFO1_EXPUB52		(1 << 14)
-#define SDIO_INFO1_EXWT			(1 << 15)
-
-/* SDHI_SDIO_INFO1_MASK */
-#define SDIO_INFO1M_CLEAR		((1 << 1) | (1 << 2))
-#define SDIO_INFO1M_ON			((1 << 15) | (1 << 14) | (1 << 2) | \
-					 (1 << 1) | (1 << 0))
-
-/* SDHI_EXT_SWAP */
-#define SET_SWAP			((1 << 6) | (1 << 7))	/* SWAP */
-
-/* SDHI_SOFT_RST */
-#define SOFT_RST_ON			(0 << 0)
-#define SOFT_RST_OFF			(1 << 0)
-
-#define	CLKDEV_SD_DATA			25000000	/* 25 MHz */
-#define CLKDEV_HS_DATA			50000000	/* 50 MHz */
-#define CLKDEV_MMC_DATA			20000000	/* 20MHz */
-#define	CLKDEV_INIT			400000		/* 100 - 400 KHz */
-
-/* For quirk */
-#define SH_SDHI_QUIRK_16BIT_BUF		BIT(0)
-#define SH_SDHI_QUIRK_64BIT_BUF		BIT(1)
-
-int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks);
-
-#endif /* _SH_SDHI_H */

arch/arm/mach-rmobile/lowlevel_init.S

@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <system-constants.h>
-
-ENTRY(lowlevel_init)
-	ldr		r0, =MERAM_BASE
-	mov		r1, #0x0
-	str		r1, [r0]
-
-	mrc		p15, 0, r0, c0, c0, 5
-	ands	r0, r0, #0xF
-	beq		lowlevel_init__
-	b		wait_interrupt
-
-	.pool
-	.align 4
-
-wait_interrupt:
-#ifdef ICCICR
-	ldr     r1, =ICCICR
-	mov     r2, #0x0
-	str     r2, [r1]
-	mov     r2, #0xF0
-	adds    r1, r1, #4 /* ICCPMR */
-	str     r2, [r1]
-	ldr     r1, =ICCICR
-	mov     r2, #0x1
-	str     r2, [r1]
-#endif
-
-wait_loop:
-	.long	0xE320F003 /* wfi */
-
-	ldr		r2, [r1, #0xC]
-	str		r2, [r1, #0x10]
-
-	ldr		r0, =MERAM_BASE
-	ldr		r2, [r0]
-	cmp		r2, #0
-	movne	pc, r2
-
-	b		wait_loop
-
-wait_loop_end:
-	.pool
-	.align 4
-
-lowlevel_init__:
-
-	mov r0, #0x200000
-
-loop0:
-	subs r0, r0, #1
-	bne  loop0
-
-	ldr sp, MERAM_STACK
-	b s_init
-
-	.pool
-	.align 4
-
-ENDPROC(lowlevel_init)
-	.ltorg
-
-MERAM_STACK:
-	.word LOW_LEVEL_MERAM_STACK

arch/arm/mach-rmobile/pfc-r8a7790.h

@@ -1,139 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- */
-
-#ifndef __PFC_R8A7790_H__
-#define __PFC_R8A7790_H__
-
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-
-#define CPU_32_PORT(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
-	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),	\
-	PORT_1(fn, pfx##31, sfx)
-
-#define CPU_32_PORT2(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
-	PORT_10(fn, pfx##2, sfx)
-
-#if defined(CONFIG_R8A7790)
-#define CPU_32_PORT1(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
-	PORT_10(fn, pfx##2, sfx)				\
-/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */
-#define CPU_ALL_PORT(fn, pfx, sfx)				\
-	CPU_32_PORT(fn, pfx##_0_, sfx),				\
-	CPU_32_PORT1(fn, pfx##_1_, sfx),			\
-	CPU_32_PORT2(fn, pfx##_2_, sfx),			\
-	CPU_32_PORT(fn, pfx##_3_, sfx),				\
-	CPU_32_PORT(fn, pfx##_4_, sfx),				\
-	CPU_32_PORT(fn, pfx##_5_, sfx)
-
-#elif defined(CONFIG_R8A7791)
-#define CPU_32_PORT1(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
-	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
-	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
-	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
-
-/*
- * GP_0_0_DATA -> GP_7_25_DATA
- * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
- *  GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
- */
-#define CPU_ALL_PORT(fn, pfx, sfx)				\
-	CPU_32_PORT(fn, pfx##_0_, sfx),				\
-	CPU_32_PORT1(fn, pfx##_1_, sfx),			\
-	CPU_32_PORT(fn, pfx##_2_, sfx),				\
-	CPU_32_PORT(fn, pfx##_3_, sfx),				\
-	CPU_32_PORT(fn, pfx##_4_, sfx),				\
-	CPU_32_PORT(fn, pfx##_5_, sfx),				\
-	CPU_32_PORT(fn, pfx##_6_, sfx),				\
-	CPU_32_PORT1(fn, pfx##_7_, sfx)
-
-#elif defined(CONFIG_R8A7792)
-/*
- * GP_0_0_DATA -> GP_11_29_DATA
- * (except for GP0[29..31],GP1[23..31],GP3[28..31],GP4[17..31],GP5[17..31]
- *  GP6[17..31],GP7[17..31],GP8[17..31],GP9[17..31],GP11[30..31])
- */
-#define CPU_32_PORT0_28(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
-	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
-	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
-	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx),	\
-	PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx),	\
-	PORT_1(fn, pfx##28, sfx)
-
-#define CPU_32_PORT0_22(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
-	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
-	PORT_1(fn, pfx##22, sfx)
-
-#define CPU_32_PORT0_27(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
-	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
-	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
-	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx),	\
-	PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
-
-#define CPU_32_PORT0_16(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx),					\
-	PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx),	\
-	PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx),	\
-	PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx),	\
-	PORT_1(fn, pfx##16, sfx)
-
-#define CPU_ALL_PORT(fn, pfx, sfx)				\
-	CPU_32_PORT0_28(fn, pfx##_0_, sfx),			\
-	CPU_32_PORT0_22(fn, pfx##_1_, sfx),			\
-	CPU_32_PORT(fn, pfx##_2_, sfx),				\
-	CPU_32_PORT0_27(fn, pfx##_3_, sfx),			\
-	CPU_32_PORT0_16(fn, pfx##_4_, sfx),			\
-	CPU_32_PORT0_16(fn, pfx##_5_, sfx),			\
-	CPU_32_PORT0_16(fn, pfx##_6_, sfx),			\
-	CPU_32_PORT0_16(fn, pfx##_7_, sfx),			\
-	CPU_32_PORT0_16(fn, pfx##_8_, sfx),			\
-	CPU_32_PORT0_16(fn, pfx##_9_, sfx),			\
-	CPU_32_PORT(fn, pfx##_10_, sfx),			\
-	CPU_32_PORT2(fn, pfx##_11_, sfx)
-
-#else
-#error "NO support"
-#endif
-
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,	\
-				       GP##pfx##_IN, GP##pfx##_OUT)
-
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-
-#define GP_ALL(str)	CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, , unused)
-
-#define PORT_10_REV(fn, pfx, sfx)				\
-	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),	\
-	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),	\
-	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),	\
-	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),	\
-	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx)					\
-	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),		\
-	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),	\
-	PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
-
-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
-							  FN_##ipsr, FN_##fn)
-
-#endif /* __PFC_R8A7790_H__ */

arch/arm/mach-sunxi/clock_sun4i.c

@@ -25,6 +25,7 @@ void clock_init_safe(void)
 	       APB0_DIV_1 << APB0_DIV_SHIFT |
 	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 	       &ccm->cpu_ahb_apb0_cfg);
+	sdelay(20);
 	writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
 	sdelay(200);
 	writel(AXI_DIV_1 << AXI_DIV_SHIFT |
@@ -32,6 +33,7 @@ void clock_init_safe(void)
 	       APB0_DIV_1 << APB0_DIV_SHIFT |
 	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 	       &ccm->cpu_ahb_apb0_cfg);
+	sdelay(20);
 #ifdef CONFIG_MACH_SUN7I
 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
 #endif

arch/arm/mach-sunxi/dram_helpers.c

@@ -26,19 +26,39 @@ void mctl_await_completion(u32 *reg, u32 mask, u32 val)
 }
 
 /*
- * Test if memory at offset offset matches memory at begin of DRAM
+ * Test if memory at offset matches memory at a certain base
  *
  * Note: dsb() is not available on ARMv5 in Thumb mode
  */
 #ifndef CONFIG_MACH_SUNIV
-bool mctl_mem_matches(u32 offset)
+bool mctl_mem_matches_base(u32 offset, ulong base)
 {
+	u32 val_base;
+	u32 val_offset;
+	bool ret;
+
+	/* Save original values */
+	val_base = readl(base);
+	val_offset = readl(base + offset);
+
 	/* Try to write different values to RAM at two addresses */
-	writel(0, CFG_SYS_SDRAM_BASE);
+	writel(0, base);
-	writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset);
+	writel(0xaa55aa55, base + offset);
 	dsb();
 	/* Check if the same value is actually observed when reading back */
-	return readl(CFG_SYS_SDRAM_BASE) ==
+	ret = readl(base) == readl(base + offset);
-	       readl((ulong)CFG_SYS_SDRAM_BASE + offset);
+
+	/* Restore original values */
+	writel(val_base, base);
+	writel(val_offset, base + offset);
+	return ret;
+}
+
+/*
+ * Test if memory at offset matches memory at begin of DRAM
+ */
+bool mctl_mem_matches(u32 offset)
+{
+	return mctl_mem_matches_base(offset, CFG_SYS_SDRAM_BASE);
 }
 #endif

arch/arm/mach-sunxi/dram_sunxi_dw.c

@@ -650,19 +650,6 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 	return 0;
 }
 
-/*
- * Test if memory at offset offset matches memory at a certain base
- */
-static bool mctl_mem_matches_base(u32 offset, ulong base)
-{
-	/* Try to write different values to RAM at two addresses */
-	writel(0, base);
-	writel(0xaa55aa55, base + offset);
-	dsb();
-	/* Check if the same value is actually observed when reading back */
-	return readl(base) ==
-	       readl(base + offset);
-}
 
 static void mctl_auto_detect_dram_size_rank(uint16_t socid, struct dram_para *para, ulong base, struct rank_para *rank)
 {

arch/sh/lib/time.c

@@ -16,7 +16,7 @@
 #include <asm/io.h>
 #include <linux/bitops.h>
 
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RENESAS)
 #define TSTR	0x4
 #define TCR0	0x10
 #endif /* CONFIG_CPU_SH4 */

board/armadeus/opos6uldev/opos6uldev.env

@@ -24,7 +24,6 @@ mmcrootfstype=ext4 rootwait
 kernelimg=opos6ul-linux.bin
 splashpos=0,0
 splashimage=CONFIG_SYS_LOAD_ADDR
-videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0
 check_env=if test -n ${flash_env_version};
 	then env default env_version;
 	else env set flash_env_version ${env_version}; env save;

board/beacon/beacon-rzg2m/Kconfig

@@ -1,7 +1,7 @@
 if TARGET_BEACON_RZG2M
 
 config SYS_SOC
-	default "rmobile"
+	default "renesas"
 
 config SYS_BOARD
 	default "beacon-rzg2m"

board/freescale/imx93_evk/spl.c

@@ -20,6 +20,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/arch-mx7ulp/gpio.h>
+#include <asm/mach-imx/ele_api.h>
 #include <asm/mach-imx/syscounter.h>
 #include <asm/sections.h>
 #include <dm/uclass.h>
@@ -43,6 +44,12 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
 
 void spl_board_init(void)
 {
+	int ret;
+
+	ret = ele_start_rng();
+	if (ret)
+		printf("Fail to start RNG: %d\n", ret);
+
 	puts("Normal Boot\n");
 }
 

board/hoperun/hihope-rzg2/Kconfig

@@ -1,7 +1,7 @@
 if TARGET_HIHOPE_RZG2
 
 config SYS_SOC
-	default "rmobile"
+	default "renesas"
 
 config SYS_BOARD
 	default "hihope-rzg2"