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Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD 2014-02-19 10:55:58 +01:00
commit 1feb6e3c92
20 changed files with 1056 additions and 74 deletions
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2
arch/arm/cpu/armv7/zynq/Makefile
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@ -12,3 +12,5 @@ obj-y := timer.o
obj-y += cpu.o
obj-y += ddrc.o
obj-y += slcr.o
obj-y += clk.o
obj-$(CONFIG_SPL_BUILD) += spl.o

664
arch/arm/cpu/armv7/zynq/clk.c Normal file
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@ -0,0 +1,664 @@
/*
* Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
* Copyright (C) 2013 Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <clk.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
/* Board oscillator frequency */
#ifndef CONFIG_ZYNQ_PS_CLK_FREQ
# define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL
#endif
/* Register bitfield defines */
#define PLLCTRL_FBDIV_MASK 0x7f000
#define PLLCTRL_FBDIV_SHIFT 12
#define PLLCTRL_BPFORCE_MASK (1 << 4)
#define PLLCTRL_PWRDWN_MASK 2
#define PLLCTRL_PWRDWN_SHIFT 1
#define PLLCTRL_RESET_MASK 1
#define PLLCTRL_RESET_SHIFT 0
#define ZYNQ_CLK_MAXDIV 0x3f
#define CLK_CTRL_DIV1_SHIFT 20
#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
#define CLK_CTRL_DIV0_SHIFT 8
#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
#define CLK_CTRL_SRCSEL_SHIFT 4
#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
#define CLK_CTRL_DIV2X_SHIFT 26
#define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
#define CLK_CTRL_DIV3X_SHIFT 20
#define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
#define ZYNQ_CLKMUX_SEL_0 0
#define ZYNQ_CLKMUX_SEL_1 1
#define ZYNQ_CLKMUX_SEL_2 2
#define ZYNQ_CLKMUX_SEL_3 3
DECLARE_GLOBAL_DATA_PTR;
struct clk;
/**
* struct clk_ops:
* @set_rate: Function pointer to set_rate() implementation
* @get_rate: Function pointer to get_rate() implementation
*/
struct clk_ops {
int (*set_rate)(struct clk *clk, unsigned long rate);
unsigned long (*get_rate)(struct clk *clk);
};
/**
* struct clk:
* @name: Clock name
* @frequency: Currenct frequency
* @parent: Parent clock
* @flags: Clock flags
* @reg: Clock control register
* @ops: Clock operations
*/
struct clk {
char *name;
unsigned long frequency;
enum zynq_clk parent;
unsigned int flags;
u32 *reg;
struct clk_ops ops;
};
#define ZYNQ_CLK_FLAGS_HAS_2_DIVS 1
static struct clk clks[clk_max];
/**
* __zynq_clk_cpu_get_parent() - Decode clock multiplexer
* @srcsel: Mux select value
* Returns the clock identifier associated with the selected mux input.
*/
static int __zynq_clk_cpu_get_parent(unsigned int srcsel)
{
unsigned int ret;
switch (srcsel) {
case ZYNQ_CLKMUX_SEL_0:
case ZYNQ_CLKMUX_SEL_1:
ret = armpll_clk;
break;
case ZYNQ_CLKMUX_SEL_2:
ret = ddrpll_clk;
break;
case ZYNQ_CLKMUX_SEL_3:
ret = iopll_clk;
break;
default:
ret = armpll_clk;
break;
}
return ret;
}
/**
* ddr2x_get_rate() - Get clock rate of DDR2x clock
* @clk: Clock handle
* Returns the current clock rate of @clk.
*/
static unsigned long ddr2x_get_rate(struct clk *clk)
{
u32 clk_ctrl = readl(clk->reg);
u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
}
/**
* ddr3x_get_rate() - Get clock rate of DDR3x clock
* @clk: Clock handle
* Returns the current clock rate of @clk.
*/
static unsigned long ddr3x_get_rate(struct clk *clk)
{
u32 clk_ctrl = readl(clk->reg);
u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
}
static void init_ddr_clocks(void)
{
u32 div0, div1;
unsigned long prate = zynq_clk_get_rate(ddrpll_clk);
u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
/* DDR2x */
clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl;
clks[ddr2x_clk].parent = ddrpll_clk;
clks[ddr2x_clk].name = "ddr_2x";
clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]);
clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate;
/* DDR3x */
clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl;
clks[ddr3x_clk].parent = ddrpll_clk;
clks[ddr3x_clk].name = "ddr_3x";
clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]);
clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate;
/* DCI */
clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
clks[dci_clk].reg = &slcr_base->dci_clk_ctrl;
clks[dci_clk].parent = ddrpll_clk;
clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
DIV_ROUND_CLOSEST(prate, div0), div1);
clks[dci_clk].name = "dci";
gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
}
static void init_cpu_clocks(void)
{
int clk_621;
u32 reg, div, srcsel;
enum zynq_clk parent;
reg = readl(&slcr_base->arm_clk_ctrl);
clk_621 = readl(&slcr_base->clk_621_true) & 1;
div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
parent = __zynq_clk_cpu_get_parent(srcsel);
/* cpu clocks */
clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl;
clks[cpu_6or4x_clk].parent = parent;
clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST(
zynq_clk_get_rate(parent), div);
clks[cpu_6or4x_clk].name = "cpu_6or4x";
clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl;
clks[cpu_3or2x_clk].parent = cpu_6or4x_clk;
clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2;
clks[cpu_3or2x_clk].name = "cpu_3or2x";
clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl;
clks[cpu_2x_clk].parent = cpu_6or4x_clk;
clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
(2 + clk_621);
clks[cpu_2x_clk].name = "cpu_2x";
clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl;
clks[cpu_1x_clk].parent = cpu_6or4x_clk;
clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
(4 + 2 * clk_621);
clks[cpu_1x_clk].name = "cpu_1x";
}
/**
* periph_calc_two_divs() - Calculate clock dividers
* @cur_rate: Current clock rate
* @tgt_rate: Target clock rate
* @prate: Parent clock rate
* @div0: First divider (output)
* @div1: Second divider (output)
* Returns the actual clock rate possible.
*
* Calculates clock dividers for clocks with two 6-bit dividers.
*/
static unsigned long periph_calc_two_divs(unsigned long cur_rate,
unsigned long tgt_rate, unsigned long prate, u32 *div0,
u32 *div1)
{
long err, best_err = (long)(~0UL >> 1);
unsigned long rate, best_rate = 0;
u32 d0, d1;
for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0),
d1);
err = abs(rate - tgt_rate);
if (err < best_err) {
*div0 = d0;
*div1 = d1;
best_err = err;
best_rate = rate;
}
}
}
return best_rate;
}
/**
* zynq_clk_periph_set_rate() - Set clock rate
* @clk: Handle of the peripheral clock
* @rate: New clock rate
* Sets the clock frequency of @clk to @rate. Returns zero on success.
*/
static int zynq_clk_periph_set_rate(struct clk *clk,
unsigned long rate)
{
u32 ctrl, div0 = 0, div1 = 0;
unsigned long prate, new_rate, cur_rate = clk->frequency;
ctrl = readl(clk->reg);
prate = zynq_clk_get_rate(clk->parent);
ctrl &= ~CLK_CTRL_DIV0_MASK;
if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) {
ctrl &= ~CLK_CTRL_DIV1_MASK;
new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0,
&div1);
ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
} else {
div0 = DIV_ROUND_CLOSEST(prate, rate);
div0 &= ZYNQ_CLK_MAXDIV;
new_rate = DIV_ROUND_CLOSEST(rate, div0);
}
/* write new divs to hardware */
ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
writel(ctrl, clk->reg);
/* update frequency in clk framework */
clk->frequency = new_rate;
return 0;
}
/**
* zynq_clk_periph_get_rate() - Get clock rate
* @clk: Handle of the peripheral clock
* Returns the current clock rate of @clk.
*/
static unsigned long zynq_clk_periph_get_rate(struct clk *clk)
{
u32 clk_ctrl = readl(clk->reg);
u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
u32 div1 = 1;
if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS)
div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
/* a register value of zero == division by 1 */
if (!div0)
div0 = 1;
if (!div1)
div1 = 1;
return
DIV_ROUND_CLOSEST(
DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0),
div1);
}
/**
* __zynq_clk_periph_get_parent() - Decode clock multiplexer
* @srcsel: Mux select value
* Returns the clock identifier associated with the selected mux input.
*/
static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel)
{
switch (srcsel) {
case ZYNQ_CLKMUX_SEL_0:
case ZYNQ_CLKMUX_SEL_1:
return iopll_clk;
case ZYNQ_CLKMUX_SEL_2:
return armpll_clk;
case ZYNQ_CLKMUX_SEL_3:
return ddrpll_clk;
default:
return 0;
}
}
/**
* zynq_clk_periph_get_parent() - Decode clock multiplexer
* @clk: Clock handle
* Returns the clock identifier associated with the selected mux input.
*/
static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk)
{
u32 clk_ctrl = readl(clk->reg);
u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
return __zynq_clk_periph_get_parent(srcsel);
}
/**
* zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
* @clk: Pointer to struct clk for the clock
* @ctrl: Clock control register
* @name: PLL name
* @two_divs: Indicates whether the clock features one or two dividers
*/
static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name,
bool two_divs)
{
clk->name = name;
clk->reg = ctrl;
if (two_divs)
clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS;
clk->parent = zynq_clk_periph_get_parent(clk);
clk->frequency = zynq_clk_periph_get_rate(clk);
clk->ops.get_rate = zynq_clk_periph_get_rate;
clk->ops.set_rate = zynq_clk_periph_set_rate;
return 0;
}
static void init_periph_clocks(void)
{
zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl,
"gem0", 1);
zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl,
"gem1", 1);
zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl,
"smc", 0);
zynq_clk_register_periph_clk(&clks[lqspi_clk],
&slcr_base->lqspi_clk_ctrl, "lqspi", 0);
zynq_clk_register_periph_clk(&clks[sdio0_clk],
&slcr_base->sdio_clk_ctrl, "sdio0", 0);
zynq_clk_register_periph_clk(&clks[sdio1_clk],
&slcr_base->sdio_clk_ctrl, "sdio1", 0);
zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl,
"spi0", 0);
zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl,
"spi1", 0);
zynq_clk_register_periph_clk(&clks[uart0_clk],
&slcr_base->uart_clk_ctrl, "uart0", 0);
zynq_clk_register_periph_clk(&clks[uart1_clk],
&slcr_base->uart_clk_ctrl, "uart1", 0);
zynq_clk_register_periph_clk(&clks[dbg_trc_clk],
&slcr_base->dbg_clk_ctrl, "dbg_trc", 0);
zynq_clk_register_periph_clk(&clks[dbg_apb_clk],
&slcr_base->dbg_clk_ctrl, "dbg_apb", 0);
zynq_clk_register_periph_clk(&clks[pcap_clk],
&slcr_base->pcap_clk_ctrl, "pcap", 0);
zynq_clk_register_periph_clk(&clks[fclk0_clk],
&slcr_base->fpga0_clk_ctrl, "fclk0", 1);
zynq_clk_register_periph_clk(&clks[fclk1_clk],
&slcr_base->fpga1_clk_ctrl, "fclk1", 1);
zynq_clk_register_periph_clk(&clks[fclk2_clk],
&slcr_base->fpga2_clk_ctrl, "fclk2", 1);
zynq_clk_register_periph_clk(&clks[fclk3_clk],
&slcr_base->fpga3_clk_ctrl, "fclk3", 1);
}
/**
* zynq_clk_register_aper_clk() - Set up a APER clock with the framework
* @clk: Pointer to struct clk for the clock
* @ctrl: Clock control register
* @name: PLL name
*/
static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name)
{
clk->name = name;
clk->reg = ctrl;
clk->parent = cpu_1x_clk;
clk->frequency = zynq_clk_get_rate(clk->parent);
}
static void init_aper_clocks(void)
{
zynq_clk_register_aper_clk(&clks[usb0_aper_clk],
&slcr_base->aper_clk_ctrl, "usb0_aper");
zynq_clk_register_aper_clk(&clks[usb1_aper_clk],
&slcr_base->aper_clk_ctrl, "usb1_aper");
zynq_clk_register_aper_clk(&clks[gem0_aper_clk],
&slcr_base->aper_clk_ctrl, "gem0_aper");
zynq_clk_register_aper_clk(&clks[gem1_aper_clk],
&slcr_base->aper_clk_ctrl, "gem1_aper");
zynq_clk_register_aper_clk(&clks[sdio0_aper_clk],
&slcr_base->aper_clk_ctrl, "sdio0_aper");
zynq_clk_register_aper_clk(&clks[sdio1_aper_clk],
&slcr_base->aper_clk_ctrl, "sdio1_aper");
zynq_clk_register_aper_clk(&clks[spi0_aper_clk],
&slcr_base->aper_clk_ctrl, "spi0_aper");
zynq_clk_register_aper_clk(&clks[spi1_aper_clk],
&slcr_base->aper_clk_ctrl, "spi1_aper");
zynq_clk_register_aper_clk(&clks[can0_aper_clk],
&slcr_base->aper_clk_ctrl, "can0_aper");
zynq_clk_register_aper_clk(&clks[can1_aper_clk],
&slcr_base->aper_clk_ctrl, "can1_aper");
zynq_clk_register_aper_clk(&clks[i2c0_aper_clk],
&slcr_base->aper_clk_ctrl, "i2c0_aper");
zynq_clk_register_aper_clk(&clks[i2c1_aper_clk],
&slcr_base->aper_clk_ctrl, "i2c1_aper");
zynq_clk_register_aper_clk(&clks[uart0_aper_clk],
&slcr_base->aper_clk_ctrl, "uart0_aper");
zynq_clk_register_aper_clk(&clks[uart1_aper_clk],
&slcr_base->aper_clk_ctrl, "uart1_aper");
zynq_clk_register_aper_clk(&clks[gpio_aper_clk],
&slcr_base->aper_clk_ctrl, "gpio_aper");
zynq_clk_register_aper_clk(&clks[lqspi_aper_clk],
&slcr_base->aper_clk_ctrl, "lqspi_aper");
zynq_clk_register_aper_clk(&clks[smc_aper_clk],
&slcr_base->aper_clk_ctrl, "smc_aper");
}
/**
* __zynq_clk_pll_get_rate() - Get PLL rate
* @addr: Address of the PLL's control register
* Returns the current PLL output rate.
*/
static unsigned long __zynq_clk_pll_get_rate(u32 *addr)
{
u32 reg, mul, bypass;
reg = readl(addr);
bypass = reg & PLLCTRL_BPFORCE_MASK;
if (bypass)
mul = 1;
else
mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
return CONFIG_ZYNQ_PS_CLK_FREQ * mul;
}
/**
* zynq_clk_pll_get_rate() - Get PLL rate
* @pll: Handle of the PLL
* Returns the current clock rate of @pll.
*/
static unsigned long zynq_clk_pll_get_rate(struct clk *pll)
{
return __zynq_clk_pll_get_rate(pll->reg);
}
/**
* zynq_clk_register_pll() - Set up a PLL with the framework
* @clk: Pointer to struct clk for the PLL
* @ctrl: PLL control register
* @name: PLL name
* @prate: PLL input clock rate
*/
static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl, char *name,
unsigned long prate)
{
clk->name = name;
clk->reg = ctrl;
clk->frequency = zynq_clk_pll_get_rate(clk);
clk->ops.get_rate = zynq_clk_pll_get_rate;
}
/**
* clkid_2_register() - Get clock control register
* @id: Clock identifier of one of the PLLs
* Returns the address of the requested PLL's control register.
*/
static u32 *clkid_2_register(enum zynq_clk id)
{
switch (id) {
case armpll_clk:
return &slcr_base->arm_pll_ctrl;
case ddrpll_clk:
return &slcr_base->ddr_pll_ctrl;
case iopll_clk:
return &slcr_base->io_pll_ctrl;
default:
return &slcr_base->io_pll_ctrl;
}
}
/* API */
/**
* zynq_clk_early_init() - Early init for the clock framework
*
* This function is called from before relocation and sets up the CPU clock
* frequency in the global data struct.
*/
void zynq_clk_early_init(void)
{
u32 reg = readl(&slcr_base->arm_clk_ctrl);
u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel);
u32 *pllreg = clkid_2_register(parent);
unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
if (!div)
div = 1;
gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div);
}
/**
* get_uart_clk() - Get UART input frequency
* @dev_index: UART ID
* Returns UART input clock frequency in Hz.
*
* Compared to zynq_clk_get_rate() this function is designed to work before
* relocation and can be called when the serial UART is set up.
*/
unsigned long get_uart_clk(int dev_index)
{
u32 reg = readl(&slcr_base->uart_clk_ctrl);
u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel);
u32 *pllreg = clkid_2_register(parent);
unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
if (!div)
div = 1;
return DIV_ROUND_CLOSEST(prate, div);
}
/**
* set_cpu_clk_info() - Initialize clock framework
* Always returns zero.
*
* This function is called from common code after relocation and sets up the
* clock framework. The framework must not be used before this function had been
* called.
*/
int set_cpu_clk_info(void)
{
zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl,
"armpll", CONFIG_ZYNQ_PS_CLK_FREQ);
zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl,
"ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ);
zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl,
"iopll", CONFIG_ZYNQ_PS_CLK_FREQ);
init_ddr_clocks();
init_cpu_clocks();
init_periph_clocks();
init_aper_clocks();
gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
gd->bd->bi_dsp_freq = 0;
return 0;
}
/**
* zynq_clk_get_rate() - Get clock rate
* @clk: Clock identifier
* Returns the current clock rate of @clk on success or zero for an invalid
* clock id.
*/
unsigned long zynq_clk_get_rate(enum zynq_clk clk)
{
if (clk < 0 || clk >= clk_max)
return 0;
return clks[clk].frequency;
}
/**
* zynq_clk_set_rate() - Set clock rate
* @clk: Clock identifier
* @rate: Requested clock rate
* Passes on the return value from the clock's set_rate() function or negative
* errno.
*/
int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate)
{
if (clk < 0 || clk >= clk_max)
return -ENODEV;
if (clks[clk].ops.set_rate)
return clks[clk].ops.set_rate(&clks[clk], rate);
return -ENXIO;
}
/**
* zynq_clk_get_name() - Get clock name
* @clk: Clock identifier
* Returns the name of @clk.
*/
const char *zynq_clk_get_name(enum zynq_clk clk)
{
return clks[clk].name;
}
/**
* soc_clk_dump() - Print clock frequencies
* Returns zero on success
*
* Implementation for the clk dump command.
*/
int soc_clk_dump(void)
{
int i;
printf("clk\t\tfrequency\n");
for (i = 0; i < clk_max; i++) {
const char *name = zynq_clk_get_name(i);
if (name)
printf("%10s%20lu\n", name, zynq_clk_get_rate(i));
}
return 0;
}

14
arch/arm/cpu/armv7/zynq/cpu.c
View File

@ -6,6 +6,7 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
@ -16,7 +17,7 @@ void lowlevel_init(void)
int arch_cpu_init(void)
{
zynq_slcr_unlock();
#ifndef CONFIG_SPL_BUILD
/* Device config APB, unlock the PCAP */
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
@ -34,7 +35,8 @@ int arch_cpu_init(void)
/* Urgent write, ports S2/S3 */
writel(0xC, &slcr_base->ddr_urgent);
#endif
#endif
zynq_clk_early_init();
zynq_slcr_lock();
return 0;
@ -46,3 +48,11 @@ void reset_cpu(ulong addr)
while (1)
;
}
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif

17
arch/arm/cpu/armv7/zynq/slcr.c
View File

@ -8,6 +8,7 @@
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
#define SLCR_LOCK_MAGIC 0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
@ -50,8 +51,10 @@ void zynq_slcr_cpu_reset(void)
}
/* Setup clk for network */
void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{
int ret;
zynq_slcr_unlock();
if (gem_id > 1) {
@ -59,16 +62,16 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
goto out;
}
ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
if (ret)
goto out;
if (gem_id) {
/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
writel(clk, &slcr_base->gem1_clk_ctrl);
/* Configure GEM_RCLK_CTRL */
writel(rclk, &slcr_base->gem1_rclk_ctrl);
writel(1, &slcr_base->gem1_rclk_ctrl);
} else {
/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
writel(clk, &slcr_base->gem0_clk_ctrl);
/* Configure GEM_RCLK_CTRL */
writel(rclk, &slcr_base->gem0_rclk_ctrl);
writel(1, &slcr_base->gem0_rclk_ctrl);
}
udelay(100000);
out:

69
arch/arm/cpu/armv7/zynq/spl.c Normal file
View File

@ -0,0 +1,69 @@
/*
* (C) Copyright 2014 Xilinx, Inc. Michal Simek
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
void board_init_f(ulong dummy)
{
ps7_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* Set global data pointer. */
gd = &gdata;
preloader_console_init();
arch_cpu_init();
board_init_r(NULL, 0);
}
u32 spl_boot_device(void)
{
u32 mode;
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
#ifdef CONFIG_SPL_SPI_SUPPORT
case ZYNQ_BM_QSPI:
puts("qspi boot\n");
mode = BOOT_DEVICE_SPI;
break;
#endif
#ifdef CONFIG_SPL_MMC_SUPPORT
case ZYNQ_BM_SD:
puts("mmc boot\n");
mode = BOOT_DEVICE_MMC1;
break;
#endif
default:
puts("Unsupported boot mode selected\n");
hang();
}
return mode;
}
#ifdef CONFIG_SPL_MMC_SUPPORT
u32 spl_boot_mode(void)
{
return MMCSD_MODE_FAT;
}
#endif
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
/* boot linux */
return 0;
}
#endif

14
arch/arm/cpu/armv7/zynq/timer.c
View File

@ -29,6 +29,7 @@
#include <div64.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
DECLARE_GLOBAL_DATA_PTR;
@ -48,7 +49,6 @@ static struct scu_timer *timer_base =
#define TIMER_LOAD_VAL 0xFFFFFFFF
#define TIMER_PRESCALE 255
#define TIMER_TICK_HZ (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE)
int timer_init(void)
{
@ -56,6 +56,8 @@ int timer_init(void)
(TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
SCUTIMER_CONTROL_ENABLE_MASK;
gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
/* Load the timer counter register */
writel(0xFFFFFFFF, &timer_base->load);
@ -69,7 +71,7 @@ int timer_init(void)
/* Reset time */
gd->arch.lastinc = readl(&timer_base->counter) /
(TIMER_TICK_HZ / CONFIG_SYS_HZ);
(gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
gd->arch.tbl = 0;
return 0;
@ -83,14 +85,15 @@ ulong get_timer_masked(void)
{
ulong now;
now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
now = readl(&timer_base->counter) /
(gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
if (gd->arch.lastinc >= now) {
/* Normal mode */
gd->arch.tbl += gd->arch.lastinc - now;
} else {
/* We have an overflow ... */
gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now;
gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now + 1;
}
gd->arch.lastinc = now;
@ -107,7 +110,8 @@ void __udelay(unsigned long usec)
if (usec == 0)
return;
countticks = lldiv(TIMER_TICK_HZ * usec, 1000000);
countticks = lldiv(((unsigned long long)gd->arch.timer_rate_hz * usec),
1000000);
/* decrementing timer */
timeend = readl(&timer_base->counter) - countticks;

61
arch/arm/cpu/armv7/zynq/u-boot-spl.lds Normal file
View File

@ -0,0 +1,61 @@
/*
* Copyright (c) 2014 Xilinx, Inc. Michal Simek
* Copyright (c) 2004-2008 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = ALIGN(4);
.text :
{
__image_copy_start = .;
CPUDIR/start.o (.text*)
*(.text*)
} > .sram
. = ALIGN(4);
.rodata : {
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
} > .sram
. = ALIGN(4);
.data : {
*(.data*)
} > .sram
. = ALIGN(4);
. = .;
__image_copy_end = .;
_end = .;
/* Move BSS section to RAM because of FAT */
.bss (NOLOAD) : {
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
} > .sdram
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}

29
arch/arm/include/asm/arch-zynq/clk.h Normal file
View File

@ -0,0 +1,29 @@
/*
* Copyright (c) 2013 Xilinx Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ZYNQ_CLK_H_
#define _ZYNQ_CLK_H_
enum zynq_clk {
armpll_clk, ddrpll_clk, iopll_clk,
cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk,
ddr2x_clk, ddr3x_clk, dci_clk,
lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk,
fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk,
sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk,
usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk,
sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk,
can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk,
uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};
void zynq_clk_early_init(void);
int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate);
unsigned long zynq_clk_get_rate(enum zynq_clk clk);
const char *zynq_clk_get_name(enum zynq_clk clk);
unsigned long get_uart_clk(int dev_id);
#endif

40
arch/arm/include/asm/arch-zynq/hardware.h
View File

@ -7,6 +7,8 @@
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
#define ZYNQ_SERIAL_BASEADDR0 0xE0000000
#define ZYNQ_SERIAL_BASEADDR1 0xE0001000
#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
#define ZYNQ_SCU_BASEADDR 0xF8F00000
@ -21,17 +23,51 @@
#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
/* Bootmode setting values */
#define ZYNQ_BM_MASK 0xF
#define ZYNQ_BM_NOR 0x2
#define ZYNQ_BM_SD 0x5
#define ZYNQ_BM_JTAG 0x0
/* Reflect slcr offsets */
struct slcr_regs {
u32 scl; /* 0x0 */
u32 slcr_lock; /* 0x4 */
u32 slcr_unlock; /* 0x8 */
u32 reserved0[75];
u32 reserved0_1[61];
u32 arm_pll_ctrl; /* 0x100 */
u32 ddr_pll_ctrl; /* 0x104 */
u32 io_pll_ctrl; /* 0x108 */
u32 reserved0_2[5];
u32 arm_clk_ctrl; /* 0x120 */
u32 ddr_clk_ctrl; /* 0x124 */
u32 dci_clk_ctrl; /* 0x128 */
u32 aper_clk_ctrl; /* 0x12c */
u32 reserved0_3[2];
u32 gem0_rclk_ctrl; /* 0x138 */
u32 gem1_rclk_ctrl; /* 0x13c */
u32 gem0_clk_ctrl; /* 0x140 */
u32 gem1_clk_ctrl; /* 0x144 */
u32 reserved1[46];
u32 smc_clk_ctrl; /* 0x148 */
u32 lqspi_clk_ctrl; /* 0x14c */
u32 sdio_clk_ctrl; /* 0x150 */
u32 uart_clk_ctrl; /* 0x154 */
u32 spi_clk_ctrl; /* 0x158 */
u32 can_clk_ctrl; /* 0x15c */
u32 can_mioclk_ctrl; /* 0x160 */
u32 dbg_clk_ctrl; /* 0x164 */
u32 pcap_clk_ctrl; /* 0x168 */
u32 reserved0_4[1];
u32 fpga0_clk_ctrl; /* 0x170 */
u32 reserved0_5[3];
u32 fpga1_clk_ctrl; /* 0x180 */
u32 reserved0_6[3];
u32 fpga2_clk_ctrl; /* 0x190 */
u32 reserved0_7[3];
u32 fpga3_clk_ctrl; /* 0x1a0 */
u32 reserved0_8[8];
u32 clk_621_true; /* 0x1c4 */
u32 reserved1[14];
u32 pss_rst_ctrl; /* 0x200 */
u32 reserved2[15];
u32 fpga_rst_ctrl; /* 0x240 */

18
arch/arm/include/asm/arch-zynq/spl.h Normal file
View File

@ -0,0 +1,18 @@
/*
* (C) Copyright 2014 Xilinx, Inc. Michal Simek
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
extern void ps7_init(void);
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_RAM 1
#define BOOT_DEVICE_SPI 2
#define BOOT_DEVICE_MMC1 3
#define BOOT_DEVICE_MMC2 4
#define BOOT_DEVICE_MMC2_2 5
#endif

2
arch/arm/include/asm/arch-zynq/sys_proto.h
View File

@ -10,7 +10,7 @@
extern void zynq_slcr_lock(void);
extern void zynq_slcr_unlock(void);
extern void zynq_slcr_cpu_reset(void);
extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
extern void zynq_slcr_devcfg_disable(void);
extern void zynq_slcr_devcfg_enable(void);
extern u32 zynq_slcr_get_boot_mode(void);

1
board/xilinx/zynq/Makefile
View File

@ -6,3 +6,4 @@
#
obj-y := board.o
obj-$(CONFIG_SPL_BUILD) += ps7_init.o

10
board/xilinx/zynq/board.c
View File

@ -12,12 +12,6 @@
DECLARE_GLOBAL_DATA_PTR;
/* Bootmode setting values */
#define ZYNQ_BM_MASK 0x0F
#define ZYNQ_BM_NOR 0x02
#define ZYNQ_BM_SD 0x05
#define ZYNQ_BM_JTAG 0x0
#ifdef CONFIG_FPGA
Xilinx_desc fpga;
@ -59,8 +53,6 @@ int board_init(void)
}
#endif
icache_enable();
#ifdef CONFIG_FPGA
fpga_init();
fpga_add(fpga_xilinx, &fpga);
@ -89,7 +81,6 @@ int board_late_init(void)
return 0;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
u32 ret = 0;
@ -123,7 +114,6 @@ int board_eth_init(bd_t *bis)
#endif
return ret;
}
#endif
#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bd)

12
board/xilinx/zynq/ps7_init.c Normal file
View File

@ -0,0 +1,12 @@
/*
* (C) Copyright 2014 Xilinx, Inc. Michal Simek
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/spl.h>
__weak void ps7_init(void)
{
puts("Please copy ps7_init.c/h from hw project\n");
}

20
drivers/net/zynq_gem.c
View File

@ -90,6 +90,11 @@
#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
/* Clock frequencies for different speeds */
#define ZYNQ_GEM_FREQUENCY_10 2500000UL
#define ZYNQ_GEM_FREQUENCY_100 25000000UL
#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
/* Device registers */
struct zynq_gem_regs {
u32 nwctrl; /* Network Control reg */
@ -270,7 +275,8 @@ static int zynq_gem_setup_mac(struct eth_device *dev)
static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
{
u32 i, rclk, clk = 0;
u32 i;
unsigned long clk_rate = 0;
struct phy_device *phydev;
const u32 stat_size = (sizeof(struct zynq_gem_regs) -
offsetof(struct zynq_gem_regs, stat)) / 4;
@ -348,26 +354,22 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
case SPEED_1000:
writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
&regs->nwcfg);
rclk = (0 << 4) | (1 << 0);
clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
clk_rate = ZYNQ_GEM_FREQUENCY_1000;
break;
case SPEED_100:
clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
rclk = 1 << 0;
clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
clk_rate = ZYNQ_GEM_FREQUENCY_100;
break;
case SPEED_10:
rclk = 1 << 0;
/* FIXME untested */
clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
clk_rate = ZYNQ_GEM_FREQUENCY_10;
break;
}
/* Change the rclk and clk only not using EMIO interface */
if (!priv->emio)
zynq_slcr_gem_clk_setup(dev->iobase !=
ZYNQ_GEM_BASEADDR0, rclk, clk);
ZYNQ_GEM_BASEADDR0, clk_rate);
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);

35
drivers/serial/serial_zynq.c
View File

@ -10,6 +10,8 @@
#include <asm/io.h>
#include <linux/compiler.h>
#include <serial.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
@ -33,28 +35,24 @@ struct uart_zynq {
};
static struct uart_zynq *uart_zynq_ports[2] = {
#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
[0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0,
#endif
#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
[1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1,
#endif
[0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0,
[1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
};
#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0)
# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
#endif
#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1)
# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE
#endif
struct uart_zynq_params {
u32 baudrate;
u32 clock;
};
static struct uart_zynq_params uart_zynq_ports_param[2] = {
#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0)
[0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
[0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0,
#endif
#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1)
[1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
[1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1,
#endif
};
/* Set up the baud rate in gd struct */
@ -64,7 +62,7 @@ static void uart_zynq_serial_setbrg(const int port)
unsigned int calc_bauderror, bdiv, bgen;
unsigned long calc_baud = 0;
unsigned long baud = uart_zynq_ports_param[port].baudrate;
unsigned long clock = uart_zynq_ports_param[port].clock;
unsigned long clock = get_uart_clk(port);
struct uart_zynq *regs = uart_zynq_ports[port];
/* master clock
@ -186,20 +184,19 @@ struct serial_device uart_zynq_serial1_device =
__weak struct serial_device *default_serial_console(void)
{
#if defined(CONFIG_ZYNQ_SERIAL_UART0)
if (uart_zynq_ports[0])
return &uart_zynq_serial0_device;
#endif
#if defined(CONFIG_ZYNQ_SERIAL_UART1)
if (uart_zynq_ports[1])
return &uart_zynq_serial1_device;
#endif
return NULL;
}
void zynq_serial_initalize(void)
{
#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
serial_register(&uart_zynq_serial0_device);
#endif
#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
serial_register(&uart_zynq_serial1_device);
#endif
}

16
include/common.h
View File

@ -964,6 +964,22 @@ static inline phys_addr_t map_to_sysmem(const void *ptr)
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
/*
* Divide positive or negative dividend by positive divisor and round
* to closest integer. Result is undefined for negative divisors and
* for negative dividends if the divisor variable type is unsigned.
*/
#define DIV_ROUND_CLOSEST(x, divisor)( \
{ \
typeof(x) __x = x; \
typeof(divisor) __d = divisor; \
(((typeof(x))-1) > 0 || \
((typeof(divisor))-1) > 0 || (__x) > 0) ? \
(((__x) + ((__d) / 2)) / (__d)) : \
(((__x) - ((__d) / 2)) / (__d)); \
} \
)
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))

102
include/configs/zynq-common.h
View File

@ -35,27 +35,12 @@
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/* Zynq Serial driver */
#ifdef CONFIG_ZYNQ_SERIAL_UART0
# define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000
# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000
#endif
#ifdef CONFIG_ZYNQ_SERIAL_UART1
# define CONFIG_ZYNQ_SERIAL_BASEADDR1 0xE0001000
# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE
# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000
#endif
#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1)
# define CONFIG_ZYNQ_SERIAL
#endif
/* DCC driver */
#if defined(CONFIG_ZYNQ_DCC)
# define CONFIG_ARM_DCC
# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
#else
# define CONFIG_ZYNQ_SERIAL
#endif
/* Ethernet driver */
@ -178,6 +163,8 @@
#define CONFIG_AUTO_COMPLETE
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_LONGHELP
#define CONFIG_CLOCKS
#define CONFIG_CMD_CLK
#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
@ -221,6 +208,9 @@
#define CONFIG_FIT_SIGNATURE
#define CONFIG_RSA
/* Extend size of kernel image for uncompression */
#define CONFIG_SYS_BOOTM_LEN (20 * 1024 * 1024)
/* Boot FreeBSD/vxWorks from an ELF image */
#if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
# define CONFIG_API
@ -236,5 +226,83 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_TFTPPUT
/* SPL part */
#define CONFIG_SPL
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot-spl.lds"
/* Disable dcache for SPL just for sure */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_DCACHE_OFF
#undef CONFIG_FPGA
#endif
/* MMC support */
#ifdef CONFIG_ZYNQ_SDHCI0
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
/* Address in RAM where the parameters must be copied by SPL. */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000
#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "system.dtb"
#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
/* Not using MMC raw mode - just for compilation purpose */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0
/* qspi mode is working fine */
#ifdef CONFIG_ZYNQ_QSPI
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
#define CONFIG_SPL_SPI_CS 0
#endif
/* for booting directly linux */
#define CONFIG_SPL_OS_BOOT
/* SP location before relocation, must use scratch RAM */
#define CONFIG_SPL_TEXT_BASE 0x0
/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
#define CONFIG_SPL_MAX_SIZE 0x30000
/* The highest 64k OCM address */
#define OCM_HIGH_ADDR 0xffff0000
/* Just define any reasonable size */
#define CONFIG_SPL_STACK_SIZE 0x1000
/* SPL stack position - and stack goes down */
#define CONFIG_SPL_STACK (OCM_HIGH_ADDR + CONFIG_SPL_STACK_SIZE)
/* On the top of OCM space */
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_STACK + \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x1000
/* BSS setup */
#define CONFIG_SPL_BSS_START_ADDR 0x100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#endif /* __CONFIG_ZYNQ_COMMON_H */

2
include/configs/zynq_zc70x.h
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@ -2,7 +2,7 @@
* (C) Copyright 2013 Xilinx, Inc.
*
* Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards
* See zynq_common.h for Zynq common configs
* See zynq-common.h for Zynq common configs
*
* SPDX-License-Identifier: GPL-2.0+
*/

2
include/configs/zynq_zed.h
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@ -2,7 +2,7 @@
* (C) Copyright 2013 Xilinx, Inc.
*
* Configuration for Zynq Evaluation and Development Board - ZedBoard
* See zynq_common.h for Zynq common configs
* See zynq-common.h for Zynq common configs
*
* SPDX-License-Identifier: GPL-2.0+
*/