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imx: apbh_dma: Update APBH-DMA for MX7D
Update APBH-DMA driver and head files to support i.MX7D Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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@ -59,7 +59,7 @@ enum {
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MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
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MXS_MAX_DMA_CHANNELS,
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};
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#elif defined(CONFIG_MX6)
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#elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
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enum {
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MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
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@ -96,7 +96,7 @@ struct mxs_apbh_regs {
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mxs_reg_32(hw_apbh_version)
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};
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#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
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#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
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struct mxs_apbh_regs {
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mxs_reg_32(hw_apbh_ctrl0)
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mxs_reg_32(hw_apbh_ctrl1)
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@ -275,7 +275,7 @@ struct mxs_apbh_regs {
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#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
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#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
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#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
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#elif defined(CONFIG_MX6)
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#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
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#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
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#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
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#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
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@ -391,7 +391,7 @@ struct mxs_apbh_regs {
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#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
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#endif
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#if defined(CONFIG_MX6)
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
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#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
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#endif
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@ -215,7 +215,7 @@ static int mxs_dma_reset(int channel)
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#if defined(CONFIG_MX23)
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uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
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uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
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#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
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#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
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uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
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uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
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#endif
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