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rockchip: rk3368: move sgrf init to spl as arch_cpu_init()

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The SoC related init will move to SPL and keep TPL clean,
so that we can reuse the common TPL board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang 2019-07-09 22:00:30 +08:00
parent 0845a0ee66
commit 1f6b599b6d
3 changed files with 80 additions and 70 deletions
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6
arch/arm/mach-rockchip/rk3368-board-spl.c
View File

@ -11,6 +11,11 @@
#include <asm/io.h>
#include <asm/arch-rockchip/periph.h>
__weak int arch_cpu_init(void)
{
return 0;
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
@ -22,6 +27,7 @@ void board_init_f(ulong dummy)
hang();
}
arch_cpu_init();
preloader_console_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);

69
arch/arm/mach-rockchip/rk3368-board-tpl.c
View File

@ -8,74 +8,8 @@
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3368.h>
#include <asm/arch-rockchip/hardware.h>
/*
* The SPL (and also the full U-Boot stage on the RK3368) will run in
* secure mode (i.e. EL3) and an ATF will eventually be booted before
* starting up the operating system... so we can initialize the SGRF
* here and rely on the ATF installing the final (secure) policy
* later.
*/
static inline uintptr_t sgrf_soc_con_addr(unsigned no)
{
const uintptr_t SGRF_BASE =
(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
return SGRF_BASE + sizeof(u32) * no;
}
static inline uintptr_t sgrf_busdmac_addr(unsigned no)
{
const uintptr_t SGRF_BASE =
(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
}
static void sgrf_init(void)
{
struct rk3368_cru * const cru =
(struct rk3368_cru * const)rockchip_get_cru();
const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
/* Set all configurable IP to 'non secure'-mode */
rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
/*
* From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
* Original comment: "ddr space set no secure mode"
*/
rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
/* Set 'secure dma' to 'non secure'-mode */
rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
dsb(); /* barrier */
rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
dsb(); /* barrier */
udelay(10);
rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
}
void board_init_f(ulong dummy)
{
@ -101,9 +35,6 @@ void board_init_f(ulong dummy)
hang();
}
/* Reset security, so we can use DMA in the MMC drivers */
sgrf_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);

75
arch/arm/mach-rockchip/rk3368/rk3368.c
View File

@ -5,12 +5,13 @@
*/
#include <common.h>
#include <syscon.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3368.h>
#include <asm/arch-rockchip/grf_rk3368.h>
#include <syscon.h>
#include <asm/arch-rockchip/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
@ -97,6 +98,78 @@ int arch_early_init_r(void)
}
#endif
#ifdef CONFIG_SPL_BUILD
/*
* The SPL (and also the full U-Boot stage on the RK3368) will run in
* secure mode (i.e. EL3) and an ATF will eventually be booted before
* starting up the operating system... so we can initialize the SGRF
* here and rely on the ATF installing the final (secure) policy
* later.
*/
static inline uintptr_t sgrf_soc_con_addr(unsigned int no)
{
const uintptr_t SGRF_BASE =
(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
return SGRF_BASE + sizeof(u32) * no;
}
static inline uintptr_t sgrf_busdmac_addr(unsigned int no)
{
const uintptr_t SGRF_BASE =
(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
}
static void sgrf_init(void)
{
struct rk3368_cru * const cru =
(struct rk3368_cru * const)rockchip_get_cru();
const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
/* Set all configurable IP to 'non secure'-mode */
rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
/*
* From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
* Original comment: "ddr space set no secure mode"
*/
rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
/* Set 'secure dma' to 'non secure'-mode */
rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
dsb(); /* barrier */
rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
dsb(); /* barrier */
udelay(10);
rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
}
int arch_cpu_init(void)
{
/* Reset security, so we can use DMA in the MMC drivers */
sgrf_init();
return 0;
}
#endif
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{