mirror of
https://github.com/u-boot/u-boot.git
synced 2025-01-19 09:13:31 +08:00
Merge branch 'master' of git://git.denx.de/u-boot-arm into master
Conflicts: arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Stefano Babic
commit
1cad23c5f4
4
.gitignore
vendored
4
.gitignore
vendored
@ -51,6 +51,10 @@
|
||||
/spl/*
|
||||
/tpl/
|
||||
|
||||
#
|
||||
# Generated include files
|
||||
#
|
||||
/include/config/
|
||||
/include/generated/
|
||||
/include/spl-autoconf.mk
|
||||
/include/tpl-autoconf.mk
|
||||
|
||||
104
Makefile
104
Makefile
@ -8,7 +8,7 @@
|
||||
VERSION = 2014
|
||||
PATCHLEVEL = 04
|
||||
SUBLEVEL =
|
||||
EXTRAVERSION = -rc1
|
||||
EXTRAVERSION = -rc2
|
||||
NAME =
|
||||
|
||||
# *DOCUMENTATION*
|
||||
@ -165,14 +165,7 @@ VPATH := $(srctree)$(if $(KBUILD_EXTMOD),:$(KBUILD_EXTMOD))
|
||||
|
||||
export srctree objtree VPATH
|
||||
|
||||
OBJTREE := $(objtree)
|
||||
SPLTREE := $(OBJTREE)/spl
|
||||
TPLTREE := $(OBJTREE)/tpl
|
||||
SRCTREE := $(srctree)
|
||||
TOPDIR := $(SRCTREE)
|
||||
export TOPDIR SRCTREE OBJTREE SPLTREE TPLTREE
|
||||
|
||||
MKCONFIG := $(SRCTREE)/mkconfig
|
||||
MKCONFIG := $(srctree)/mkconfig
|
||||
export MKCONFIG
|
||||
|
||||
# Make sure CDPATH settings don't interfere
|
||||
@ -358,13 +351,13 @@ UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null)
|
||||
UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION)
|
||||
|
||||
export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
|
||||
export ARCH CPU BOARD VENDOR SOC
|
||||
export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
|
||||
export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
|
||||
export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
|
||||
export MAKE AWK
|
||||
export DTC CHECK CHECKFLAGS
|
||||
|
||||
export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE
|
||||
export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
|
||||
export KBUILD_CFLAGS KBUILD_AFLAGS
|
||||
|
||||
# When compiling out-of-tree modules, put MODVERDIR in the module
|
||||
@ -489,10 +482,8 @@ endif
|
||||
# that (or fail if absent). Otherwise, search for a linker script in a
|
||||
# standard location.
|
||||
|
||||
LDSCRIPT_MAKEFILE_DIR = $(dir $(LDSCRIPT))
|
||||
|
||||
ifndef LDSCRIPT
|
||||
#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
|
||||
#LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds.debug
|
||||
ifdef CONFIG_SYS_LDSCRIPT
|
||||
# need to strip off double quotes
|
||||
LDSCRIPT := $(srctree)/$(CONFIG_SYS_LDSCRIPT:"%"=%)
|
||||
@ -502,21 +493,19 @@ endif
|
||||
# If there is no specified link script, we look in a number of places for it
|
||||
ifndef LDSCRIPT
|
||||
ifeq ($(CONFIG_NAND_U_BOOT),y)
|
||||
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
|
||||
LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-nand.lds
|
||||
ifeq ($(wildcard $(LDSCRIPT)),)
|
||||
LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
|
||||
LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-nand.lds
|
||||
endif
|
||||
endif
|
||||
ifeq ($(wildcard $(LDSCRIPT)),)
|
||||
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
|
||||
LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds
|
||||
endif
|
||||
ifeq ($(wildcard $(LDSCRIPT)),)
|
||||
LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds
|
||||
LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot.lds
|
||||
endif
|
||||
ifeq ($(wildcard $(LDSCRIPT)),)
|
||||
LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot.lds
|
||||
# We don't expect a Makefile here
|
||||
LDSCRIPT_MAKEFILE_DIR =
|
||||
LDSCRIPT := $(srctree)/arch/$(ARCH)/cpu/u-boot.lds
|
||||
endif
|
||||
endif
|
||||
|
||||
@ -560,18 +549,17 @@ export CONFIG_SYS_TEXT_BASE
|
||||
|
||||
# Use UBOOTINCLUDE when you must reference the include/ directory.
|
||||
# Needed to be compatible with the O= option
|
||||
UBOOTINCLUDE :=
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
UBOOTINCLUDE += -I$(OBJTREE)/include
|
||||
endif
|
||||
UBOOTINCLUDE += -I$(srctree)/include \
|
||||
UBOOTINCLUDE := \
|
||||
-Iinclude \
|
||||
$(if $(KBUILD_SRC), -I$(srctree)/include) \
|
||||
-I$(srctree)/arch/$(ARCH)/include
|
||||
|
||||
NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
|
||||
CHECKFLAGS += $(NOSTDINC_FLAGS)
|
||||
|
||||
# FIX ME
|
||||
cpp_flags := $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS)
|
||||
cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \
|
||||
$(NOSTDINC_FLAGS)
|
||||
c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
|
||||
|
||||
#########################################################################
|
||||
@ -595,6 +583,7 @@ libs-y += fs/
|
||||
libs-y += net/
|
||||
libs-y += disk/
|
||||
libs-y += drivers/
|
||||
libs-$(CONFIG_DM) += drivers/core/
|
||||
libs-y += drivers/dma/
|
||||
libs-y += drivers/gpio/
|
||||
libs-y += drivers/i2c/
|
||||
@ -629,6 +618,8 @@ libs-y += lib/libfdt/
|
||||
libs-$(CONFIG_API) += api/
|
||||
libs-$(CONFIG_HAS_POST) += post/
|
||||
libs-y += test/
|
||||
libs-y += test/dm/
|
||||
libs-$(CONFIG_DM_DEMO) += drivers/demo/
|
||||
|
||||
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
|
||||
libs-y += arch/$(ARCH)/imx-common/
|
||||
@ -637,7 +628,7 @@ endif
|
||||
libs-$(CONFIG_ARM) += arch/arm/cpu/
|
||||
libs-$(CONFIG_PPC) += arch/powerpc/cpu/
|
||||
|
||||
libs-y += board/$(BOARDDIR)/
|
||||
libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
|
||||
|
||||
libs-y := $(sort $(libs-y))
|
||||
|
||||
@ -652,11 +643,11 @@ u-boot-main := $(libs-y)
|
||||
|
||||
|
||||
# Add GCC lib
|
||||
ifdef USE_PRIVATE_LIBGCC
|
||||
ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
|
||||
PLATFORM_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/lib.a
|
||||
ifdef CONFIG_USE_PRIVATE_LIBGCC
|
||||
ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
|
||||
PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
|
||||
else
|
||||
PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc
|
||||
PLATFORM_LIBGCC = -L $(CONFIG_USE_PRIVATE_LIBGCC) -lgcc
|
||||
endif
|
||||
else
|
||||
PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc
|
||||
@ -668,7 +659,7 @@ export PLATFORM_LIBS
|
||||
# Pass the version down so we can handle backwards compatibility
|
||||
# on the fly.
|
||||
LDPPFLAGS += \
|
||||
-include $(TOPDIR)/include/u-boot/u-boot.lds.h \
|
||||
-include $(srctree)/include/u-boot/u-boot.lds.h \
|
||||
-DCPUDIR=$(CPUDIR) \
|
||||
$(shell $(LD) --version | \
|
||||
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
|
||||
@ -712,6 +703,7 @@ ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
|
||||
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
|
||||
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
|
||||
ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin
|
||||
ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb
|
||||
ifneq ($(CONFIG_SPL_TARGET),)
|
||||
ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
|
||||
endif
|
||||
@ -804,11 +796,11 @@ MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
|
||||
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
|
||||
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
|
||||
|
||||
MKIMAGEFLAGS_u-boot.kwb = -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
|
||||
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
|
||||
MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
|
||||
-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
|
||||
|
||||
MKIMAGEFLAGS_u-boot.pbl = -n $(CONFIG_SYS_FSL_PBL_RCW) \
|
||||
-R $(CONFIG_SYS_FSL_PBL_PBI) -T pblimage
|
||||
MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
|
||||
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
|
||||
|
||||
u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
|
||||
$(call if_changed,mkimage)
|
||||
@ -857,7 +849,7 @@ u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE
|
||||
$(call if_changed,pad_cat)
|
||||
|
||||
u-boot.sb: u-boot.bin spl/u-boot-spl.bin
|
||||
$(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs $(objtree)/u-boot.sb
|
||||
$(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot.sb
|
||||
|
||||
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
|
||||
# Both images are created using mkimage (crc etc), so that the ROM
|
||||
@ -1021,7 +1013,7 @@ define filechk_timestamp.h
|
||||
LC_ALL=C date +'#define U_BOOT_TIME "%T"')
|
||||
endef
|
||||
|
||||
$(version_h): $(srctree)/Makefile FORCE
|
||||
$(version_h): include/config/uboot.release FORCE
|
||||
$(call filechk,version.h)
|
||||
|
||||
$(timestamp_h): $(srctree)/Makefile FORCE
|
||||
@ -1067,6 +1059,13 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE
|
||||
PHONY += nand_spl
|
||||
nand_spl: prepare
|
||||
$(Q)$(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all
|
||||
@echo >&2
|
||||
@echo >&2 "==================== WARNING ====================="
|
||||
@echo >&2 "nand_spl will not be included in v2014.07 release."
|
||||
@echo >&2 "Please switch over to SPL."
|
||||
@echo >&2 "Otherwise, this board will be removed."
|
||||
@echo >&2 "=================================================="
|
||||
@echo >&2
|
||||
|
||||
nand_spl/u-boot-spl-16k.bin: nand_spl
|
||||
@:
|
||||
@ -1106,23 +1105,6 @@ SYSTEM_MAP = \
|
||||
System.map: u-boot
|
||||
@$(call SYSTEM_MAP,$<) > $@
|
||||
|
||||
checkthumb:
|
||||
@if test $(call cc-version) -lt 0404; then \
|
||||
echo -n '*** Your GCC does not produce working '; \
|
||||
echo 'binaries in THUMB mode.'; \
|
||||
echo '*** Your board is configured for THUMB mode.'; \
|
||||
false; \
|
||||
fi
|
||||
|
||||
# GCC 3.x is reported to have problems generating the type of relocation
|
||||
# that U-Boot wants.
|
||||
# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
|
||||
checkgcc4:
|
||||
@if test $(call cc-version) -lt 0400; then \
|
||||
echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
|
||||
false; \
|
||||
fi
|
||||
|
||||
checkdtc:
|
||||
@if test $(call dtc-version) -lt 0104; then \
|
||||
echo '*** Your dtc is too old, please upgrade to dtc 1.4 or newer'; \
|
||||
@ -1145,9 +1127,12 @@ checkarmreloc: u-boot
|
||||
env: scripts_basic
|
||||
$(Q)$(MAKE) $(build)=tools/$@
|
||||
|
||||
tools-all: HOST_TOOLS_ALL=y
|
||||
tools-all: export HOST_TOOLS_ALL=y
|
||||
tools-all: env tools ;
|
||||
|
||||
cross_tools: export CROSS_BUILD_TOOLS=y
|
||||
cross_tools: tools ;
|
||||
|
||||
.PHONY : CHANGELOG
|
||||
CHANGELOG:
|
||||
git log --no-merges U-Boot-1_1_5.. | \
|
||||
@ -1167,7 +1152,6 @@ include/license.h: tools/bin2header COPYING
|
||||
# Directories & files removed with 'make clean'
|
||||
CLEAN_DIRS += $(MODVERDIR)
|
||||
CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \
|
||||
board/*/config.tmp board/*/*/config.tmp \
|
||||
include/autoconf.mk* include/spl-autoconf.mk \
|
||||
include/tpl-autoconf.mk
|
||||
|
||||
@ -1244,12 +1228,12 @@ distclean: mrproper
|
||||
@find $(srctree) $(RCS_FIND_IGNORE) \
|
||||
\( -name '*.orig' -o -name '*.rej' -o -name '*~' \
|
||||
-o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \
|
||||
-o -name '.*.rej' \
|
||||
-o -name '.*.rej' -o -name '*.pyc' \
|
||||
-o -name '*%' -o -name '.*.cmd' -o -name 'core' \) \
|
||||
-type f -print | xargs rm -f
|
||||
|
||||
backup:
|
||||
F=`basename $(TOPDIR)` ; cd .. ; \
|
||||
F=`basename $(srctree)` ; cd .. ; \
|
||||
gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F
|
||||
|
||||
help:
|
||||
|
||||
3
README
3
README
@ -3470,6 +3470,9 @@ typically in board_init_f() and board_init_r().
|
||||
Configuration Settings:
|
||||
-----------------------
|
||||
|
||||
- CONFIG_SYS_SUPPORT_64BIT_DATA: Defined automatically if compiled as 64-bit.
|
||||
Optionally it can be defined to support 64-bit memory commands.
|
||||
|
||||
- CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
|
||||
undefine this when you're short of memory.
|
||||
|
||||
|
||||
@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si)
|
||||
si->clk_bus = gd->bus_clk;
|
||||
si->clk_cpu = gd->cpu_clk;
|
||||
|
||||
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || \
|
||||
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || \
|
||||
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
|
||||
#define bi_bar bi_immr_base
|
||||
#elif defined(CONFIG_MPC5xxx)
|
||||
|
||||
@ -9,17 +9,19 @@ CONFIG_SYS_LITTLE_ENDIAN = 1
|
||||
endif
|
||||
|
||||
ifdef CONFIG_SYS_LITTLE_ENDIAN
|
||||
CROSS_COMPILE ?= arc-buildroot-linux-uclibc-
|
||||
ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc-
|
||||
endif
|
||||
|
||||
ifdef CONFIG_SYS_BIG_ENDIAN
|
||||
CROSS_COMPILE ?= arceb-buildroot-linux-uclibc-
|
||||
ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc-
|
||||
PLATFORM_LDFLAGS += -EB
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
CROSS_COMPILE := $(ARC_CROSS_COMPILE)
|
||||
endif
|
||||
|
||||
LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
|
||||
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2
|
||||
|
||||
# Needed for relocation
|
||||
LDFLAGS_FINAL += -pie
|
||||
|
||||
@ -5,7 +5,9 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
CROSS_COMPILE ?= arm-linux-
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
CROSS_COMPILE := arm-linux-
|
||||
endif
|
||||
|
||||
ifndef CONFIG_STANDALONE_LOAD_ADDR
|
||||
ifneq ($(CONFIG_OMAP_COMMON),)
|
||||
@ -39,7 +41,17 @@ endif
|
||||
|
||||
# Only test once
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ALL-$(CONFIG_SYS_THUMB_BUILD) += checkthumb
|
||||
ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
|
||||
archprepare: checkthumb
|
||||
|
||||
checkthumb:
|
||||
@if test "$(call cc-version)" -lt "0404"; then \
|
||||
echo -n '*** Your GCC does not produce working '; \
|
||||
echo 'binaries in THUMB mode.'; \
|
||||
echo '*** Your board is configured for THUMB mode.'; \
|
||||
false; \
|
||||
fi
|
||||
endif
|
||||
endif
|
||||
|
||||
# Try if EABI is supported, else fall back to old API,
|
||||
@ -67,13 +79,8 @@ ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
|
||||
# times. Also, the prefix needs to be different based on whether
|
||||
# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry
|
||||
# before adding the correct one.
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
PLATFORM_LIBS := $(SPLTREE)/arch/arm/lib/eabi_compat.o \
|
||||
$(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
|
||||
else
|
||||
PLATFORM_LIBS := $(OBJTREE)/arch/arm/lib/eabi_compat.o \
|
||||
$(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
|
||||
endif
|
||||
PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \
|
||||
$(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
|
||||
endif
|
||||
|
||||
# needed for relocation
|
||||
|
||||
@ -378,8 +378,7 @@ void clock_enable_coresight(int enable)
|
||||
void halt_avp(void)
|
||||
{
|
||||
for (;;) {
|
||||
writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
|
||||
| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
|
||||
FLOW_CTLR_HALT_COP_EVENTS);
|
||||
writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
|
||||
FLOW_CTLR_HALT_COP_EVENTS);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,19 +0,0 @@
|
||||
#
|
||||
# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms and conditions of the GNU General Public License,
|
||||
# version 2, as published by the Free Software Foundation.
|
||||
#
|
||||
# This program is distributed in the hope it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
# more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
USE_PRIVATE_LIBGCC = yes
|
||||
@ -1,7 +0,0 @@
|
||||
#
|
||||
# (C) Copyright 2010-2013
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#/
|
||||
USE_PRIVATE_LIBGCC = yes
|
||||
@ -252,8 +252,8 @@ void start_cpu(u32 reset_vector)
|
||||
tegra124_init_clocks();
|
||||
|
||||
/* Set power-gating timer multiplier */
|
||||
clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
|
||||
setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
|
||||
writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
|
||||
&pmc->pmc_pwrgate_timer_mult);
|
||||
|
||||
enable_cpu_power_rail();
|
||||
enable_cpu_clocks();
|
||||
|
||||
@ -1,10 +0,0 @@
|
||||
#
|
||||
# (C) Copyright 2010,2011
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
USE_PRIVATE_LIBGCC = yes
|
||||
@ -1,19 +0,0 @@
|
||||
#
|
||||
# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms and conditions of the GNU General Public License,
|
||||
# version 2, as published by the Free Software Foundation.
|
||||
#
|
||||
# This program is distributed in the hope it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
# more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
USE_PRIVATE_LIBGCC = yes
|
||||
@ -143,6 +143,31 @@ void at91_spi1_hw_init(unsigned long cs_mask)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_GENERIC_ATMEL_MCI)
|
||||
void at91_mci_hw_init(void)
|
||||
{
|
||||
/* Enable mci clock */
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
|
||||
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */
|
||||
|
||||
#if defined(CONFIG_ATMEL_MCI_PORTB)
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */
|
||||
#else
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */
|
||||
at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACB
|
||||
void at91_macb_hw_init(void)
|
||||
{
|
||||
|
||||
@ -14,11 +14,12 @@ obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
|
||||
endif
|
||||
|
||||
# Specify the target for use in elftosb call
|
||||
MKIMAGE_TARGET-$(CONFIG_MX23) = mx23
|
||||
MKIMAGE_TARGET-$(CONFIG_MX28) = mx28
|
||||
MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg
|
||||
MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg
|
||||
|
||||
$(OBJTREE)/mxsimage.cfg: $(SRCTREE)/$(CPUDIR)/$(SOC)/mxsimage.$(MKIMAGE_TARGET-y).cfg
|
||||
sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@
|
||||
quiet_cmd_mkimage_mxs = UIMAGE $@
|
||||
cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \
|
||||
$(if $(KBUILD_VERBOSE:1=), >/dev/null)
|
||||
|
||||
$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/mxsimage.cfg
|
||||
$(OBJTREE)/tools/mkimage -n $(OBJTREE)/mxsimage.cfg -T mxsimage $@
|
||||
u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE
|
||||
$(call if_changed,mkimage_mxs)
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
SECTION 0x0 BOOTABLE
|
||||
TAG LAST
|
||||
LOAD 0x1000 OBJTREE/spl/u-boot-spl.bin
|
||||
LOAD 0x1000 spl/u-boot-spl.bin
|
||||
CALL 0x1000 0x0
|
||||
LOAD 0x40002000 OBJTREE/u-boot.bin
|
||||
LOAD 0x40002000 u-boot.bin
|
||||
CALL 0x40002000 0x0
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
SECTION 0x0 BOOTABLE
|
||||
TAG LAST
|
||||
LOAD 0x1000 OBJTREE/spl/u-boot-spl.bin
|
||||
LOAD 0x1000 spl/u-boot-spl.bin
|
||||
LOAD IVT 0x8000 0x1000
|
||||
CALL HAB 0x8000 0x0
|
||||
LOAD 0x40002000 OBJTREE/u-boot.bin
|
||||
LOAD 0x40002000 u-boot.bin
|
||||
LOAD IVT 0x8000 0x40002000
|
||||
CALL HAB 0x8000 0x0
|
||||
|
||||
@ -4,8 +4,8 @@ options {
|
||||
}
|
||||
|
||||
sources {
|
||||
u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
|
||||
u_boot="OBJTREE/u-boot.bin";
|
||||
u_boot_spl="spl/u-boot-spl.bin";
|
||||
u_boot="u-boot.bin";
|
||||
}
|
||||
|
||||
section (0) {
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
sources {
|
||||
u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
|
||||
u_boot="OBJTREE/u-boot.bin";
|
||||
u_boot_spl="spl/u-boot-spl.bin";
|
||||
u_boot="u-boot.bin";
|
||||
}
|
||||
|
||||
section (0) {
|
||||
|
||||
@ -202,6 +202,7 @@ static void watchdog_disable(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
|
||||
void s_init(void)
|
||||
{
|
||||
/*
|
||||
@ -220,22 +221,19 @@ void s_init(void)
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
save_omap_boot_params();
|
||||
#endif
|
||||
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
|
||||
watchdog_disable();
|
||||
timer_init();
|
||||
set_uart_mux_conf();
|
||||
setup_clocks_for_console();
|
||||
uart_soft_reset();
|
||||
#endif
|
||||
#ifdef CONFIG_NOR_BOOT
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
serial_init();
|
||||
gd->have_console = 1;
|
||||
#else
|
||||
#elif defined(CONFIG_SPL_BUILD)
|
||||
gd = &gdata;
|
||||
preloader_console_init();
|
||||
#endif
|
||||
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
|
||||
prcm_init();
|
||||
set_mux_conf_regs();
|
||||
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
|
||||
@ -243,8 +241,8 @@ void s_init(void)
|
||||
rtc32k_enable();
|
||||
#endif
|
||||
sdram_init();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
void enable_caches(void)
|
||||
|
||||
@ -39,6 +39,9 @@ static void exynos5_uart_config(int peripheral)
|
||||
start = 4;
|
||||
count = 2;
|
||||
break;
|
||||
default:
|
||||
debug("%s: invalid peripheral %d", __func__, peripheral);
|
||||
return;
|
||||
}
|
||||
for (i = start; i < start + count; i++) {
|
||||
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
|
||||
@ -74,6 +77,9 @@ static void exynos5420_uart_config(int peripheral)
|
||||
start = 4;
|
||||
count = 2;
|
||||
break;
|
||||
default:
|
||||
debug("%s: invalid peripheral %d", __func__, peripheral);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = start; i < start + count; i++) {
|
||||
@ -110,6 +116,9 @@ static int exynos5_mmc_config(int peripheral, int flags)
|
||||
bank = &gpio1->c4;
|
||||
bank_ext = NULL;
|
||||
break;
|
||||
default:
|
||||
debug("%s: invalid peripheral %d", __func__, peripheral);
|
||||
return -1;
|
||||
}
|
||||
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
|
||||
debug("SDMMC device %d does not support 8bit mode",
|
||||
@ -683,6 +692,9 @@ static void exynos4_uart_config(int peripheral)
|
||||
start = 4;
|
||||
count = 2;
|
||||
break;
|
||||
default:
|
||||
debug("%s: invalid peripheral %d", __func__, peripheral);
|
||||
return;
|
||||
}
|
||||
for (i = start; i < start + count; i++) {
|
||||
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
|
||||
@ -741,6 +753,21 @@ int exynos_pinmux_config(int peripheral, int flags)
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
|
||||
{
|
||||
int err;
|
||||
u32 cell[3];
|
||||
|
||||
err = fdtdec_get_int_array(blob, node, "interrupts", cell,
|
||||
ARRAY_SIZE(cell));
|
||||
if (err) {
|
||||
debug(" invalid peripheral id\n");
|
||||
return PERIPH_ID_NONE;
|
||||
}
|
||||
|
||||
return cell[1];
|
||||
}
|
||||
|
||||
static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
|
||||
{
|
||||
int err;
|
||||
@ -758,6 +785,8 @@ int pinmux_decode_periph_id(const void *blob, int node)
|
||||
{
|
||||
if (cpu_is_exynos5())
|
||||
return exynos5_pinmux_decode_periph_id(blob, node);
|
||||
else if (cpu_is_exynos4())
|
||||
return exynos4_pinmux_decode_periph_id(blob, node);
|
||||
else
|
||||
return PERIPH_ID_NONE;
|
||||
}
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
void enable_caches(void)
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
#include <common.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/emif.h>
|
||||
#include <asm/omap_common.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
@ -15,7 +15,7 @@
|
||||
#include <asm/armv7.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/emif.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/omap_common.h>
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/utils.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/emif.h>
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
@ -52,6 +52,10 @@ u32 spl_boot_device(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_USE_MMC
|
||||
return BOOT_DEVICE_MMC1;
|
||||
#elif CONFIG_SYS_USE_NANDFLASH
|
||||
return BOOT_DEVICE_NAND;
|
||||
#elif CONFIG_SYS_USE_SERIALFLASH
|
||||
return BOOT_DEVICE_SPI;
|
||||
#endif
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
|
||||
exynos4210-universal_c210.dtb \
|
||||
exynos4210-trats.dtb \
|
||||
exynos4412-trats2.dtb
|
||||
|
||||
dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
|
||||
exynos5250-snow.dtb \
|
||||
exynos5250-smdk5250.dtb \
|
||||
|
||||
138
arch/arm/dts/exynos4.dtsi
Normal file
138
arch/arm/dts/exynos4.dtsi
Normal file
@ -0,0 +1,138 @@
|
||||
/*
|
||||
* Samsung's Exynos4 SoC common device tree source
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
serial@13800000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13800000 0x3c>;
|
||||
id = <0>;
|
||||
};
|
||||
|
||||
serial@13810000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13810000 0x3c>;
|
||||
id = <1>;
|
||||
};
|
||||
|
||||
serial@13820000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x3c>;
|
||||
id = <2>;
|
||||
};
|
||||
|
||||
serial@13830000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13830000 0x3c>;
|
||||
id = <3>;
|
||||
};
|
||||
|
||||
serial@13840000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13840000 0x3c>;
|
||||
id = <4>;
|
||||
};
|
||||
|
||||
i2c@13860000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
interrupts = <0 0 0>;
|
||||
};
|
||||
|
||||
i2c@13870000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
interrupts = <1 1 0>;
|
||||
};
|
||||
|
||||
i2c@13880000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
interrupts = <2 2 0>;
|
||||
};
|
||||
|
||||
i2c@13890000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
interrupts = <3 3 0>;
|
||||
};
|
||||
|
||||
i2c@138a0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
interrupts = <4 4 0>;
|
||||
};
|
||||
|
||||
i2c@138b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
interrupts = <5 5 0>;
|
||||
};
|
||||
|
||||
i2c@138c0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
interrupts = <6 6 0>;
|
||||
};
|
||||
|
||||
i2c@138d0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
interrupts = <7 7 0>;
|
||||
};
|
||||
|
||||
sdhci@12510000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos-mmc";
|
||||
reg = <0x12510000 0x1000>;
|
||||
interrupts = <0 75 0>;
|
||||
};
|
||||
|
||||
sdhci@12520000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos-mmc";
|
||||
reg = <0x12520000 0x1000>;
|
||||
interrupts = <0 76 0>;
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos-mmc";
|
||||
reg = <0x12530000 0x1000>;
|
||||
interrupts = <0 77 0>;
|
||||
};
|
||||
|
||||
sdhci@12540000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos-mmc";
|
||||
reg = <0x12540000 0x1000>;
|
||||
interrupts = <0 78 0>;
|
||||
};
|
||||
|
||||
gpio: gpio {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
45
arch/arm/dts/exynos4210-origen.dts
Normal file
45
arch/arm/dts/exynos4210-origen.dts
Normal file
@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Samsung's Exynos4210 based Origen board device tree source
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "skeleton.dtsi"
|
||||
/include/ "exynos4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Insignal Origen evaluation board based on Exynos4210";
|
||||
compatible = "insignal,origen", "samsung,exynos4210";
|
||||
|
||||
chosen {
|
||||
bootargs ="";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = "/serial@13800000";
|
||||
console = "/serial@13820000";
|
||||
mmc2 = "sdhci@12530000";
|
||||
};
|
||||
|
||||
sdhci@12510000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@12520000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
samsung,bus-width = <4>;
|
||||
samsung,timing = <1 2 3>;
|
||||
cd-gpios = <&gpio 0x2008002 0>;
|
||||
};
|
||||
|
||||
sdhci@12540000 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
120
arch/arm/dts/exynos4210-trats.dts
Normal file
120
arch/arm/dts/exynos4210-trats.dts
Normal file
@ -0,0 +1,120 @@
|
||||
/*
|
||||
* Samsung's Exynos4210 based Trats board device tree source
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Samsung Trats based on Exynos4210";
|
||||
compatible = "samsung,trats", "samsung,exynos4210";
|
||||
|
||||
config {
|
||||
samsung,dsim-device-name = "s6e8ax0";
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@13860000";
|
||||
i2c1 = "/i2c@13870000";
|
||||
i2c2 = "/i2c@13880000";
|
||||
i2c3 = "/i2c@13890000";
|
||||
i2c4 = "/i2c@138a0000";
|
||||
i2c5 = "/i2c@138b0000";
|
||||
i2c6 = "/i2c@138c0000";
|
||||
i2c7 = "/i2c@138d0000";
|
||||
serial0 = "/serial@13800000";
|
||||
console = "/serial@13820000";
|
||||
mmc0 = "sdhci@12510000";
|
||||
mmc2 = "sdhci@12530000";
|
||||
};
|
||||
|
||||
fimd@11c00000 {
|
||||
compatible = "samsung,exynos-fimd";
|
||||
reg = <0x11c00000 0xa4>;
|
||||
|
||||
samsung,vl-freq = <60>;
|
||||
samsung,vl-col = <720>;
|
||||
samsung,vl-row = <1280>;
|
||||
samsung,vl-width = <720>;
|
||||
samsung,vl-height = <1280>;
|
||||
|
||||
samsung,vl-clkp = <0>;
|
||||
samsung,vl-oep = <0>;
|
||||
samsung,vl-hsp = <1>;
|
||||
samsung,vl-vsp = <1>;
|
||||
samsung,vl-dp = <1>;
|
||||
samsung,vl-bpix = <4>;
|
||||
|
||||
samsung,vl-hspw = <5>;
|
||||
samsung,vl-hbpd = <10>;
|
||||
samsung,vl-hfpd = <10>;
|
||||
samsung,vl-vspw = <2>;
|
||||
samsung,vl-vbpd = <1>;
|
||||
samsung,vl-vfpd = <13>;
|
||||
samsung,vl-cmd-allow-len = <0xf>;
|
||||
|
||||
samsung,winid = <3>;
|
||||
samsung,power-on-delay = <30>;
|
||||
samsung,interface-mode = <1>;
|
||||
samsung,mipi-enabled = <1>;
|
||||
samsung,dp-enabled;
|
||||
samsung,dual-lcd-enabled;
|
||||
|
||||
samsung,logo-on = <1>;
|
||||
samsung,resolution = <0>;
|
||||
samsung,rgb-mode = <0>;
|
||||
};
|
||||
|
||||
mipidsi@11c80000 {
|
||||
compatible = "samsung,exynos-mipi-dsi";
|
||||
reg = <0x11c80000 0x5c>;
|
||||
|
||||
samsung,dsim-config-e-interface = <1>;
|
||||
samsung,dsim-config-e-virtual-ch = <0>;
|
||||
samsung,dsim-config-e-pixel-format = <7>;
|
||||
samsung,dsim-config-e-burst-mode = <1>;
|
||||
samsung,dsim-config-e-no-data-lane = <3>;
|
||||
samsung,dsim-config-e-byte-clk = <0>;
|
||||
samsung,dsim-config-hfp = <1>;
|
||||
|
||||
samsung,dsim-config-p = <3>;
|
||||
samsung,dsim-config-m = <120>;
|
||||
samsung,dsim-config-s = <1>;
|
||||
|
||||
samsung,dsim-config-pll-stable-time = <500>;
|
||||
samsung,dsim-config-esc-clk = <20000000>;
|
||||
samsung,dsim-config-stop-holding-cnt = <0x7ff>;
|
||||
samsung,dsim-config-bta-timeout = <0xff>;
|
||||
samsung,dsim-config-rx-timeout = <0xffff>;
|
||||
|
||||
samsung,dsim-device-id = <0xffffffff>;
|
||||
samsung,dsim-device-bus-id = <0>;
|
||||
|
||||
samsung,dsim-device-reverse-panel = <1>;
|
||||
};
|
||||
|
||||
sdhci@12510000 {
|
||||
samsung,bus-width = <8>;
|
||||
samsung,timing = <1 3 3>;
|
||||
pwr-gpios = <&gpio 0x2008002 0>;
|
||||
};
|
||||
|
||||
sdhci@12520000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
samsung,bus-width = <4>;
|
||||
samsung,timing = <1 2 3>;
|
||||
cd-gpios = <&gpio 0x20c6004 0>;
|
||||
};
|
||||
|
||||
sdhci@12540000 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
83
arch/arm/dts/exynos4210-universal_c210.dts
Normal file
83
arch/arm/dts/exynos4210-universal_c210.dts
Normal file
@ -0,0 +1,83 @@
|
||||
/*
|
||||
* Samsung's Exynos4210 based Universal C210 board device tree source
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Samsung Universal C210 based on Exynos4210 rev0";
|
||||
compatible = "samsung,universal_c210", "samsung,exynos4210";
|
||||
|
||||
aliases {
|
||||
serial0 = "/serial@13800000";
|
||||
console = "/serial@13820000";
|
||||
mmc0 = "sdhci@12510000";
|
||||
mmc2 = "sdhci@12530000";
|
||||
};
|
||||
|
||||
sdhci@12510000 {
|
||||
samsung,bus-width = <8>;
|
||||
samsung,timing = <1 3 3>;
|
||||
pwr-gpios = <&gpio 0x2008002 0>;
|
||||
};
|
||||
|
||||
sdhci@12520000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
samsung,bus-width = <4>;
|
||||
samsung,timing = <1 2 3>;
|
||||
cd-gpios = <&gpio 0x20c6004 0>;
|
||||
};
|
||||
|
||||
sdhci@12540000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fimd@11c00000 {
|
||||
compatible = "samsung,exynos-fimd";
|
||||
reg = <0x11c00000 0xa4>;
|
||||
|
||||
samsung,vl-freq = <60>;
|
||||
samsung,vl-col = <480>;
|
||||
samsung,vl-row = <800>;
|
||||
samsung,vl-width = <480>;
|
||||
samsung,vl-height = <800>;
|
||||
|
||||
samsung,vl-clkp = <0>;
|
||||
samsung,vl-oep = <0>;
|
||||
samsung,vl-hsp = <1>;
|
||||
samsung,vl-vsp = <1>;
|
||||
samsung,vl-dp = <1>;
|
||||
samsung,vl-bpix = <4>;
|
||||
|
||||
samsung,vl-hspw = <2>;
|
||||
samsung,vl-hbpd = <16>;
|
||||
samsung,vl-hfpd = <16>;
|
||||
samsung,vl-vspw = <2>;
|
||||
samsung,vl-vbpd = <8>;
|
||||
samsung,vl-vfpd = <8>;
|
||||
samsung,vl-cmd-allow-len = <0xf>;
|
||||
|
||||
samsung,pclk_name = <1>;
|
||||
samsung,sclk_div = <1>;
|
||||
|
||||
samsung,winid = <0>;
|
||||
samsung,power-on-delay = <10000>;
|
||||
samsung,interface-mode = <1>;
|
||||
samsung,mipi-enabled = <0>;
|
||||
samsung,dp-enabled;
|
||||
samsung,dual-lcd-enabled;
|
||||
|
||||
samsung,logo-on = <1>;
|
||||
samsung,resolution = <0>;
|
||||
samsung,rgb-mode = <0>;
|
||||
};
|
||||
};
|
||||
434
arch/arm/dts/exynos4412-trats2.dts
Normal file
434
arch/arm/dts/exynos4412-trats2.dts
Normal file
@ -0,0 +1,434 @@
|
||||
/*
|
||||
* Samsung's Exynos4412 based Trats2 board device tree source
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Samsung Trats2 based on Exynos4412";
|
||||
compatible = "samsung,trats2", "samsung,exynos4412";
|
||||
|
||||
config {
|
||||
samsung,dsim-device-name = "s6e8ax0";
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@13860000";
|
||||
i2c1 = "/i2c@13870000";
|
||||
i2c2 = "/i2c@13880000";
|
||||
i2c3 = "/i2c@13890000";
|
||||
i2c4 = "/i2c@138a0000";
|
||||
i2c5 = "/i2c@138b0000";
|
||||
i2c6 = "/i2c@138c0000";
|
||||
i2c7 = "/i2c@138d0000";
|
||||
serial0 = "/serial@13800000";
|
||||
console = "/serial@13820000";
|
||||
mmc0 = "sdhci@12510000";
|
||||
mmc2 = "sdhci@12530000";
|
||||
};
|
||||
|
||||
i2c@138d0000 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-slave-addr = <0x10>;
|
||||
samsung,i2c-max-bus-freq = <100000>;
|
||||
status = "okay";
|
||||
|
||||
max77686_pmic@09 {
|
||||
compatible = "maxim,max77686_pmic";
|
||||
interrupts = <7 0>;
|
||||
reg = <0x09 0 0>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
voltage-regulators {
|
||||
ldo1_reg: ldo1 {
|
||||
regulator-compatible = "LDO1";
|
||||
regulator-name = "VALIVE_1.0V_AP";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-mem-on;
|
||||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
regulator-compatible = "LDO2";
|
||||
regulator-name = "VM1M2_1.2V_AP";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-mem-on;
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
regulator-compatible = "LDO3";
|
||||
regulator-name = "VCC_1.8V_AP";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-mem-on;
|
||||
};
|
||||
|
||||
ldo4_reg: ldo4 {
|
||||
regulator-compatible = "LDO4";
|
||||
regulator-name = "VCC_2.8V_AP";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
regulator-mem-on;
|
||||
};
|
||||
|
||||
ldo5_reg: ldo5 {
|
||||
regulator-compatible = "LDO5";
|
||||
regulator-name = "VCC_1.8V_IO";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-mem-on;
|
||||
};
|
||||
|
||||
ldo6_reg: ldo6 {
|
||||
regulator-compatible = "LDO6";
|
||||
regulator-name = "VMPLL_1.0V_AP";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-mem-on;
|
||||
};
|
||||
|
||||
ldo7_reg: ldo7 {
|
||||
regulator-compatible = "LDO7";
|
||||
regulator-name = "VPLL_1.0V_AP";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-mem-on;
|
||||
};
|
||||
|
||||
ldo8_reg: ldo8 {
|
||||
regulator-compatible = "LDO8";
|
||||
regulator-name = "VMIPI_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
ldo9_reg: ldo9 {
|
||||
regulator-compatible = "LDO9";
|
||||
regulator-name = "CAM_ISP_MIPI_1.2V";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-mem-idle;
|
||||
};
|
||||
|
||||
ldo10_reg: ldo10 {
|
||||
regulator-compatible = "LDO10";
|
||||
regulator-name = "VMIPI_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
ldo11_reg: ldo11 {
|
||||
regulator-compatible = "LDO11";
|
||||
regulator-name = "VABB1_1.95V";
|
||||
regulator-min-microvolt = <1950000>;
|
||||
regulator-max-microvolt = <1950000>;
|
||||
regulator-always-on;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
ldo12_reg: ldo12 {
|
||||
regulator-compatible = "LDO12";
|
||||
regulator-name = "VUOTG_3.0V";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
ldo13_reg: ldo13 {
|
||||
regulator-compatible = "LDO13";
|
||||
regulator-name = "NFC_AVDD_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-mem-idle;
|
||||
};
|
||||
|
||||
ldo14_reg: ldo14 {
|
||||
regulator-compatible = "LDO14";
|
||||
regulator-name = "VABB2_1.95V";
|
||||
regulator-min-microvolt = <1950000>;
|
||||
regulator-max-microvolt = <1950000>;
|
||||
regulator-always-on;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
ldo15_reg: ldo15 {
|
||||
regulator-compatible = "LDO15";
|
||||
regulator-name = "VHSIC_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
ldo16_reg: ldo16 {
|
||||
regulator-compatible = "LDO16";
|
||||
regulator-name = "VHSIC_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
ldo17_reg: ldo17 {
|
||||
regulator-compatible = "LDO17";
|
||||
regulator-name = "CAM_SENSOR_CORE_1.2V";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-mem-idle;
|
||||
};
|
||||
|
||||
ldo18_reg: ldo18 {
|
||||
regulator-compatible = "LDO18";
|
||||
regulator-name = "CAM_ISP_SEN_IO_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-mem-idle;
|
||||
};
|
||||
|
||||
ldo19_reg: ldo19 {
|
||||
regulator-compatible = "LDO19";
|
||||
regulator-name = "VT_CAM_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-mem-idle;
|
||||
};
|
||||
|
||||
ldo20_reg: ldo20 {
|
||||
regulator-compatible = "LDO20";
|
||||
regulator-name = "VDDQ_PRE_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-mem-idle;
|
||||
};
|
||||
|
||||
ldo21_reg: ldo21 {
|
||||
regulator-compatible = "LDO21";
|
||||
regulator-name = "VTF_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-mem-idle;
|
||||
};
|
||||
|
||||
ldo22_reg: ldo22 {
|
||||
regulator-compatible = "LDO22";
|
||||
regulator-name = "VMEM_VDD_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
ldo23_reg: ldo23 {
|
||||
regulator-compatible = "LDO23";
|
||||
regulator-name = "TSP_AVDD_3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-mem-idle;
|
||||
};
|
||||
|
||||
ldo24_reg: ldo24 {
|
||||
regulator-compatible = "LDO24";
|
||||
regulator-name = "TSP_VDD_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-mem-idle;
|
||||
};
|
||||
|
||||
ldo25_reg: ldo25 {
|
||||
regulator-compatible = "LDO25";
|
||||
regulator-name = "LCD_VCC_3.3V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-mem-idle;
|
||||
};
|
||||
|
||||
ldo26_reg: ldo26 {
|
||||
regulator-compatible = "LDO26";
|
||||
regulator-name = "MOTOR_VCC_3.0V";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-mem-idle;
|
||||
};
|
||||
|
||||
buck1_reg: buck1 {
|
||||
regulator-compatible = "BUCK1";
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
buck2_reg: buck2 {
|
||||
regulator-compatible = "BUCK2";
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
buck3_reg: buck3 {
|
||||
regulator-compatible = "BUCK3";
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
buck4_reg: buck4 {
|
||||
regulator-compatible = "BUCK4";
|
||||
regulator-name = "vdd_g3d";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
buck5_reg: buck5 {
|
||||
regulator-compatible = "BUCK5";
|
||||
regulator-name = "VMEM_1.2V_AP";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck6_reg: buck6 {
|
||||
regulator-compatible = "BUCK6";
|
||||
regulator-name = "VCC_SUB_1.35V";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck7_reg: buck7 {
|
||||
regulator-compatible = "BUCK7";
|
||||
regulator-name = "VCC_SUB_2.0V";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck8_reg: buck8 {
|
||||
regulator-compatible = "BUCK8";
|
||||
regulator-name = "VMEM_VDDF_3.0V";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
regulator-mem-off;
|
||||
};
|
||||
|
||||
buck9_reg: buck9 {
|
||||
regulator-compatible = "BUCK9";
|
||||
regulator-name = "CAM_ISP_CORE_1.2V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-mem-off;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fimd@11c00000 {
|
||||
compatible = "samsung,exynos-fimd";
|
||||
reg = <0x11c00000 0xa4>;
|
||||
|
||||
samsung,vl-freq = <60>;
|
||||
samsung,vl-col = <720>;
|
||||
samsung,vl-row = <1280>;
|
||||
samsung,vl-width = <720>;
|
||||
samsung,vl-height = <1280>;
|
||||
|
||||
samsung,vl-clkp = <0>;
|
||||
samsung,vl-oep = <0>;
|
||||
samsung,vl-hsp = <1>;
|
||||
samsung,vl-vsp = <1>;
|
||||
samsung,vl-dp = <1>;
|
||||
samsung,vl-bpix = <4>;
|
||||
|
||||
samsung,vl-hspw = <5>;
|
||||
samsung,vl-hbpd = <10>;
|
||||
samsung,vl-hfpd = <10>;
|
||||
samsung,vl-vspw = <2>;
|
||||
samsung,vl-vbpd = <1>;
|
||||
samsung,vl-vfpd = <13>;
|
||||
samsung,vl-cmd-allow-len = <0xf>;
|
||||
|
||||
samsung,winid = <0>;
|
||||
samsung,power-on-delay = <30>;
|
||||
samsung,interface-mode = <1>;
|
||||
samsung,mipi-enabled = <1>;
|
||||
samsung,dp-enabled;
|
||||
samsung,dual-lcd-enabled;
|
||||
|
||||
samsung,logo-on = <1>;
|
||||
samsung,resolution = <0>;
|
||||
samsung,rgb-mode = <0>;
|
||||
};
|
||||
|
||||
mipidsi@11c80000 {
|
||||
compatible = "samsung,exynos-mipi-dsi";
|
||||
reg = <0x11c80000 0x5c>;
|
||||
|
||||
samsung,dsim-config-e-interface = <1>;
|
||||
samsung,dsim-config-e-virtual-ch = <0>;
|
||||
samsung,dsim-config-e-pixel-format = <7>;
|
||||
samsung,dsim-config-e-burst-mode = <1>;
|
||||
samsung,dsim-config-e-no-data-lane = <3>;
|
||||
samsung,dsim-config-e-byte-clk = <0>;
|
||||
samsung,dsim-config-hfp = <1>;
|
||||
|
||||
samsung,dsim-config-p = <3>;
|
||||
samsung,dsim-config-m = <120>;
|
||||
samsung,dsim-config-s = <1>;
|
||||
|
||||
samsung,dsim-config-pll-stable-time = <500>;
|
||||
samsung,dsim-config-esc-clk = <20000000>;
|
||||
samsung,dsim-config-stop-holding-cnt = <0x7ff>;
|
||||
samsung,dsim-config-bta-timeout = <0xff>;
|
||||
samsung,dsim-config-rx-timeout = <0xffff>;
|
||||
|
||||
samsung,dsim-device-id = <0xffffffff>;
|
||||
samsung,dsim-device-bus-id = <0>;
|
||||
|
||||
samsung,dsim-device-reverse-panel = <1>;
|
||||
};
|
||||
|
||||
sdhci@12510000 {
|
||||
samsung,bus-width = <8>;
|
||||
samsung,timing = <1 3 3>;
|
||||
pwr-gpios = <&gpio 0x2004002 0>;
|
||||
};
|
||||
|
||||
sdhci@12520000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
samsung,bus-width = <4>;
|
||||
samsung,timing = <1 2 3>;
|
||||
cd-gpios = <&gpio 0x20C6004 0>;
|
||||
};
|
||||
|
||||
sdhci@12540000 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@ -78,58 +78,7 @@
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct gpmc_cs {
|
||||
u32 config1; /* 0x00 */
|
||||
u32 config2; /* 0x04 */
|
||||
u32 config3; /* 0x08 */
|
||||
u32 config4; /* 0x0C */
|
||||
u32 config5; /* 0x10 */
|
||||
u32 config6; /* 0x14 */
|
||||
u32 config7; /* 0x18 */
|
||||
u32 nand_cmd; /* 0x1C */
|
||||
u32 nand_adr; /* 0x20 */
|
||||
u32 nand_dat; /* 0x24 */
|
||||
u8 res[8]; /* blow up to 0x30 byte */
|
||||
};
|
||||
|
||||
struct bch_res_0_3 {
|
||||
u32 bch_result_x[4];
|
||||
};
|
||||
|
||||
struct gpmc {
|
||||
u8 res1[0x10];
|
||||
u32 sysconfig; /* 0x10 */
|
||||
u8 res2[0x4];
|
||||
u32 irqstatus; /* 0x18 */
|
||||
u32 irqenable; /* 0x1C */
|
||||
u8 res3[0x20];
|
||||
u32 timeout_control; /* 0x40 */
|
||||
u8 res4[0xC];
|
||||
u32 config; /* 0x50 */
|
||||
u32 status; /* 0x54 */
|
||||
u8 res5[0x8]; /* 0x58 */
|
||||
struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
|
||||
u8 res6[0x14]; /* 0x1E0 */
|
||||
u32 ecc_config; /* 0x1F4 */
|
||||
u32 ecc_control; /* 0x1F8 */
|
||||
u32 ecc_size_config; /* 0x1FC */
|
||||
u32 ecc1_result; /* 0x200 */
|
||||
u32 ecc2_result; /* 0x204 */
|
||||
u32 ecc3_result; /* 0x208 */
|
||||
u32 ecc4_result; /* 0x20C */
|
||||
u32 ecc5_result; /* 0x210 */
|
||||
u32 ecc6_result; /* 0x214 */
|
||||
u32 ecc7_result; /* 0x218 */
|
||||
u32 ecc8_result; /* 0x21C */
|
||||
u32 ecc9_result; /* 0x220 */
|
||||
u8 res7[12]; /* 0x224 */
|
||||
u32 testmomde_ctrl; /* 0x230 */
|
||||
u8 res8[12]; /* 0x234 */
|
||||
struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
|
||||
};
|
||||
|
||||
/* Used for board specific gpmc initialization */
|
||||
extern struct gpmc *gpmc_cfg;
|
||||
|
||||
#ifndef CONFIG_AM43XX
|
||||
/* Encapsulating core pll registers */
|
||||
|
||||
@ -1,48 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
|
||||
* Rohit Choraria <rohitkc@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __ASM_ARCH_OMAP_GPMC_H
|
||||
#define __ASM_ARCH_OMAP_GPMC_H
|
||||
|
||||
/* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines are based on AM33xx ELM */
|
||||
#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
|
||||
.eccbytes = 32,\
|
||||
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
|
||||
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
|
||||
28, 29, 30, 31, 32, 33},\
|
||||
.oobfree = {\
|
||||
{.offset = 34,\
|
||||
.length = 30 } } \
|
||||
}
|
||||
|
||||
#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
|
||||
.eccbytes = 56,\
|
||||
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
|
||||
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
|
||||
28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
|
||||
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
|
||||
52, 53, 54, 55, 56, 57},\
|
||||
.oobfree = {\
|
||||
{.offset = 58,\
|
||||
.length = 6 } } \
|
||||
}
|
||||
|
||||
#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\
|
||||
.eccbytes = 104,\
|
||||
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
|
||||
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
|
||||
28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
|
||||
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
|
||||
52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
|
||||
64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
|
||||
76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
|
||||
88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
|
||||
100, 101, 102, 103, 104, 105},\
|
||||
.oobfree = {\
|
||||
{.offset = 106,\
|
||||
.length = 8 } } \
|
||||
}
|
||||
#endif /* __ASM_ARCH_OMAP_GPMC_H */
|
||||
@ -10,6 +10,7 @@
|
||||
|
||||
#ifndef _SYS_PROTO_H_
|
||||
#define _SYS_PROTO_H_
|
||||
#include <linux/mtd/omap_gpmc.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
#define BOARD_REV_ID 0x0
|
||||
|
||||
@ -214,7 +214,7 @@ static inline unsigned pin_to_mask(unsigned pin)
|
||||
|
||||
/* The following macros are need for backward compatibility */
|
||||
#define at91_set_GPIO_periph(x, y) \
|
||||
at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y)
|
||||
at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y)
|
||||
#define at91_set_A_periph(x, y) \
|
||||
at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
|
||||
#define at91_set_B_periph(x, y) \
|
||||
|
||||
@ -14,6 +14,10 @@ enum {
|
||||
BOOT_DEVICE_MMC1,
|
||||
BOOT_DEVICE_MMC2,
|
||||
BOOT_DEVICE_MMC2_2,
|
||||
#elif CONFIG_SYS_USE_NANDFLASH
|
||||
BOOT_DEVICE_NAND,
|
||||
#elif CONFIG_SYS_USE_SERIALFLASH
|
||||
BOOT_DEVICE_SPI,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
@ -15,7 +15,7 @@
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#define REG(addr) (*(volatile unsigned int *)(addr))
|
||||
#define REG_P(addr) ((volatile unsigned int *)(addr))
|
||||
|
||||
@ -14,4 +14,16 @@
|
||||
*/
|
||||
int exynos_init(void);
|
||||
|
||||
/*
|
||||
* Exynos board specific changes for
|
||||
* board_early_init_f
|
||||
*/
|
||||
int exynos_early_init_f(void);
|
||||
|
||||
/*
|
||||
* Exynos board specific changes for
|
||||
* board_power_init
|
||||
*/
|
||||
int exynos_power_init(void);
|
||||
|
||||
#endif /* EXYNOS_BOARD_H */
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
|
||||
#include <linux/list.h>
|
||||
#include <linux/fb.h>
|
||||
#include <lcd.h>
|
||||
|
||||
#define PANEL_NAME_SIZE (32)
|
||||
|
||||
@ -368,8 +369,12 @@ int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
|
||||
*lcd_dev);
|
||||
|
||||
void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
|
||||
void exynos_init_dsim_platform_data(vidinfo_t *vid);
|
||||
|
||||
/* panel driver init based on mipi dsi interface */
|
||||
void s6e8ax0_init(void);
|
||||
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
extern int mipi_power(void);
|
||||
#endif
|
||||
#endif /* _DSIM_H */
|
||||
|
||||
@ -53,6 +53,8 @@
|
||||
#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
|
||||
#define SDHCI_CTRL4_DRIVE_SHIFT (16)
|
||||
|
||||
#define SDHCI_MAX_HOSTS 4
|
||||
|
||||
int s5p_sdhci_init(u32 regbase, int index, int bus_width);
|
||||
|
||||
static inline int s5p_mmc_init(int index, int bus_width)
|
||||
@ -62,4 +64,9 @@ static inline int s5p_mmc_init(int index, int bus_width)
|
||||
|
||||
return s5p_sdhci_init(base, index, bus_width);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
int exynos_mmc_init(const void *blob);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -38,7 +38,7 @@
|
||||
* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
|
||||
*/
|
||||
#ifndef CONFIG_SYS_KWD_CONFIG
|
||||
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
|
||||
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
|
||||
#endif /* CONFIG_SYS_KWD_CONFIG */
|
||||
|
||||
/* Kirkwood has 2k of Security SRAM, use it for SP */
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/mb86r0x.h>
|
||||
|
||||
#endif
|
||||
|
||||
@ -77,59 +77,7 @@ struct ctrl_id {
|
||||
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct gpmc_cs {
|
||||
u32 config1; /* 0x00 */
|
||||
u32 config2; /* 0x04 */
|
||||
u32 config3; /* 0x08 */
|
||||
u32 config4; /* 0x0C */
|
||||
u32 config5; /* 0x10 */
|
||||
u32 config6; /* 0x14 */
|
||||
u32 config7; /* 0x18 */
|
||||
u32 nand_cmd; /* 0x1C */
|
||||
u32 nand_adr; /* 0x20 */
|
||||
u32 nand_dat; /* 0x24 */
|
||||
u8 res[8]; /* blow up to 0x30 byte */
|
||||
};
|
||||
|
||||
struct bch_res_0_3 {
|
||||
u32 bch_result_x[4];
|
||||
};
|
||||
|
||||
struct gpmc {
|
||||
u8 res1[0x10];
|
||||
u32 sysconfig; /* 0x10 */
|
||||
u8 res2[0x4];
|
||||
u32 irqstatus; /* 0x18 */
|
||||
u32 irqenable; /* 0x1C */
|
||||
u8 res3[0x20];
|
||||
u32 timeout_control; /* 0x40 */
|
||||
u8 res4[0xC];
|
||||
u32 config; /* 0x50 */
|
||||
u32 status; /* 0x54 */
|
||||
u8 res5[0x8]; /* 0x58 */
|
||||
struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
|
||||
u8 res6[0x14]; /* 0x1E0 */
|
||||
u32 ecc_config; /* 0x1F4 */
|
||||
u32 ecc_control; /* 0x1F8 */
|
||||
u32 ecc_size_config; /* 0x1FC */
|
||||
u32 ecc1_result; /* 0x200 */
|
||||
u32 ecc2_result; /* 0x204 */
|
||||
u32 ecc3_result; /* 0x208 */
|
||||
u32 ecc4_result; /* 0x20C */
|
||||
u32 ecc5_result; /* 0x210 */
|
||||
u32 ecc6_result; /* 0x214 */
|
||||
u32 ecc7_result; /* 0x218 */
|
||||
u32 ecc8_result; /* 0x21C */
|
||||
u32 ecc9_result; /* 0x220 */
|
||||
u8 res7[0x1C]; /* fill up to 0x240 */
|
||||
struct bch_res_0_3 bch_result_0_3[7]; /* 0x240 */
|
||||
};
|
||||
|
||||
/* Used for board specific gpmc initialization */
|
||||
extern struct gpmc *gpmc_cfg;
|
||||
|
||||
#else /* __ASSEMBLY__ */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define GPMC_CONFIG1 0x00
|
||||
#define GPMC_CONFIG2 0x04
|
||||
#define GPMC_CONFIG3 0x08
|
||||
|
||||
@ -419,6 +419,16 @@ enum {
|
||||
#define NET_GPMC_CONFIG6 0x00000FCF
|
||||
#define NET_GPMC_CONFIG7 0x00000f6c
|
||||
|
||||
/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
|
||||
#define NET_LAN9221_GPMC_CONFIG1 0x00001000
|
||||
#define NET_LAN9221_GPMC_CONFIG2 0x00060700
|
||||
#define NET_LAN9221_GPMC_CONFIG3 0x00020201
|
||||
#define NET_LAN9221_GPMC_CONFIG4 0x06000700
|
||||
#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
|
||||
#define NET_LAN9221_GPMC_CONFIG6 0x87030000
|
||||
#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
|
||||
|
||||
|
||||
/* max number of GPMC Chip Selects */
|
||||
#define GPMC_MAX_CS 8
|
||||
/* max number of GPMC regs */
|
||||
|
||||
@ -1,36 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
|
||||
* Rohit Choraria <rohitkc@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __ASM_ARCH_OMAP_GPMC_H
|
||||
#define __ASM_ARCH_OMAP_GPMC_H
|
||||
|
||||
/*
|
||||
* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines using the BCH library.
|
||||
* The OOB layout was first defined by linx kernel in commit
|
||||
* 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c, we have to reuse it here cause
|
||||
* we want to be compatible.
|
||||
*/
|
||||
#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
|
||||
.eccbytes = 56,\
|
||||
.eccpos = {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\
|
||||
23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\
|
||||
37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,\
|
||||
51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63},\
|
||||
.oobfree = {\
|
||||
{.offset = 2,\
|
||||
.length = 10 } } \
|
||||
}
|
||||
|
||||
/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
|
||||
#define NET_LAN9221_GPMC_CONFIG1 0x00001000
|
||||
#define NET_LAN9221_GPMC_CONFIG2 0x00060700
|
||||
#define NET_LAN9221_GPMC_CONFIG3 0x00020201
|
||||
#define NET_LAN9221_GPMC_CONFIG4 0x06000700
|
||||
#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
|
||||
#define NET_LAN9221_GPMC_CONFIG6 0x87030000
|
||||
#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
|
||||
|
||||
#endif /* __ASM_ARCH_OMAP_GPMC_H */
|
||||
@ -7,6 +7,7 @@
|
||||
*/
|
||||
#ifndef _SYS_PROTO_H_
|
||||
#define _SYS_PROTO_H_
|
||||
#include <linux/mtd/omap_gpmc.h>
|
||||
|
||||
typedef struct {
|
||||
u32 mtype;
|
||||
|
||||
@ -14,51 +14,6 @@
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct gpmc_cs {
|
||||
u32 config1; /* 0x00 */
|
||||
u32 config2; /* 0x04 */
|
||||
u32 config3; /* 0x08 */
|
||||
u32 config4; /* 0x0C */
|
||||
u32 config5; /* 0x10 */
|
||||
u32 config6; /* 0x14 */
|
||||
u32 config7; /* 0x18 */
|
||||
u32 nand_cmd; /* 0x1C */
|
||||
u32 nand_adr; /* 0x20 */
|
||||
u32 nand_dat; /* 0x24 */
|
||||
u8 res[8]; /* blow up to 0x30 byte */
|
||||
};
|
||||
|
||||
struct gpmc {
|
||||
u8 res1[0x10];
|
||||
u32 sysconfig; /* 0x10 */
|
||||
u8 res2[0x4];
|
||||
u32 irqstatus; /* 0x18 */
|
||||
u32 irqenable; /* 0x1C */
|
||||
u8 res3[0x20];
|
||||
u32 timeout_control; /* 0x40 */
|
||||
u8 res4[0xC];
|
||||
u32 config; /* 0x50 */
|
||||
u32 status; /* 0x54 */
|
||||
u8 res5[0x8]; /* 0x58 */
|
||||
struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
|
||||
u8 res6[0x14]; /* 0x1E0 */
|
||||
u32 ecc_config; /* 0x1F4 */
|
||||
u32 ecc_control; /* 0x1F8 */
|
||||
u32 ecc_size_config; /* 0x1FC */
|
||||
u32 ecc1_result; /* 0x200 */
|
||||
u32 ecc2_result; /* 0x204 */
|
||||
u32 ecc3_result; /* 0x208 */
|
||||
u32 ecc4_result; /* 0x20C */
|
||||
u32 ecc5_result; /* 0x210 */
|
||||
u32 ecc6_result; /* 0x214 */
|
||||
u32 ecc7_result; /* 0x218 */
|
||||
u32 ecc8_result; /* 0x21C */
|
||||
u32 ecc9_result; /* 0x220 */
|
||||
};
|
||||
|
||||
/* Used for board specific gpmc initialization */
|
||||
extern struct gpmc *gpmc_cfg;
|
||||
|
||||
struct gptimer {
|
||||
u32 tidr; /* 0x00 r */
|
||||
u8 res[0xc];
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/omap_common.h>
|
||||
#include <linux/mtd/omap_gpmc.h>
|
||||
#include <asm/arch/mux_omap4.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
@ -16,51 +16,6 @@
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct gpmc_cs {
|
||||
u32 config1; /* 0x00 */
|
||||
u32 config2; /* 0x04 */
|
||||
u32 config3; /* 0x08 */
|
||||
u32 config4; /* 0x0C */
|
||||
u32 config5; /* 0x10 */
|
||||
u32 config6; /* 0x14 */
|
||||
u32 config7; /* 0x18 */
|
||||
u32 nand_cmd; /* 0x1C */
|
||||
u32 nand_adr; /* 0x20 */
|
||||
u32 nand_dat; /* 0x24 */
|
||||
u8 res[8]; /* blow up to 0x30 byte */
|
||||
};
|
||||
|
||||
struct gpmc {
|
||||
u8 res1[0x10];
|
||||
u32 sysconfig; /* 0x10 */
|
||||
u8 res2[0x4];
|
||||
u32 irqstatus; /* 0x18 */
|
||||
u32 irqenable; /* 0x1C */
|
||||
u8 res3[0x20];
|
||||
u32 timeout_control; /* 0x40 */
|
||||
u8 res4[0xC];
|
||||
u32 config; /* 0x50 */
|
||||
u32 status; /* 0x54 */
|
||||
u8 res5[0x8]; /* 0x58 */
|
||||
struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
|
||||
u8 res6[0x14]; /* 0x1E0 */
|
||||
u32 ecc_config; /* 0x1F4 */
|
||||
u32 ecc_control; /* 0x1F8 */
|
||||
u32 ecc_size_config; /* 0x1FC */
|
||||
u32 ecc1_result; /* 0x200 */
|
||||
u32 ecc2_result; /* 0x204 */
|
||||
u32 ecc3_result; /* 0x208 */
|
||||
u32 ecc4_result; /* 0x20C */
|
||||
u32 ecc5_result; /* 0x210 */
|
||||
u32 ecc6_result; /* 0x214 */
|
||||
u32 ecc7_result; /* 0x218 */
|
||||
u32 ecc8_result; /* 0x21C */
|
||||
u32 ecc9_result; /* 0x220 */
|
||||
};
|
||||
|
||||
/* Used for board specific gpmc initialization */
|
||||
extern struct gpmc *gpmc_cfg;
|
||||
|
||||
struct gptimer {
|
||||
u32 tidr; /* 0x00 r */
|
||||
u8 res1[0xc];
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/omap_common.h>
|
||||
#include <linux/mtd/omap_gpmc.h>
|
||||
#include <asm/arch/clock.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
@ -298,14 +298,25 @@ struct pmc_ctlr {
|
||||
#define PMC_XOFS_SHIFT 1
|
||||
#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
|
||||
|
||||
#if defined(CONFIG_TEGRA114)
|
||||
#define TIMER_MULT_SHIFT 0
|
||||
#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
|
||||
#define TIMER_MULT_CPU_SHIFT 2
|
||||
#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
|
||||
#elif defined(CONFIG_TEGRA124)
|
||||
#define TIMER_MULT_SHIFT 0
|
||||
#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
|
||||
#define TIMER_MULT_CPU_SHIFT 3
|
||||
#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT)
|
||||
#endif
|
||||
|
||||
#define MULT_1 0
|
||||
#define MULT_2 1
|
||||
#define MULT_4 2
|
||||
#define MULT_8 3
|
||||
#if defined(CONFIG_TEGRA124)
|
||||
#define MULT_16 4
|
||||
#endif
|
||||
|
||||
#define AMAP_WRITE_SHIFT 20
|
||||
#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT)
|
||||
|
||||
@ -34,7 +34,12 @@
|
||||
#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
|
||||
#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
|
||||
#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
|
||||
#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
|
||||
defined(CONFIG_TEGRA114)
|
||||
#define NV_PA_CSITE_BASE 0x70040000
|
||||
#else
|
||||
#define NV_PA_CSITE_BASE 0x70800000
|
||||
#endif
|
||||
#define TEGRA_USB_ADDR_MASK 0xFFFFC000
|
||||
|
||||
#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
|
||||
|
||||
@ -17,6 +17,8 @@
|
||||
#ifndef _TEGRA114_H_
|
||||
#define _TEGRA114_H_
|
||||
|
||||
#define CONFIG_TEGRA114
|
||||
|
||||
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
|
||||
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
|
||||
|
||||
|
||||
@ -8,6 +8,8 @@
|
||||
#ifndef _TEGRA124_H_
|
||||
#define _TEGRA124_H_
|
||||
|
||||
#define CONFIG_TEGRA124
|
||||
|
||||
#define NV_PA_SDRAM_BASE 0x80000000
|
||||
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
|
||||
#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
|
||||
|
||||
@ -8,6 +8,8 @@
|
||||
#ifndef _TEGRA20_H_
|
||||
#define _TEGRA20_H_
|
||||
|
||||
#define CONFIG_TEGRA20
|
||||
|
||||
#define NV_PA_SDRAM_BASE 0x00000000
|
||||
|
||||
#include <asm/arch-tegra/tegra.h>
|
||||
|
||||
@ -17,6 +17,8 @@
|
||||
#ifndef _TEGRA30_H_
|
||||
#define _TEGRA30_H_
|
||||
|
||||
#define CONFIG_TEGRA30
|
||||
|
||||
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
|
||||
|
||||
#include <asm/arch-tegra/tegra.h>
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#define ASYNC_EMIF_NUM_CS 4
|
||||
#define ASYNC_EMIF_MODE_NOR 0
|
||||
|
||||
@ -19,5 +19,6 @@ extern void zynq_ddrc_init(void);
|
||||
|
||||
/* Driver extern functions */
|
||||
extern int zynq_sdhci_init(u32 regbase);
|
||||
extern int zynq_sdhci_of_init(const void *blob);
|
||||
|
||||
#endif /* _SYS_PROTO_H_ */
|
||||
|
||||
@ -1,87 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
|
||||
* Rohit Choraria <rohitkc@ti.com>
|
||||
*
|
||||
* (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __ASM_OMAP_GPMC_H
|
||||
#define __ASM_OMAP_GPMC_H
|
||||
|
||||
#include <asm/arch/omap_gpmc.h>
|
||||
|
||||
#define GPMC_BUF_EMPTY 0
|
||||
#define GPMC_BUF_FULL 1
|
||||
|
||||
#define ECCCLEAR (0x1 << 8)
|
||||
#define ECCRESULTREG1 (0x1 << 0)
|
||||
#define ECCSIZE512BYTE 0xFF
|
||||
#define ECCSIZE1 (ECCSIZE512BYTE << 22)
|
||||
#define ECCSIZE0 (ECCSIZE512BYTE << 12)
|
||||
#define ECCSIZE0SEL (0x000 << 0)
|
||||
|
||||
/* Generic ECC Layouts */
|
||||
/* Large Page x8 NAND device Layout */
|
||||
#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
|
||||
#define GPMC_NAND_HW_ECC_LAYOUT {\
|
||||
.eccbytes = 12,\
|
||||
.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
|
||||
9, 10, 11, 12},\
|
||||
.oobfree = {\
|
||||
{.offset = 13,\
|
||||
.length = 51 } } \
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Large Page x16 NAND device Layout */
|
||||
#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
|
||||
#define GPMC_NAND_HW_ECC_LAYOUT {\
|
||||
.eccbytes = 12,\
|
||||
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
|
||||
10, 11, 12, 13},\
|
||||
.oobfree = {\
|
||||
{.offset = 14,\
|
||||
.length = 50 } } \
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Small Page x8 NAND device Layout */
|
||||
#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
|
||||
#define GPMC_NAND_HW_ECC_LAYOUT {\
|
||||
.eccbytes = 3,\
|
||||
.eccpos = {1, 2, 3},\
|
||||
.oobfree = {\
|
||||
{.offset = 4,\
|
||||
.length = 12 } } \
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Small Page x16 NAND device Layout */
|
||||
#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
|
||||
#define GPMC_NAND_HW_ECC_LAYOUT {\
|
||||
.eccbytes = 3,\
|
||||
.eccpos = {2, 3, 4},\
|
||||
.oobfree = {\
|
||||
{.offset = 5,\
|
||||
.length = 11 } } \
|
||||
}
|
||||
#endif
|
||||
|
||||
enum omap_ecc {
|
||||
/* 1-bit ECC calculation by Software, Error detection by Software */
|
||||
OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
|
||||
/* 1-bit ECC calculation by GPMC, Error detection by Software */
|
||||
/* ECC layout compatible to legacy ROMCODE. */
|
||||
OMAP_ECC_HAM1_CODE_HW,
|
||||
/* 4-bit ECC calculation by GPMC, Error detection by Software */
|
||||
OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
|
||||
/* 4-bit ECC calculation by GPMC, Error detection by ELM */
|
||||
OMAP_ECC_BCH4_CODE_HW,
|
||||
/* 8-bit ECC calculation by GPMC, Error detection by Software */
|
||||
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
|
||||
/* 8-bit ECC calculation by GPMC, Error detection by ELM */
|
||||
OMAP_ECC_BCH8_CODE_HW,
|
||||
};
|
||||
|
||||
#endif /* __ASM_OMAP_GPMC_H */
|
||||
@ -1,39 +0,0 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
/* Size defintions
|
||||
* Copyright (C) ARM Limited 1998. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __sizes_h
|
||||
#define __sizes_h 1
|
||||
|
||||
/* handy sizes */
|
||||
#define SZ_1K 0x00000400
|
||||
#define SZ_4K 0x00001000
|
||||
#define SZ_8K 0x00002000
|
||||
#define SZ_16K 0x00004000
|
||||
#define SZ_32K 0x00008000
|
||||
#define SZ_64K 0x00010000
|
||||
#define SZ_128K 0x00020000
|
||||
#define SZ_256K 0x00040000
|
||||
#define SZ_512K 0x00080000
|
||||
|
||||
#define SZ_1M 0x00100000
|
||||
#define SZ_2M 0x00200000
|
||||
#define SZ_4M 0x00400000
|
||||
#define SZ_8M 0x00800000
|
||||
#define SZ_16M 0x01000000
|
||||
#define SZ_31M 0x01F00000
|
||||
#define SZ_32M 0x02000000
|
||||
#define SZ_64M 0x04000000
|
||||
#define SZ_128M 0x08000000
|
||||
#define SZ_256M 0x10000000
|
||||
#define SZ_512M 0x20000000
|
||||
|
||||
#define SZ_1G 0x40000000
|
||||
#define SZ_2G 0x80000000
|
||||
|
||||
#endif
|
||||
|
||||
/* END */
|
||||
@ -5,17 +5,8 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
# Build private libgcc only when asked for
|
||||
ifdef USE_PRIVATE_LIBGCC
|
||||
lib-y += _ashldi3.o
|
||||
lib-y += _ashrdi3.o
|
||||
lib-y += _divsi3.o
|
||||
lib-y += _lshrdi3.o
|
||||
lib-y += _modsi3.o
|
||||
lib-y += _udivsi3.o
|
||||
lib-y += _umodsi3.o
|
||||
lib-y += div0.o
|
||||
endif
|
||||
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
|
||||
_lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o
|
||||
|
||||
ifdef CONFIG_ARM64
|
||||
obj-y += crt0_64.o
|
||||
|
||||
@ -33,6 +33,7 @@
|
||||
#include <nand.h>
|
||||
#include <onenand_uboot.h>
|
||||
#include <mmc.h>
|
||||
#include <scsi.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdtdec.h>
|
||||
#include <post.h>
|
||||
@ -593,6 +594,11 @@ void board_init_r(gd_t *id, ulong dest_addr)
|
||||
mmc_initialize(gd->bd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_SCSI
|
||||
puts("SCSI: ");
|
||||
scsi_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAS_DATAFLASH
|
||||
AT91F_DataflashInit();
|
||||
dataflash_print_info();
|
||||
|
||||
@ -5,7 +5,10 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
CROSS_COMPILE ?= avr32-linux-
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
CROSS_COMPILE := avr32-linux-
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_AVR32
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
|
||||
|
||||
|
||||
@ -5,7 +5,9 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
CROSS_COMPILE ?= bfin-uclinux-
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
CROSS_COMPILE := bfin-uclinux-
|
||||
endif
|
||||
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x1000 -m elf32bfin
|
||||
|
||||
@ -41,6 +43,7 @@ CREATE_LDR_ENV =
|
||||
endif
|
||||
|
||||
SYM_PREFIX = _
|
||||
export SYM_PREFIX
|
||||
|
||||
LDR_FLAGS-y :=
|
||||
LDR_FLAGS-$(CONFIG_BFIN_BOOTROM_USES_EVT1) += -J
|
||||
|
||||
@ -5,11 +5,14 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
CROSS_COMPILE ?= m68k-elf-
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
CROSS_COMPILE := m68k-elf-
|
||||
endif
|
||||
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__
|
||||
PLATFORM_LDFLAGS += -n
|
||||
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
|
||||
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
|
||||
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
|
||||
LDFLAGS_FINAL += --gc-sections
|
||||
|
||||
@ -7,5 +7,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
|
||||
PLATFORM_CPPFLAGS += -mcpu=52277 -fPIC
|
||||
|
||||
@ -7,5 +7,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
|
||||
PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC
|
||||
|
||||
@ -7,16 +7,14 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
|
||||
|
||||
cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
|
||||
is5208:=$(shell grep CONFIG_M5208 $(TOPDIR)/include/$(cfg))
|
||||
is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
|
||||
is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
|
||||
is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
|
||||
is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
|
||||
is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
|
||||
is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
|
||||
cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
|
||||
is5208:=$(shell grep CONFIG_M5208 $(srctree)/include/$(cfg))
|
||||
is5249:=$(shell grep CONFIG_M5249 $(srctree)/include/$(cfg))
|
||||
is5253:=$(shell grep CONFIG_M5253 $(srctree)/include/$(cfg))
|
||||
is5271:=$(shell grep CONFIG_M5271 $(srctree)/include/$(cfg))
|
||||
is5272:=$(shell grep CONFIG_M5272 $(srctree)/include/$(cfg))
|
||||
is5275:=$(shell grep CONFIG_M5275 $(srctree)/include/$(cfg))
|
||||
is5282:=$(shell grep CONFIG_M5282 $(srctree)/include/$(cfg))
|
||||
|
||||
ifneq (,$(findstring CONFIG_M5208,$(is5208)))
|
||||
PLATFORM_CPPFLAGS += -mcpu=5208
|
||||
|
||||
@ -7,11 +7,9 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
|
||||
|
||||
cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
|
||||
is5301x:=$(shell grep CONFIG_MCF5301x $(TOPDIR)/include/$(cfg))
|
||||
is532x:=$(shell grep CONFIG_MCF532x $(TOPDIR)/include/$(cfg))
|
||||
cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
|
||||
is5301x:=$(shell grep CONFIG_MCF5301x $(srctree)/include/$(cfg))
|
||||
is532x:=$(shell grep CONFIG_MCF532x $(srctree)/include/$(cfg))
|
||||
|
||||
ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x)))
|
||||
PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC
|
||||
|
||||
@ -9,10 +9,8 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
|
||||
|
||||
cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
|
||||
is5441x:=$(shell grep CONFIG_MCF5441x $(TOPDIR)/include/$(cfg))
|
||||
cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
|
||||
is5441x:=$(shell grep CONFIG_MCF5441x $(srctree)/include/$(cfg))
|
||||
|
||||
ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x)))
|
||||
PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC
|
||||
|
||||
@ -7,7 +7,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
|
||||
PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC
|
||||
|
||||
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
|
||||
|
||||
@ -8,10 +8,10 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
CROSS_COMPILE ?= mb-
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
CROSS_COMPILE := mb-
|
||||
endif
|
||||
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000
|
||||
|
||||
PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
|
||||
|
||||
LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
|
||||
|
||||
@ -5,7 +5,9 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
CROSS_COMPILE ?= mips_4KC-
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
CROSS_COMPILE := mips_4KC-
|
||||
endif
|
||||
|
||||
# Handle special prefix in ELDK 4.0 toolchain
|
||||
ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
|
||||
|
||||
@ -839,104 +839,7 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list)
|
||||
* Virtual Root Hub
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
/* Device descriptor */
|
||||
static __u8 root_hub_dev_des[] =
|
||||
{
|
||||
0x12, /* __u8 bLength; */
|
||||
0x01, /* __u8 bDescriptorType; Device */
|
||||
0x10, /* __u16 bcdUSB; v1.1 */
|
||||
0x01,
|
||||
0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
|
||||
0x00, /* __u8 bDeviceSubClass; */
|
||||
0x00, /* __u8 bDeviceProtocol; */
|
||||
0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
|
||||
0x00, /* __u16 idVendor; */
|
||||
0x00,
|
||||
0x00, /* __u16 idProduct; */
|
||||
0x00,
|
||||
0x00, /* __u16 bcdDevice; */
|
||||
0x00,
|
||||
0x00, /* __u8 iManufacturer; */
|
||||
0x01, /* __u8 iProduct; */
|
||||
0x00, /* __u8 iSerialNumber; */
|
||||
0x01 /* __u8 bNumConfigurations; */
|
||||
};
|
||||
|
||||
|
||||
/* Configuration descriptor */
|
||||
static __u8 root_hub_config_des[] =
|
||||
{
|
||||
0x09, /* __u8 bLength; */
|
||||
0x02, /* __u8 bDescriptorType; Configuration */
|
||||
0x19, /* __u16 wTotalLength; */
|
||||
0x00,
|
||||
0x01, /* __u8 bNumInterfaces; */
|
||||
0x01, /* __u8 bConfigurationValue; */
|
||||
0x00, /* __u8 iConfiguration; */
|
||||
0x40, /* __u8 bmAttributes;
|
||||
Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
|
||||
0x00, /* __u8 MaxPower; */
|
||||
|
||||
/* interface */
|
||||
0x09, /* __u8 if_bLength; */
|
||||
0x04, /* __u8 if_bDescriptorType; Interface */
|
||||
0x00, /* __u8 if_bInterfaceNumber; */
|
||||
0x00, /* __u8 if_bAlternateSetting; */
|
||||
0x01, /* __u8 if_bNumEndpoints; */
|
||||
0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
|
||||
0x00, /* __u8 if_bInterfaceSubClass; */
|
||||
0x00, /* __u8 if_bInterfaceProtocol; */
|
||||
0x00, /* __u8 if_iInterface; */
|
||||
|
||||
/* endpoint */
|
||||
0x07, /* __u8 ep_bLength; */
|
||||
0x05, /* __u8 ep_bDescriptorType; Endpoint */
|
||||
0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
|
||||
0x03, /* __u8 ep_bmAttributes; Interrupt */
|
||||
0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
|
||||
0x00,
|
||||
0xff /* __u8 ep_bInterval; 255 ms */
|
||||
};
|
||||
|
||||
static unsigned char root_hub_str_index0[] =
|
||||
{
|
||||
0x04, /* __u8 bLength; */
|
||||
0x03, /* __u8 bDescriptorType; String-descriptor */
|
||||
0x09, /* __u8 lang ID */
|
||||
0x04, /* __u8 lang ID */
|
||||
};
|
||||
|
||||
static unsigned char root_hub_str_index1[] =
|
||||
{
|
||||
28, /* __u8 bLength; */
|
||||
0x03, /* __u8 bDescriptorType; String-descriptor */
|
||||
'O', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'H', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'C', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'I', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
' ', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'R', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'o', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'o', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
't', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
' ', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'H', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'u', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'b', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
};
|
||||
#include <usbroothubdes.h>
|
||||
|
||||
/* Hub class-specific descriptor is constructed dynamically */
|
||||
|
||||
|
||||
@ -11,9 +11,7 @@
|
||||
# Note: Toolchains with binutils prior to v2.16
|
||||
# are no longer supported by U-Boot MIPS tree!
|
||||
#
|
||||
MIPSFLAGS := -march=mips32r2
|
||||
|
||||
PLATFORM_CPPFLAGS += $(MIPSFLAGS)
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MIPS32 -march=mips32r2
|
||||
PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
|
||||
ifdef CONFIG_SYS_BIG_ENDIAN
|
||||
PLATFORM_LDFLAGS += -m elf32btsmip
|
||||
@ -21,4 +19,5 @@ else
|
||||
PLATFORM_LDFLAGS += -m elf32ltsmip
|
||||
endif
|
||||
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T $(srctree)/$(src)/mips.lds
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
|
||||
-T $(srctree)/examples/standalone/mips.lds
|
||||
|
||||
@ -11,9 +11,7 @@
|
||||
# Note: Toolchains with binutils prior to v2.16
|
||||
# are no longer supported by U-Boot MIPS tree!
|
||||
#
|
||||
MIPSFLAGS = -march=mips64
|
||||
|
||||
PLATFORM_CPPFLAGS += $(MIPSFLAGS)
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MIPS64 -march=mips64
|
||||
PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
|
||||
ifdef CONFIG_SYS_BIG_ENDIAN
|
||||
PLATFORM_LDFLAGS += -m elf64btsmip
|
||||
@ -21,4 +19,5 @@ else
|
||||
PLATFORM_LDFLAGS += -m elf64ltsmip
|
||||
endif
|
||||
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T $(srctree)/$(src)/mips64.lds
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \
|
||||
-T $(srctree)/examples/standalone/mips64.lds
|
||||
|
||||
@ -12,4 +12,5 @@ else
|
||||
PLATFORM_LDFLAGS += -m elf32ltsmip
|
||||
endif
|
||||
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T $(srctree)/$(src)/mips.lds
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
|
||||
-T $(srctree)/examples/standalone/mips.lds
|
||||
|
||||
@ -27,18 +27,12 @@ typedef unsigned short __u16;
|
||||
typedef __signed__ int __s32;
|
||||
typedef unsigned int __u32;
|
||||
|
||||
#if (_MIPS_SZLONG == 64)
|
||||
|
||||
typedef __signed__ long __s64;
|
||||
typedef unsigned long __u64;
|
||||
|
||||
#else
|
||||
|
||||
#if defined(__GNUC__)
|
||||
__extension__ typedef __signed__ long long __s64;
|
||||
__extension__ typedef unsigned long long __u64;
|
||||
#endif
|
||||
|
||||
#else
|
||||
typedef __signed__ long long __s64;
|
||||
typedef unsigned long long __u64;
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
@ -61,19 +55,8 @@ typedef unsigned short u16;
|
||||
typedef __signed int s32;
|
||||
typedef unsigned int u32;
|
||||
|
||||
#if (_MIPS_SZLONG == 64)
|
||||
|
||||
typedef __signed__ long s64;
|
||||
typedef unsigned long u64;
|
||||
|
||||
#else
|
||||
|
||||
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
|
||||
typedef __signed__ long long s64;
|
||||
typedef unsigned long long u64;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
|
||||
|| defined(CONFIG_64BIT)
|
||||
|
||||
@ -8,9 +8,4 @@
|
||||
obj-y += board.o
|
||||
obj-$(CONFIG_CMD_BOOTM) += bootm.o
|
||||
|
||||
# Build private libgcc only when asked for
|
||||
ifdef USE_PRIVATE_LIBGCC
|
||||
lib-y += ashldi3.o
|
||||
lib-y += ashrdi3.o
|
||||
lib-y += lshrdi3.o
|
||||
endif
|
||||
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o
|
||||
|
||||
@ -8,9 +8,12 @@
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
CROSS_COMPILE ?= nds32le-linux-
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
CROSS_COMPILE := nds32le-linux-
|
||||
endif
|
||||
|
||||
CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T $(srctree)/$(src)/nds32.lds
|
||||
CONFIG_STANDALONE_LOAD_ADDR = 0x300000 \
|
||||
-T $(srctree)/examples/standalone/nds32.lds
|
||||
|
||||
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -mrelax
|
||||
PLATFORM_RELFLAGS += -gdwarf-2
|
||||
|
||||
@ -6,7 +6,9 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
CROSS_COMPILE ?= nios2-elf-
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
CROSS_COMPILE := nios2-elf-
|
||||
endif
|
||||
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000
|
||||
|
||||
|
||||
@ -5,12 +5,12 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
CROSS_COMPILE ?= or32-elf-
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
CROSS_COMPILE := or32-elf-
|
||||
endif
|
||||
|
||||
# r10 used for global object pointer, already set in OR32 GCC but just to be
|
||||
# clear
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_OPENRISC -D__OR1K__ -ffixed-r10
|
||||
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
|
||||
|
||||
LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
|
||||
|
||||
@ -5,7 +5,9 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
CROSS_COMPILE ?= ppc_8xx-
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
CROSS_COMPILE := ppc_8xx-
|
||||
endif
|
||||
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
|
||||
LDFLAGS_FINAL += --gc-sections
|
||||
@ -33,5 +35,14 @@ endif
|
||||
|
||||
# Only test once
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ALL-y += checkgcc4
|
||||
archprepare: checkgcc4
|
||||
|
||||
# GCC 3.x is reported to have problems generating the type of relocation
|
||||
# that U-Boot wants.
|
||||
# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
|
||||
checkgcc4:
|
||||
@if test $(call cc-version) -lt 0400; then \
|
||||
echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
|
||||
false; \
|
||||
fi
|
||||
endif
|
||||
|
||||
@ -842,104 +842,7 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list)
|
||||
* Virtual Root Hub
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
/* Device descriptor */
|
||||
static __u8 root_hub_dev_des[] =
|
||||
{
|
||||
0x12, /* __u8 bLength; */
|
||||
0x01, /* __u8 bDescriptorType; Device */
|
||||
0x10, /* __u16 bcdUSB; v1.1 */
|
||||
0x01,
|
||||
0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
|
||||
0x00, /* __u8 bDeviceSubClass; */
|
||||
0x00, /* __u8 bDeviceProtocol; */
|
||||
0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
|
||||
0x00, /* __u16 idVendor; */
|
||||
0x00,
|
||||
0x00, /* __u16 idProduct; */
|
||||
0x00,
|
||||
0x00, /* __u16 bcdDevice; */
|
||||
0x00,
|
||||
0x00, /* __u8 iManufacturer; */
|
||||
0x01, /* __u8 iProduct; */
|
||||
0x00, /* __u8 iSerialNumber; */
|
||||
0x01 /* __u8 bNumConfigurations; */
|
||||
};
|
||||
|
||||
|
||||
/* Configuration descriptor */
|
||||
static __u8 root_hub_config_des[] =
|
||||
{
|
||||
0x09, /* __u8 bLength; */
|
||||
0x02, /* __u8 bDescriptorType; Configuration */
|
||||
0x19, /* __u16 wTotalLength; */
|
||||
0x00,
|
||||
0x01, /* __u8 bNumInterfaces; */
|
||||
0x01, /* __u8 bConfigurationValue; */
|
||||
0x00, /* __u8 iConfiguration; */
|
||||
0x40, /* __u8 bmAttributes;
|
||||
Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
|
||||
0x00, /* __u8 MaxPower; */
|
||||
|
||||
/* interface */
|
||||
0x09, /* __u8 if_bLength; */
|
||||
0x04, /* __u8 if_bDescriptorType; Interface */
|
||||
0x00, /* __u8 if_bInterfaceNumber; */
|
||||
0x00, /* __u8 if_bAlternateSetting; */
|
||||
0x01, /* __u8 if_bNumEndpoints; */
|
||||
0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
|
||||
0x00, /* __u8 if_bInterfaceSubClass; */
|
||||
0x00, /* __u8 if_bInterfaceProtocol; */
|
||||
0x00, /* __u8 if_iInterface; */
|
||||
|
||||
/* endpoint */
|
||||
0x07, /* __u8 ep_bLength; */
|
||||
0x05, /* __u8 ep_bDescriptorType; Endpoint */
|
||||
0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
|
||||
0x03, /* __u8 ep_bmAttributes; Interrupt */
|
||||
0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
|
||||
0x00,
|
||||
0xff /* __u8 ep_bInterval; 255 ms */
|
||||
};
|
||||
|
||||
static unsigned char root_hub_str_index0[] =
|
||||
{
|
||||
0x04, /* __u8 bLength; */
|
||||
0x03, /* __u8 bDescriptorType; String-descriptor */
|
||||
0x09, /* __u8 lang ID */
|
||||
0x04, /* __u8 lang ID */
|
||||
};
|
||||
|
||||
static unsigned char root_hub_str_index1[] =
|
||||
{
|
||||
28, /* __u8 bLength; */
|
||||
0x03, /* __u8 bDescriptorType; String-descriptor */
|
||||
'O', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'H', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'C', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'I', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
' ', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'R', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'o', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'o', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
't', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
' ', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'H', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'u', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'b', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
};
|
||||
#include <usbroothubdes.h>
|
||||
|
||||
/* Hub class-specific descriptor is constructed dynamically */
|
||||
|
||||
|
||||
@ -5,5 +5,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 \
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC8260 -DCONFIG_CPM2 \
|
||||
-mstring -mcpu=603e -mmultiple
|
||||
|
||||
@ -9,8 +9,6 @@
|
||||
#include <mpc8260.h>
|
||||
#include <version.h>
|
||||
|
||||
#define CONFIG_8260 1 /* needed for Linux kernel header files */
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <ppc_defs.h>
|
||||
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#include <mpc8260.h>
|
||||
#include <version.h>
|
||||
|
||||
#define CONFIG_8260 1 /* needed for Linux kernel header files */
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <ppc_defs.h>
|
||||
|
||||
|
||||
@ -18,12 +18,32 @@ struct serdes_config {
|
||||
#ifdef CONFIG_PPC_B4860
|
||||
static struct serdes_config serdes1_cfg_tbl[] = {
|
||||
/* SerDes 1 */
|
||||
{0x02, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x04, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x05, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x06, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x08, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x09, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x0A, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x0B, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x0C, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1}},
|
||||
{0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1}},
|
||||
{0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1}},
|
||||
{0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
|
||||
CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
|
||||
CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
|
||||
{0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
|
||||
@ -32,6 +52,9 @@ static struct serdes_config serdes1_cfg_tbl[] = {
|
||||
CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
|
||||
{0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
|
||||
CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
|
||||
{0x2F, {AURORA, AURORA,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x30, {AURORA, AURORA,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1}},
|
||||
@ -44,18 +67,38 @@ static struct serdes_config serdes1_cfg_tbl[] = {
|
||||
{0x34, {AURORA, AURORA,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1}},
|
||||
{0x39, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x3A, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x3C, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x3D, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1}},
|
||||
{0x5C, {AURORA, AURORA,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{0x5D, {AURORA, AURORA,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
CPRI4, CPRI3, CPRI2, CPRI1} },
|
||||
{}
|
||||
};
|
||||
static struct serdes_config serdes2_cfg_tbl[] = {
|
||||
/* SerDes 2 */
|
||||
{0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
AURORA, AURORA, SRIO1, SRIO1} },
|
||||
{0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
AURORA, AURORA, SRIO1, SRIO1}},
|
||||
{0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
AURORA, AURORA, SRIO1, SRIO1}},
|
||||
{0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SRIO2, SRIO2,
|
||||
AURORA, AURORA, SRIO1, SRIO1} },
|
||||
{0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SRIO2, SRIO2,
|
||||
AURORA, AURORA, SRIO1, SRIO1}},
|
||||
@ -63,6 +106,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
|
||||
SRIO2, SRIO2,
|
||||
AURORA, AURORA,
|
||||
SRIO1, SRIO1}},
|
||||
{0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, AURORA,
|
||||
SRIO1, SRIO1, SRIO1, SRIO1} },
|
||||
{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, AURORA,
|
||||
SRIO1, SRIO1, SRIO1, SRIO1}},
|
||||
@ -75,18 +121,30 @@ static struct serdes_config serdes2_cfg_tbl[] = {
|
||||
{0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, AURORA,
|
||||
SRIO1, SRIO1, SRIO1, SRIO1}},
|
||||
{0x79, {SRIO2, SRIO2, SRIO2, SRIO2,
|
||||
SRIO1, SRIO1, SRIO1, SRIO1} },
|
||||
{0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
|
||||
SRIO1, SRIO1, SRIO1, SRIO1}},
|
||||
{0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SRIO2, SRIO2, AURORA, AURORA,
|
||||
XFI_FM1_MAC9, XFI_FM1_MAC10} },
|
||||
{0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SRIO2, SRIO2, AURORA, AURORA,
|
||||
XFI_FM1_MAC9, XFI_FM1_MAC10}},
|
||||
{0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SRIO2, SRIO2, AURORA, AURORA,
|
||||
XFI_FM1_MAC9, XFI_FM1_MAC10}},
|
||||
{0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SRIO2, SRIO2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
XFI_FM1_MAC9, XFI_FM1_MAC10} },
|
||||
{0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SRIO2, SRIO2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
XFI_FM1_MAC9, XFI_FM1_MAC10}},
|
||||
{0x8C, {SRIO2, SRIO2, SRIO2, SRIO2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
XFI_FM1_MAC9, XFI_FM1_MAC10} },
|
||||
{0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
XFI_FM1_MAC9, XFI_FM1_MAC10}},
|
||||
@ -101,6 +159,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
XAUI_FM1_MAC10, XAUI_FM1_MAC10,
|
||||
XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
|
||||
{0xB1, {PCIE1, PCIE1, PCIE1, PCIE1,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
XFI_FM1_MAC9, XFI_FM1_MAC10} },
|
||||
{0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
XFI_FM1_MAC9, XFI_FM1_MAC10}},
|
||||
|
||||
@ -229,6 +229,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
if (IS_SVR_REV(svr, 1, 0))
|
||||
puts("Work-around for Erratum A005871 enabled\n");
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A006475
|
||||
if (SVR_MAJ(get_svr()) == 1)
|
||||
puts("Work-around for Erratum A006475 enabled\n");
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A006384
|
||||
if (SVR_MAJ(get_svr()) == 1)
|
||||
puts("Work-around for Erratum A006384 enabled\n");
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
|
||||
/* This work-around is implemented in PBI, so just check for it */
|
||||
check_erratum_a4849(svr);
|
||||
@ -264,6 +272,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
|
||||
(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
|
||||
puts("Work-around for Erratum I2C-A004447 enabled\n");
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
if (has_erratum_a006261())
|
||||
puts("Work-around for Erratum A006261 enabled\n");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -36,6 +36,54 @@
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
|
||||
|
||||
/* Increase Disconnect Threshold by 50mV */
|
||||
xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
|
||||
INC_DCNT_THRESHOLD_50MV;
|
||||
/* Enable programming of USB High speed Disconnect threshold */
|
||||
xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
|
||||
out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
|
||||
|
||||
xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
|
||||
/* Increase Disconnect Threshold by 50mV */
|
||||
xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
|
||||
INC_DCNT_THRESHOLD_50MV;
|
||||
/* Enable programming of USB High speed Disconnect threshold */
|
||||
xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
|
||||
out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
|
||||
#else
|
||||
|
||||
u32 temp = 0;
|
||||
u32 status = in_be32(&usb_phy->status1);
|
||||
|
||||
u32 squelch_prog_rd_0_2 =
|
||||
(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
|
||||
& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
|
||||
|
||||
u32 squelch_prog_rd_3_5 =
|
||||
(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
|
||||
& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
|
||||
|
||||
setbits_be32(&usb_phy->config1,
|
||||
CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
|
||||
setbits_be32(&usb_phy->config2,
|
||||
CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
|
||||
|
||||
temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
|
||||
out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
|
||||
|
||||
temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
|
||||
out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_QE
|
||||
extern qe_iop_conf_t qe_iop_conf_tab[];
|
||||
extern void qe_config_iopin(u8 port, u8 pin, int dir,
|
||||
@ -625,6 +673,10 @@ skip_l2:
|
||||
{
|
||||
struct ccsr_usb_phy __iomem *usb_phy1 =
|
||||
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
if (has_erratum_a006261())
|
||||
fsl_erratum_a006261_workaround(usb_phy1);
|
||||
#endif
|
||||
out_be32(&usb_phy1->usb_enable_override,
|
||||
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
|
||||
}
|
||||
@ -633,6 +685,10 @@ skip_l2:
|
||||
{
|
||||
struct ccsr_usb_phy __iomem *usb_phy2 =
|
||||
(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
if (has_erratum_a006261())
|
||||
fsl_erratum_a006261_workaround(usb_phy2);
|
||||
#endif
|
||||
out_be32(&usb_phy2->usb_enable_override,
|
||||
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
|
||||
}
|
||||
@ -672,8 +728,14 @@ skip_l2:
|
||||
CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
|
||||
setbits_be32(&usb_phy->port2.pwrfltcfg,
|
||||
CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
if (has_erratum_a006261())
|
||||
fsl_erratum_a006261_workaround(usb_phy);
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
|
||||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
fman_enet_init();
|
||||
#endif
|
||||
|
||||
@ -49,7 +49,6 @@
|
||||
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
|
||||
} while (0)
|
||||
|
||||
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||
static void update_rdcc(void)
|
||||
{
|
||||
u32 val;
|
||||
@ -72,7 +71,6 @@ static void update_rdcc(void)
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_440)
|
||||
/*
|
||||
@ -101,7 +99,6 @@ void dcbz_area(u32 start_address, u32 num_bytes);
|
||||
|
||||
#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
|
||||
|
||||
#if !defined(CONFIG_NAND_SPL)
|
||||
/*-----------------------------------------------------------------------------+
|
||||
* sdram_memsize
|
||||
*-----------------------------------------------------------------------------*/
|
||||
@ -217,7 +214,6 @@ void board_add_ram_info(int use_default)
|
||||
val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
|
||||
printf(", CL%d)", val);
|
||||
}
|
||||
#endif /* !CONFIG_NAND_SPL */
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
|
||||
@ -2843,16 +2839,6 @@ static void test(void)
|
||||
*---------------------------------------------------------------------------*/
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
/*
|
||||
* Only run this SDRAM init code once. For NAND booting
|
||||
* targets like Kilauea, we call initdram() early from the
|
||||
* 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
|
||||
* Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
|
||||
* which calls initdram() again. This time the controller
|
||||
* mustn't be reconfigured again since we're already running
|
||||
* from SDRAM.
|
||||
*/
|
||||
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||
unsigned long val;
|
||||
|
||||
#if defined(CONFIG_440)
|
||||
@ -2969,12 +2955,10 @@ phys_size_t initdram(int board_type)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
/*------------------------------------------------------------------
|
||||
| DQS calibration.
|
||||
+-----------------------------------------------------------------*/
|
||||
DQS_autocalibration();
|
||||
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
|
||||
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
|
||||
|
||||
/*
|
||||
@ -3009,13 +2993,10 @@ phys_size_t initdram(int board_type)
|
||||
set_mcsr(get_mcsr());
|
||||
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
|
||||
|
||||
#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
|
||||
|
||||
return (CONFIG_SYS_MBYTES_SDRAM << 20);
|
||||
}
|
||||
#endif /* CONFIG_SPD_EEPROM */
|
||||
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#if defined(CONFIG_440)
|
||||
u32 mfdcr_any(u32 dcr)
|
||||
{
|
||||
@ -3062,7 +3043,6 @@ void mtdcr_any(u32 dcr, u32 val)
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_440) */
|
||||
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
|
||||
|
||||
inline void ppc4xx_ibm_ddr2_register_dump(void)
|
||||
{
|
||||
|
||||
@ -27,12 +27,6 @@
|
||||
|
||||
#include "ecc.h"
|
||||
|
||||
/*
|
||||
* Only compile the DDR auto-calibration code for NOR boot and
|
||||
* not for NAND boot (NAND SPL and NAND U-Boot - NUB)
|
||||
*/
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
|
||||
#define MAXBXCF 4
|
||||
#define SDRAM_RXBAS_SHIFT_1M 20
|
||||
|
||||
@ -1231,9 +1225,3 @@ u32 DQS_autocalibration(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
|
||||
u32 DQS_autocalibration(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
|
||||
|
||||
@ -14,11 +14,7 @@ obj-y += kgdb.o
|
||||
|
||||
obj-y += 40x_spd_sdram.o
|
||||
|
||||
ifndef CONFIG_NAND_SPL
|
||||
ifndef CONFIG_NAND_U_BOOT
|
||||
obj-y += 44x_spd_ddr.o
|
||||
endif
|
||||
endif
|
||||
obj-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
|
||||
obj-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o
|
||||
obj-y += 4xx_pci.o
|
||||
|
||||
@ -7,8 +7,8 @@
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_4xx -mstring -msoft-float
|
||||
|
||||
cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
|
||||
is440:=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg))
|
||||
cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
|
||||
is440:=$(shell grep CONFIG_440 $(srctree)/include/$(cfg))
|
||||
|
||||
ifneq (,$(findstring CONFIG_440,$(is440)))
|
||||
PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440
|
||||
|
||||
@ -182,16 +182,13 @@
|
||||
|
||||
|
||||
.extern ext_bus_cntlr_init
|
||||
#ifdef CONFIG_NAND_U_BOOT
|
||||
.extern reconfig_tlb0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Set up GOT: Global Offset Table
|
||||
*
|
||||
* Use r12 to access the GOT
|
||||
*/
|
||||
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
START_GOT
|
||||
GOT_ENTRY(_GOT2_TABLE_)
|
||||
GOT_ENTRY(_FIXUP_TABLE_)
|
||||
@ -205,22 +202,7 @@
|
||||
GOT_ENTRY(__bss_end)
|
||||
GOT_ENTRY(__bss_start)
|
||||
END_GOT
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
|
||||
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
|
||||
!defined(CONFIG_SPL_BUILD)
|
||||
/*
|
||||
* NAND U-Boot image is started from offset 0
|
||||
*/
|
||||
.text
|
||||
#if defined(CONFIG_440)
|
||||
bl reconfig_tlb0
|
||||
#endif
|
||||
GET_GOT
|
||||
bl cpu_init_f /* run low-level CPU init code (from Flash) */
|
||||
bl board_init_f
|
||||
/* NOTREACHED - board_init_f() does not return */
|
||||
#endif
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
|
||||
/*
|
||||
@ -255,9 +237,7 @@
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_440)
|
||||
#if !defined(CONFIG_NAND_SPL)
|
||||
.section .bootpg,"ax"
|
||||
#endif
|
||||
.globl _start_440
|
||||
|
||||
/**************************************************************************/
|
||||
@ -511,7 +491,7 @@ tlbnx2: addi r4,r4,1 /* Next TLB */
|
||||
* r3 - 1st arg to board_init(): IMMP pointer
|
||||
* r4 - 2nd arg to board_init(): boot flag
|
||||
*/
|
||||
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
.text
|
||||
.long 0x27051956 /* U-Boot Magic Number */
|
||||
.globl version_string
|
||||
@ -777,9 +757,6 @@ _start:
|
||||
stwu r1,-8(r1) /* Save back chain and move SP */
|
||||
stw r0,+12(r1) /* Save return addr (underflow vect) */
|
||||
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
bl nand_boot_common /* will not return */
|
||||
#else
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
GET_GOT
|
||||
#endif
|
||||
@ -787,7 +764,6 @@ _start:
|
||||
bl cpu_init_f /* run low-level CPU init code (from Flash) */
|
||||
bl board_init_f
|
||||
/* NOTREACHED - board_init_f() does not return */
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_440 */
|
||||
|
||||
@ -1050,9 +1026,6 @@ _start:
|
||||
stw r0, +12(r1) /* Save return addr (underflow vect) */
|
||||
#endif /* CONFIG_SYS_INIT_DCACHE_CS */
|
||||
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
bl nand_boot_common /* will not return */
|
||||
#else
|
||||
GET_GOT /* initialize GOT access */
|
||||
|
||||
bl cpu_init_f /* run low-level CPU init code (from Flash) */
|
||||
@ -1060,13 +1033,11 @@ _start:
|
||||
bl board_init_f /* run first part of init code (from Flash) */
|
||||
/* NOTREACHED - board_init_f() does not return */
|
||||
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
|
||||
#endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
|
||||
/*----------------------------------------------------------------------- */
|
||||
|
||||
|
||||
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
/*
|
||||
* This code finishes saving the registers to the exception frame
|
||||
* and jumps to the appropriate handler for the exception.
|
||||
@ -1632,7 +1603,7 @@ __440_msr_continue:
|
||||
blr
|
||||
function_epilog(dcbz_area)
|
||||
#endif /* CONFIG_440 */
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/* Function: in8 */
|
||||
@ -1981,75 +1952,3 @@ pll_wait:
|
||||
blr
|
||||
function_epilog(mftlb1)
|
||||
#endif /* CONFIG_440 */
|
||||
|
||||
#if defined(CONFIG_NAND_SPL)
|
||||
/*
|
||||
* void nand_boot_relocate(dst, src, bytes)
|
||||
*
|
||||
* r3 = Destination address to copy code to (in SDRAM)
|
||||
* r4 = Source address to copy code from
|
||||
* r5 = size to copy in bytes
|
||||
*/
|
||||
nand_boot_relocate:
|
||||
mr r6,r3
|
||||
mr r7,r4
|
||||
mflr r8
|
||||
|
||||
/*
|
||||
* Copy SPL from icache into SDRAM
|
||||
*/
|
||||
subi r3,r3,4
|
||||
subi r4,r4,4
|
||||
srwi r5,r5,2
|
||||
mtctr r5
|
||||
..spl_loop:
|
||||
lwzu r0,4(r4)
|
||||
stwu r0,4(r3)
|
||||
bdnz ..spl_loop
|
||||
|
||||
/*
|
||||
* Calculate "corrected" link register, so that we "continue"
|
||||
* in execution in destination range
|
||||
*/
|
||||
sub r3,r7,r6 /* r3 = src - dst */
|
||||
sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
|
||||
mtlr r8
|
||||
blr
|
||||
|
||||
nand_boot_common:
|
||||
/*
|
||||
* First initialize SDRAM. It has to be available *before* calling
|
||||
* nand_boot().
|
||||
*/
|
||||
lis r3,CONFIG_SYS_SDRAM_BASE@h
|
||||
ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
|
||||
bl initdram
|
||||
|
||||
/*
|
||||
* Now copy the 4k SPL code into SDRAM and continue execution
|
||||
* from there.
|
||||
*/
|
||||
lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
|
||||
ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
|
||||
lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
|
||||
ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
|
||||
lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
|
||||
ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
|
||||
bl nand_boot_relocate
|
||||
|
||||
/*
|
||||
* We're running from SDRAM now!!!
|
||||
*
|
||||
* It is necessary for 4xx systems to relocate from running at
|
||||
* the original location (0xfffffxxx) to somewhere else (SDRAM
|
||||
* preferably). This is because CS0 needs to be reconfigured for
|
||||
* NAND access. And we can't reconfigure this CS when currently
|
||||
* "running" from it.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Finally call nand_boot() to load main NAND U-Boot image from
|
||||
* NAND and jump to it.
|
||||
*/
|
||||
bl nand_boot /* will not return */
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
|
||||
@ -847,104 +847,7 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list)
|
||||
* Virtual Root Hub
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
/* Device descriptor */
|
||||
static __u8 root_hub_dev_des[] =
|
||||
{
|
||||
0x12, /* __u8 bLength; */
|
||||
0x01, /* __u8 bDescriptorType; Device */
|
||||
0x10, /* __u16 bcdUSB; v1.1 */
|
||||
0x01,
|
||||
0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
|
||||
0x00, /* __u8 bDeviceSubClass; */
|
||||
0x00, /* __u8 bDeviceProtocol; */
|
||||
0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
|
||||
0x00, /* __u16 idVendor; */
|
||||
0x00,
|
||||
0x00, /* __u16 idProduct; */
|
||||
0x00,
|
||||
0x00, /* __u16 bcdDevice; */
|
||||
0x00,
|
||||
0x00, /* __u8 iManufacturer; */
|
||||
0x01, /* __u8 iProduct; */
|
||||
0x00, /* __u8 iSerialNumber; */
|
||||
0x01 /* __u8 bNumConfigurations; */
|
||||
};
|
||||
|
||||
|
||||
/* Configuration descriptor */
|
||||
static __u8 root_hub_config_des[] =
|
||||
{
|
||||
0x09, /* __u8 bLength; */
|
||||
0x02, /* __u8 bDescriptorType; Configuration */
|
||||
0x19, /* __u16 wTotalLength; */
|
||||
0x00,
|
||||
0x01, /* __u8 bNumInterfaces; */
|
||||
0x01, /* __u8 bConfigurationValue; */
|
||||
0x00, /* __u8 iConfiguration; */
|
||||
0x40, /* __u8 bmAttributes;
|
||||
Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
|
||||
0x00, /* __u8 MaxPower; */
|
||||
|
||||
/* interface */
|
||||
0x09, /* __u8 if_bLength; */
|
||||
0x04, /* __u8 if_bDescriptorType; Interface */
|
||||
0x00, /* __u8 if_bInterfaceNumber; */
|
||||
0x00, /* __u8 if_bAlternateSetting; */
|
||||
0x01, /* __u8 if_bNumEndpoints; */
|
||||
0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
|
||||
0x00, /* __u8 if_bInterfaceSubClass; */
|
||||
0x00, /* __u8 if_bInterfaceProtocol; */
|
||||
0x00, /* __u8 if_iInterface; */
|
||||
|
||||
/* endpoint */
|
||||
0x07, /* __u8 ep_bLength; */
|
||||
0x05, /* __u8 ep_bDescriptorType; Endpoint */
|
||||
0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
|
||||
0x03, /* __u8 ep_bmAttributes; Interrupt */
|
||||
0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
|
||||
0x00,
|
||||
0xff /* __u8 ep_bInterval; 255 ms */
|
||||
};
|
||||
|
||||
static unsigned char root_hub_str_index0[] =
|
||||
{
|
||||
0x04, /* __u8 bLength; */
|
||||
0x03, /* __u8 bDescriptorType; String-descriptor */
|
||||
0x09, /* __u8 lang ID */
|
||||
0x04, /* __u8 lang ID */
|
||||
};
|
||||
|
||||
static unsigned char root_hub_str_index1[] =
|
||||
{
|
||||
28, /* __u8 bLength; */
|
||||
0x03, /* __u8 bDescriptorType; String-descriptor */
|
||||
'O', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'H', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'C', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'I', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
' ', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'R', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'o', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'o', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
't', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
' ', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'H', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'u', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
'b', /* __u8 Unicode */
|
||||
0, /* __u8 Unicode */
|
||||
};
|
||||
#include <usbroothubdes.h>
|
||||
|
||||
/* Hub class-specific descriptor is constructed dynamically */
|
||||
|
||||
|
||||
@ -154,6 +154,7 @@
|
||||
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
|
||||
#define CONFIG_ESDHC_HC_BLK_ADDR
|
||||
|
||||
@ -386,6 +387,7 @@
|
||||
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004849
|
||||
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
|
||||
|
||||
#elif defined(CONFIG_PPC_P3041)
|
||||
@ -424,6 +426,7 @@
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004849
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005812
|
||||
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
|
||||
|
||||
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
|
||||
@ -507,6 +510,7 @@
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
||||
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
|
||||
|
||||
#elif defined(CONFIG_PPC_P5040)
|
||||
@ -538,6 +542,7 @@
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004699
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004510
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005812
|
||||
|
||||
@ -633,6 +638,7 @@
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004468
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A_004934
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005871
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006379
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006593
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
@ -662,11 +668,14 @@
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005871
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006379
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006593
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006475
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006384
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
|
||||
#ifdef CONFIG_PPC_B4860
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 6
|
||||
@ -679,6 +688,7 @@
|
||||
#define CONFIG_SYS_FSL_SRIO_LIODN
|
||||
#else
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
|
||||
@ -722,6 +732,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
|
||||
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
|
||||
@ -26,4 +26,38 @@ static inline bool has_erratum_a006379(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
static inline bool has_erratum_a006261(void)
|
||||
{
|
||||
u32 svr = get_svr();
|
||||
u32 soc = SVR_SOC_VER(svr);
|
||||
|
||||
switch (soc) {
|
||||
case SVR_P1010:
|
||||
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
|
||||
case SVR_P2041:
|
||||
case SVR_P2040:
|
||||
return IS_SVR_REV(svr, 1, 0) ||
|
||||
IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
|
||||
case SVR_P3041:
|
||||
return IS_SVR_REV(svr, 1, 0) ||
|
||||
IS_SVR_REV(svr, 1, 1) ||
|
||||
IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
|
||||
case SVR_P5010:
|
||||
case SVR_P5020:
|
||||
case SVR_P5021:
|
||||
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
|
||||
case SVR_T4240:
|
||||
case SVR_T4160:
|
||||
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
|
||||
case SVR_T1040:
|
||||
return IS_SVR_REV(svr, 1, 0);
|
||||
case SVR_P5040:
|
||||
return IS_SVR_REV(svr, 1, 0);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -1722,6 +1722,9 @@ typedef struct ccsr_gur {
|
||||
u32 rstrqpblsr; /* Reset request preboot loader status */
|
||||
u8 res11[8];
|
||||
u32 rstrqmr1; /* Reset request mask */
|
||||
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
|
||||
#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
|
||||
#endif
|
||||
u8 res12[4];
|
||||
u32 rstrqsr1; /* Reset request status */
|
||||
u8 res13[4];
|
||||
@ -1770,6 +1773,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
|
||||
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
|
||||
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000
|
||||
#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
|
||||
#define PXCKEN_MASK 0x80000000
|
||||
#define PXCK_MASK 0x00FF0000
|
||||
#define PXCK_BITS_START 16
|
||||
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
|
||||
@ -2492,6 +2499,7 @@ typedef struct serdes_corenet {
|
||||
#define SRDS_RSTCTL_SDEN 0x00000020
|
||||
#define SRDS_RSTCTL_SDRST_B 0x00000040
|
||||
#define SRDS_RSTCTL_PLLRST_B 0x00000080
|
||||
#define SRDS_RSTCTL_RSTERR_SHIFT 29
|
||||
u32 pllcr0; /* PLL Control Register 0 */
|
||||
#define SRDS_PLLCR0_POFF 0x80000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
|
||||
@ -2501,6 +2509,7 @@ typedef struct serdes_corenet {
|
||||
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
|
||||
#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
|
||||
@ -2508,9 +2517,22 @@ typedef struct serdes_corenet {
|
||||
#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
|
||||
#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
|
||||
#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
|
||||
u32 pllcr1; /* PLL Control Register 1 */
|
||||
#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
|
||||
u32 res_0c; /* 0x00c */
|
||||
#define SRDS_PLLCR1_BCAP_EN 0x20000000
|
||||
#define SRDS_PLLCR1_BCAP_OVD 0x10000000
|
||||
#define SRDS_PLLCR1_PLL_FCAP 0x001F8000
|
||||
#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
|
||||
#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
|
||||
#define SRDS_PLLCR1_BYP_CAL 0x02000000
|
||||
u32 pllsr2; /* At 0x00c, PLL Status Register 2 */
|
||||
#define SRDS_PLLSR2_BCAP_EN 0x00800000
|
||||
#define SRDS_PLLSR2_BCAP_EN_SHIFT 23
|
||||
#define SRDS_PLLSR2_FCAP 0x003F0000
|
||||
#define SRDS_PLLSR2_FCAP_SHIFT 16
|
||||
#define SRDS_PLLSR2_DCBIAS 0x000F0000
|
||||
#define SRDS_PLLSR2_DCBIAS_SHIFT 16
|
||||
u32 pllcr3;
|
||||
u32 pllcr4;
|
||||
u8 res_18[0x20-0x18];
|
||||
@ -2845,6 +2867,7 @@ struct ccsr_pman {
|
||||
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
|
||||
#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
|
||||
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
|
||||
#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
|
||||
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
|
||||
#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
|
||||
#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
|
||||
@ -2962,6 +2985,10 @@ struct ccsr_pman {
|
||||
|
||||
#define CONFIG_SYS_FSL_CPC_ADDR \
|
||||
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_SCFG_ADDR \
|
||||
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
|
||||
#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
|
||||
(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
|
||||
#define CONFIG_SYS_FSL_QMAN_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
|
||||
#define CONFIG_SYS_FSL_BMAN_ADDR \
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user