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AT91CAP9ADK: Handle 8 or 16 bit NAND
The Atmel boards can handle 8 or 16 bit NAND memories. This patch makes the support configurable in the board config header file (CFG_NAND_DBW_8 or CFG_NAND_DBW_16). Signed-off-by: Stelian Pop <stelian@popies.net> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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@ -116,7 +116,12 @@ static void at91cap9_nand_hw_init(void)
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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AT91_SMC_DBW_8 | AT91_SMC_TDF_(1));
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#ifdef CFG_NAND_DBW_16
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AT91_SMC_DBW_16 |
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#else /* CFG_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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#endif
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AT91_SMC_TDF_(1));
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at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
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@ -252,7 +257,6 @@ int board_init(void)
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#ifdef CONFIG_USB_OHCI_NEW
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at91cap9_uhp_hw_init();
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#endif
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return 0;
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}
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@ -63,6 +63,9 @@ static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
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int board_nand_init(struct nand_chip *nand)
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{
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nand->eccmode = NAND_ECC_SOFT;
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#ifdef CFG_NAND_DBW_16
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nand->options = NAND_BUSWIDTH_16;
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#endif
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nand->hwcontrol = at91cap9adk_nand_hwcontrol;
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nand->chip_delay = 20;
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@ -110,6 +110,7 @@
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#define NAND_MAX_CHIPS 1
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#define CFG_MAX_NAND_DEVICE 1
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#define CFG_NAND_BASE 0x40000000
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#define CFG_NAND_DBW_8 1
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/* Ethernet */
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#define CONFIG_MACB 1
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