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tegra: clock: Avoid a divide-by-zero error
The clock fix-up for tegra is still present in the code. It causes a
divide-by-zero bug after relocation when chain-loading U-Boot from
coreboot. Fix this by adding a check.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 7468676
(ARM: tegra: fix clock_get_periph_rate() for UART clocks)
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@ -339,8 +339,11 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
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* return value doesn't help. In summary this clock driver is
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* quite broken but I'm afraid I have no idea how to fix it
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* without completely replacing it.
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*
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* Be careful to avoid a divide by zero error.
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*/
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div -= 2;
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if (div >= 1)
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div -= 2;
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break;
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#endif
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default:
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