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ARM: rmobile: Remove Watchdog and CPG settings on Gen3
This code is unnecessary, because these registers are set by the initial program loader (IPL). Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
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@ -26,21 +26,8 @@
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DECLARE_GLOBAL_DATA_PTR;
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#define CPGWPCR 0xE6150904
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#define CPGWPR 0xE6150900
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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writel(0x5A5AFFFF, CPGWPR);
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writel(0xA5A50000, CPGWPCR);
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}
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#define GSX_MSTP112 BIT(12) /* 3DG */
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@ -27,21 +27,8 @@
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DECLARE_GLOBAL_DATA_PTR;
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#define CPGWPCR 0xE6150904
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#define CPGWPR 0xE6150900
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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writel(0x5A5AFFFF, CPGWPR);
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writel(0xA5A50000, CPGWPCR);
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}
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#define GSX_MSTP112 BIT(12) /* 3DG */
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@ -26,21 +26,8 @@
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DECLARE_GLOBAL_DATA_PTR;
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#define CPGWPCR 0xE6150904
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#define CPGWPR 0xE6150900
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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writel(0x5A5AFFFF, CPGWPR);
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writel(0xA5A50000, CPGWPCR);
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}
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#define GSX_MSTP112 BIT(12) /* 3DG */
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