mirror of
https://github.com/u-boot/u-boot.git
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Extend ATI Radeon driver to support more video modes
Adds ATI Radeon 9200 support for 1280x1024, 1024x768, 800x600, 640x480 at 24, 16 and 8 bpp. Signed-off-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Anatolij Gustschin
Wolfgang Denk
parent
4124382de0
commit
1b8607e1f7
@ -44,6 +44,7 @@
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#include <asm/io.h>
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#include <malloc.h>
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#include <video_fb.h>
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#include "videomodes.h"
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#include <radeon.h>
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#include "ati_ids.h"
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@ -65,6 +66,21 @@
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#define MAX_MAPPED_VRAM (2048*2048*4)
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#define MIN_MAPPED_VRAM (1024*768*1)
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#define RADEON_BUFFER_ALIGN 0x00000fff
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#define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \
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& ~RADEON_BUFFER_ALIGN) - 1)
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#define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \
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((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16))
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#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \
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(((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16))
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#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \
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(((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16))
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#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \
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((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16))
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#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \
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((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16))
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/*#define PCI_VENDOR_ID_ATI*/
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#define PCI_CHIP_RV280_5960 0x5960
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#define PCI_CHIP_RV280_5961 0x5961
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@ -350,6 +366,204 @@ void radeon_setmode(void)
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radeon_write_pll_regs(rinfo, mode);
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}
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static void set_pal(void)
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{
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int idx, val = 0;
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for (idx = 0; idx < 256; idx++) {
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OUTREG8(PALETTE_INDEX, idx);
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OUTREG(PALETTE_DATA, val);
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val += 0x00010101;
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}
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}
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void radeon_setmode_9200(int vesa_idx, int bpp)
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{
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struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
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mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN;
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mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON;
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mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN;
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mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN;
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switch (bpp) {
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case 24:
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mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */
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#if defined(__BIG_ENDIAN)
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mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
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mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
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#endif
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break;
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case 16:
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mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */
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#if defined(__BIG_ENDIAN)
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mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
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mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
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#endif
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break;
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default:
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mode->crtc_gen_cntl |= 0x2 << 8; /* palette */
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mode->surface_cntl = 0x00000000;
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break;
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}
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switch (vesa_idx) {
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case RES_MODE_1280x1024:
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mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280);
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mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024);
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mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3);
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#if defined(CONFIG_RADEON_VREFRESH_75HZ)
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mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18);
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mode->ppll_div_3 = 0x00010078;
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#else /* default @ 60 Hz */
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mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14);
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mode->ppll_div_3 = 0x00010060;
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#endif
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/*
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* for this mode pitch expands to the same value for 32, 16 and 8 bpp,
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* so we set it here once only.
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*/
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mode->crtc_pitch = RADEON_CRT_PITCH(1280,32);
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switch (bpp) {
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case 24:
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mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16);
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mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32);
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break;
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case 16:
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mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16);
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mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16);
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break;
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default: /* 8 bpp */
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mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16);
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mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8);
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break;
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}
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break;
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case RES_MODE_1024x768:
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#if defined(CONFIG_RADEON_VREFRESH_75HZ)
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mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024);
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mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12);
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mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768);
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mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3);
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mode->ppll_div_3 = 0x0002008c;
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#else /* @ 60 Hz */
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mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024);
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mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL;
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mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768);
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mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL;
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mode->ppll_div_3 = 0x00020074;
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#endif
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/* also same pitch value for 32, 16 and 8 bpp */
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mode->crtc_pitch = RADEON_CRT_PITCH(1024,32);
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switch (bpp) {
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case 24:
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mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16);
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mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32);
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break;
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case 16:
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mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16);
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mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16);
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break;
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default: /* 8 bpp */
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mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
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mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8);
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break;
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}
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break;
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case RES_MODE_800x600:
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mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800);
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#if defined(CONFIG_RADEON_VREFRESH_75HZ)
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mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10);
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mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600);
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mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3);
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mode->ppll_div_3 = 0x000300b0;
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#else /* @ 60 Hz */
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mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16);
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mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600);
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mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4);
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mode->ppll_div_3 = 0x0003008e;
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#endif
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switch (bpp) {
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case 24:
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mode->crtc_pitch = RADEON_CRT_PITCH(832,32);
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mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16);
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mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32);
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break;
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case 16:
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mode->crtc_pitch = RADEON_CRT_PITCH(896,16);
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mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16);
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mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16);
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break;
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default: /* 8 bpp */
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mode->crtc_pitch = RADEON_CRT_PITCH(1024,8);
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mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
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mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8);
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break;
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}
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break;
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default: /* RES_MODE_640x480 */
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#if defined(CONFIG_RADEON_VREFRESH_75HZ)
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mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640);
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mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL;
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mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480);
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mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL;
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mode->ppll_div_3 = 0x00030070;
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#else /* @ 60 Hz */
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mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640);
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mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL;
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mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480);
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mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL;
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mode->ppll_div_3 = 0x00030059;
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#endif
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/* also same pitch value for 32, 16 and 8 bpp */
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mode->crtc_pitch = RADEON_CRT_PITCH(640,32);
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switch (bpp) {
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case 24:
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mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16);
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mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32);
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break;
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case 16:
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mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16);
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mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16);
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break;
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default: /* 8 bpp */
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mode->crtc_offset_cntl = 0x00000000;
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break;
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}
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break;
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}
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OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
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OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
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(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
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OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
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OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
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OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
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OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
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OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
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OUTREG(CRTC_OFFSET, 0);
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OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl);
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OUTREG(CRTC_PITCH, mode->crtc_pitch);
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OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
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mode->clk_cntl_index = 0x300;
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mode->ppll_ref_div = 0xc;
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radeon_write_pll_regs(rinfo, mode);
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OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
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~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
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OUTREG(SURFACE0_INFO, mode->surf_info[0]);
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OUTREG(SURFACE0_LOWER_BOUND, 0);
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OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]);
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OUTREG(SURFACE_CNTL, mode->surface_cntl);
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if (bpp > 8)
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set_pal();
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free(mode);
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}
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#include "../bios_emulator/include/biosemu.h"
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extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp);
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@ -421,29 +635,101 @@ GraphicDevice ctfb;
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void *video_hw_init(void)
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{
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GraphicDevice *pGD = (GraphicDevice *) & ctfb;
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int i;
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u32 *vm;
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char *penv;
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unsigned long t1, hsynch, vsynch;
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int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
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struct ctfb_res_modes *res_mode;
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struct ctfb_res_modes var_mode;
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rinfo = malloc(sizeof(struct radeonfb_info));
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printf("Video: ");
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if(radeon_probe(rinfo)) {
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printf("No radeon video card found!\n");
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return NULL;
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}
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tmp = 0;
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videomode = CFG_DEFAULT_VIDEO_MODE;
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/* get video mode via environment */
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if ((penv = getenv ("videomode")) != NULL) {
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/* deceide if it is a string */
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if (penv[0] <= '9') {
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videomode = (int) simple_strtoul (penv, NULL, 16);
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tmp = 1;
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}
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} else {
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tmp = 1;
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}
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if (tmp) {
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/* parameter are vesa modes */
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/* search params */
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for (i = 0; i < VESA_MODES_COUNT; i++) {
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if (vesa_modes[i].vesanr == videomode)
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break;
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}
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if (i == VESA_MODES_COUNT) {
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printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE);
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i = 0;
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}
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res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex];
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bits_per_pixel = vesa_modes[i].bits_per_pixel;
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vesa_idx = vesa_modes[i].resindex;
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} else {
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res_mode = (struct ctfb_res_modes *) &var_mode;
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bits_per_pixel = video_get_params (res_mode, penv);
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}
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/* calculate hsynch and vsynch freq (info only) */
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t1 = (res_mode->left_margin + res_mode->xres +
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res_mode->right_margin + res_mode->hsync_len) / 8;
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t1 *= 8;
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t1 *= res_mode->pixclock;
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t1 /= 1000;
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hsynch = 1000000000L / t1;
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t1 *= (res_mode->upper_margin + res_mode->yres +
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res_mode->lower_margin + res_mode->vsync_len);
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t1 /= 1000;
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vsynch = 1000000000L / t1;
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/* fill in Graphic device struct */
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sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", 640,
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480, 16, (1000 / 1000),
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(2000 / 1000));
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sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
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res_mode->yres, bits_per_pixel, (hsynch / 1000),
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(vsynch / 1000));
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printf ("%s\n", pGD->modeIdent);
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pGD->winSizeX = res_mode->xres;
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pGD->winSizeY = res_mode->yres;
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pGD->plnSizeX = res_mode->xres;
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pGD->plnSizeY = res_mode->yres;
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pGD->winSizeX = 640;
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pGD->winSizeY = 480;
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pGD->plnSizeX = 640;
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pGD->plnSizeY = 480;
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pGD->gdfBytesPP = 1;
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pGD->gdfIndex = GDF__8BIT_INDEX;
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switch (bits_per_pixel) {
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case 24:
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pGD->gdfBytesPP = 4;
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pGD->gdfIndex = GDF_32BIT_X888RGB;
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if (res_mode->xres == 800) {
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pGD->winSizeX = 832;
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pGD->plnSizeX = 832;
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}
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break;
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case 16:
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pGD->gdfBytesPP = 2;
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pGD->gdfIndex = GDF_16BIT_565RGB;
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if (res_mode->xres == 800) {
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pGD->winSizeX = 896;
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pGD->plnSizeX = 896;
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}
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break;
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default:
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if (res_mode->xres == 800) {
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pGD->winSizeX = 1024;
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pGD->plnSizeX = 1024;
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}
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pGD->gdfBytesPP = 1;
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pGD->gdfIndex = GDF__8BIT_INDEX;
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break;
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}
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pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS;
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pGD->pciBase = rinfo->fb_base_phys;
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@ -464,14 +750,17 @@ void *video_hw_init(void)
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pGD->cprBase = rinfo->fb_base_phys; /* Dummy */
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/* set up Hardware */
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/* Clear video memory */
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i = pGD->memSize / 4;
|
||||
/* Clear video memory (only visible screen area) */
|
||||
i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
|
||||
vm = (unsigned int *) pGD->pciBase;
|
||||
while (i--)
|
||||
*vm++ = 0;
|
||||
/*SetDrawingEngine (bits_per_pixel);*/
|
||||
|
||||
radeon_setmode();
|
||||
if (rinfo->family == CHIP_FAMILY_RV280)
|
||||
radeon_setmode_9200(vesa_idx, bits_per_pixel);
|
||||
else
|
||||
radeon_setmode();
|
||||
|
||||
return ((void *) pGD);
|
||||
}
|
||||
|
||||
@ -154,8 +154,10 @@
|
||||
#define PALETTE_30_DATA 0x00B8
|
||||
#define CRTC_H_TOTAL_DISP 0x0200
|
||||
#define CRTC_H_SYNC_STRT_WID 0x0204
|
||||
#define CRTC_H_SYNC_POL (1 << 23)
|
||||
#define CRTC_V_TOTAL_DISP 0x0208
|
||||
#define CRTC_V_SYNC_STRT_WID 0x020C
|
||||
#define CRTC_V_SYNC_POL (1 << 23)
|
||||
#define CRTC_VLINE_CRNT_VLINE 0x0210
|
||||
#define CRTC_CRNT_FRAME 0x0214
|
||||
#define CRTC_GUI_TRIG_VLINE 0x0218
|
||||
@ -749,6 +751,8 @@
|
||||
#define NONSURF_AP1_SWP_16BPP (1 << 22)
|
||||
#define NONSURF_AP1_SWP_32BPP (1 << 23)
|
||||
|
||||
#define R200_SURF_TILE_COLOR_MACRO (1 << 16)
|
||||
|
||||
/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
|
||||
#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
|
||||
#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user