mirror of
https://github.com/u-boot/u-boot.git
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dm: clk: remove CLK() macro for clk_stm32h7
CLK() macro is a residue of a previously reworked patch, remove it. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
This commit is contained in:
Patrice Chotard
Tom Rini
parent
0c19efa7e1
commit
1b4ce69dc2
@ -195,13 +195,6 @@ struct clk_cfg {
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const char *name;
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};
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#define CLK(_gate_offset, _bit_idx, _name) \
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{ \
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.gate_offset = _gate_offset,\
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.gate_bit_idx = _bit_idx,\
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.name = _name,\
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}
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/*
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* the way all these entries are sorted in this array could seem
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* unlogical, but we are dependant of kernel DT_bindings,
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@ -210,114 +203,114 @@ struct clk_cfg {
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*/
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static const struct clk_cfg clk_map[] = {
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CLK(RCC_AHB3ENR, 31, "d1sram1"), /* peripheral clocks */
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CLK(RCC_AHB3ENR, 30, "itcm"),
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CLK(RCC_AHB3ENR, 29, "dtcm2"),
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CLK(RCC_AHB3ENR, 28, "dtcm1"),
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CLK(RCC_AHB3ENR, 8, "flitf"),
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CLK(RCC_AHB3ENR, 5, "jpgdec"),
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CLK(RCC_AHB3ENR, 4, "dma2d"),
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CLK(RCC_AHB3ENR, 0, "mdma"),
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CLK(RCC_AHB1ENR, 28, "usb2ulpi"),
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CLK(RCC_AHB1ENR, 17, "eth1rx"),
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CLK(RCC_AHB1ENR, 16, "eth1tx"),
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CLK(RCC_AHB1ENR, 15, "eth1mac"),
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CLK(RCC_AHB1ENR, 14, "art"),
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CLK(RCC_AHB1ENR, 26, "usb1ulpi"),
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CLK(RCC_AHB1ENR, 1, "dma2"),
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CLK(RCC_AHB1ENR, 0, "dma1"),
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CLK(RCC_AHB2ENR, 31, "d2sram3"),
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CLK(RCC_AHB2ENR, 30, "d2sram2"),
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CLK(RCC_AHB2ENR, 29, "d2sram1"),
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CLK(RCC_AHB2ENR, 5, "hash"),
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CLK(RCC_AHB2ENR, 4, "crypt"),
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CLK(RCC_AHB2ENR, 0, "camitf"),
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CLK(RCC_AHB4ENR, 28, "bkpram"),
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CLK(RCC_AHB4ENR, 25, "hsem"),
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CLK(RCC_AHB4ENR, 21, "bdma"),
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CLK(RCC_AHB4ENR, 19, "crc"),
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CLK(RCC_AHB4ENR, 10, "gpiok"),
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CLK(RCC_AHB4ENR, 9, "gpioj"),
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CLK(RCC_AHB4ENR, 8, "gpioi"),
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CLK(RCC_AHB4ENR, 7, "gpioh"),
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CLK(RCC_AHB4ENR, 6, "gpiog"),
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CLK(RCC_AHB4ENR, 5, "gpiof"),
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CLK(RCC_AHB4ENR, 4, "gpioe"),
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CLK(RCC_AHB4ENR, 3, "gpiod"),
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CLK(RCC_AHB4ENR, 2, "gpioc"),
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CLK(RCC_AHB4ENR, 1, "gpiob"),
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CLK(RCC_AHB4ENR, 0, "gpioa"),
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CLK(RCC_APB3ENR, 6, "wwdg1"),
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CLK(RCC_APB1LENR, 29, "dac12"),
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CLK(RCC_APB1LENR, 11, "wwdg2"),
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CLK(RCC_APB1LENR, 8, "tim14"),
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CLK(RCC_APB1LENR, 7, "tim13"),
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CLK(RCC_APB1LENR, 6, "tim12"),
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CLK(RCC_APB1LENR, 5, "tim7"),
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CLK(RCC_APB1LENR, 4, "tim6"),
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CLK(RCC_APB1LENR, 3, "tim5"),
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CLK(RCC_APB1LENR, 2, "tim4"),
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CLK(RCC_APB1LENR, 1, "tim3"),
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CLK(RCC_APB1LENR, 0, "tim2"),
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CLK(RCC_APB1HENR, 5, "mdios"),
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CLK(RCC_APB1HENR, 4, "opamp"),
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CLK(RCC_APB1HENR, 1, "crs"),
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CLK(RCC_APB2ENR, 18, "tim17"),
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CLK(RCC_APB2ENR, 17, "tim16"),
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CLK(RCC_APB2ENR, 16, "tim15"),
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CLK(RCC_APB2ENR, 1, "tim8"),
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CLK(RCC_APB2ENR, 0, "tim1"),
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CLK(RCC_APB4ENR, 26, "tmpsens"),
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CLK(RCC_APB4ENR, 16, "rtcapb"),
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CLK(RCC_APB4ENR, 15, "vref"),
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CLK(RCC_APB4ENR, 14, "comp12"),
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CLK(RCC_APB4ENR, 1, "syscfg"),
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CLK(RCC_AHB3ENR, 16, "sdmmc1"), /* kernel clocks */
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CLK(RCC_AHB3ENR, 14, "quadspi"),
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CLK(RCC_AHB3ENR, 12, "fmc"),
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CLK(RCC_AHB1ENR, 27, "usb2otg"),
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CLK(RCC_AHB1ENR, 25, "usb1otg"),
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CLK(RCC_AHB1ENR, 5, "adc12"),
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CLK(RCC_AHB2ENR, 9, "sdmmc2"),
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CLK(RCC_AHB2ENR, 6, "rng"),
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CLK(RCC_AHB4ENR, 24, "adc3"),
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CLK(RCC_APB3ENR, 4, "dsi"),
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CLK(RCC_APB3ENR, 3, "ltdc"),
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CLK(RCC_APB1LENR, 31, "usart8"),
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CLK(RCC_APB1LENR, 30, "usart7"),
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CLK(RCC_APB1LENR, 27, "hdmicec"),
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CLK(RCC_APB1LENR, 23, "i2c3"),
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CLK(RCC_APB1LENR, 22, "i2c2"),
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CLK(RCC_APB1LENR, 21, "i2c1"),
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CLK(RCC_APB1LENR, 20, "uart5"),
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CLK(RCC_APB1LENR, 19, "uart4"),
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CLK(RCC_APB1LENR, 18, "usart3"),
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CLK(RCC_APB1LENR, 17, "usart2"),
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CLK(RCC_APB1LENR, 16, "spdifrx"),
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CLK(RCC_APB1LENR, 15, "spi3"),
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CLK(RCC_APB1LENR, 14, "spi2"),
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CLK(RCC_APB1LENR, 9, "lptim1"),
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CLK(RCC_APB1HENR, 8, "fdcan"),
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CLK(RCC_APB1HENR, 2, "swp"),
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CLK(RCC_APB2ENR, 29, "hrtim"),
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CLK(RCC_APB2ENR, 28, "dfsdm1"),
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CLK(RCC_APB2ENR, 24, "sai3"),
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CLK(RCC_APB2ENR, 23, "sai2"),
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CLK(RCC_APB2ENR, 22, "sai1"),
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CLK(RCC_APB2ENR, 20, "spi5"),
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CLK(RCC_APB2ENR, 13, "spi4"),
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CLK(RCC_APB2ENR, 12, "spi1"),
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CLK(RCC_APB2ENR, 5, "usart6"),
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CLK(RCC_APB2ENR, 4, "usart1"),
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CLK(RCC_APB4ENR, 21, "sai4a"),
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CLK(RCC_APB4ENR, 21, "sai4b"),
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CLK(RCC_APB4ENR, 12, "lptim5"),
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CLK(RCC_APB4ENR, 11, "lptim4"),
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CLK(RCC_APB4ENR, 10, "lptim3"),
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CLK(RCC_APB4ENR, 9, "lptim2"),
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CLK(RCC_APB4ENR, 7, "i2c4"),
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CLK(RCC_APB4ENR, 5, "spi6"),
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CLK(RCC_APB4ENR, 3, "lpuart1"),
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{RCC_AHB3ENR, 31, "d1sram1"}, /* peripheral clocks */
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{RCC_AHB3ENR, 30, "itcm"},
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{RCC_AHB3ENR, 29, "dtcm2"},
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{RCC_AHB3ENR, 28, "dtcm1"},
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{RCC_AHB3ENR, 8, "flitf"},
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{RCC_AHB3ENR, 5, "jpgdec"},
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{RCC_AHB3ENR, 4, "dma2d"},
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{RCC_AHB3ENR, 0, "mdma"},
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{RCC_AHB1ENR, 28, "usb2ulpi"},
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{RCC_AHB1ENR, 17, "eth1rx"},
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{RCC_AHB1ENR, 16, "eth1tx"},
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{RCC_AHB1ENR, 15, "eth1mac"},
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{RCC_AHB1ENR, 14, "art"},
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{RCC_AHB1ENR, 26, "usb1ulpi"},
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{RCC_AHB1ENR, 1, "dma2"},
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{RCC_AHB1ENR, 0, "dma1"},
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{RCC_AHB2ENR, 31, "d2sram3"},
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{RCC_AHB2ENR, 30, "d2sram2"},
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{RCC_AHB2ENR, 29, "d2sram1"},
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{RCC_AHB2ENR, 5, "hash"},
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{RCC_AHB2ENR, 4, "crypt"},
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{RCC_AHB2ENR, 0, "camitf"},
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{RCC_AHB4ENR, 28, "bkpram"},
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{RCC_AHB4ENR, 25, "hsem"},
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{RCC_AHB4ENR, 21, "bdma"},
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{RCC_AHB4ENR, 19, "crc"},
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{RCC_AHB4ENR, 10, "gpiok"},
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{RCC_AHB4ENR, 9, "gpioj"},
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{RCC_AHB4ENR, 8, "gpioi"},
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{RCC_AHB4ENR, 7, "gpioh"},
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{RCC_AHB4ENR, 6, "gpiog"},
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{RCC_AHB4ENR, 5, "gpiof"},
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{RCC_AHB4ENR, 4, "gpioe"},
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{RCC_AHB4ENR, 3, "gpiod"},
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{RCC_AHB4ENR, 2, "gpioc"},
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{RCC_AHB4ENR, 1, "gpiob"},
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{RCC_AHB4ENR, 0, "gpioa"},
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{RCC_APB3ENR, 6, "wwdg1"},
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{RCC_APB1LENR, 29, "dac12"},
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{RCC_APB1LENR, 11, "wwdg2"},
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{RCC_APB1LENR, 8, "tim14"},
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{RCC_APB1LENR, 7, "tim13"},
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{RCC_APB1LENR, 6, "tim12"},
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{RCC_APB1LENR, 5, "tim7"},
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{RCC_APB1LENR, 4, "tim6"},
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{RCC_APB1LENR, 3, "tim5"},
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{RCC_APB1LENR, 2, "tim4"},
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{RCC_APB1LENR, 1, "tim3"},
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{RCC_APB1LENR, 0, "tim2"},
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{RCC_APB1HENR, 5, "mdios"},
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{RCC_APB1HENR, 4, "opamp"},
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{RCC_APB1HENR, 1, "crs"},
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{RCC_APB2ENR, 18, "tim17"},
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{RCC_APB2ENR, 17, "tim16"},
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{RCC_APB2ENR, 16, "tim15"},
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{RCC_APB2ENR, 1, "tim8"},
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{RCC_APB2ENR, 0, "tim1"},
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{RCC_APB4ENR, 26, "tmpsens"},
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{RCC_APB4ENR, 16, "rtcapb"},
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{RCC_APB4ENR, 15, "vref"},
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{RCC_APB4ENR, 14, "comp12"},
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{RCC_APB4ENR, 1, "syscfg"},
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{RCC_AHB3ENR, 16, "sdmmc1"}, /* kernel clocks */
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{RCC_AHB3ENR, 14, "quadspi"},
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{RCC_AHB3ENR, 12, "fmc"},
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{RCC_AHB1ENR, 27, "usb2otg"},
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{RCC_AHB1ENR, 25, "usb1otg"},
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{RCC_AHB1ENR, 5, "adc12"},
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{RCC_AHB2ENR, 9, "sdmmc2"},
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{RCC_AHB2ENR, 6, "rng"},
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{RCC_AHB4ENR, 24, "adc3"},
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{RCC_APB3ENR, 4, "dsi"},
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{RCC_APB3ENR, 3, "ltdc"},
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{RCC_APB1LENR, 31, "usart8"},
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{RCC_APB1LENR, 30, "usart7"},
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{RCC_APB1LENR, 27, "hdmicec"},
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{RCC_APB1LENR, 23, "i2c3"},
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{RCC_APB1LENR, 22, "i2c2"},
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{RCC_APB1LENR, 21, "i2c1"},
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{RCC_APB1LENR, 20, "uart5"},
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{RCC_APB1LENR, 19, "uart4"},
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{RCC_APB1LENR, 18, "usart3"},
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{RCC_APB1LENR, 17, "usart2"},
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{RCC_APB1LENR, 16, "spdifrx"},
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{RCC_APB1LENR, 15, "spi3"},
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{RCC_APB1LENR, 14, "spi2"},
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{RCC_APB1LENR, 9, "lptim1"},
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{RCC_APB1HENR, 8, "fdcan"},
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{RCC_APB1HENR, 2, "swp"},
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{RCC_APB2ENR, 29, "hrtim"},
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{RCC_APB2ENR, 28, "dfsdm1"},
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{RCC_APB2ENR, 24, "sai3"},
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{RCC_APB2ENR, 23, "sai2"},
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{RCC_APB2ENR, 22, "sai1"},
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{RCC_APB2ENR, 20, "spi5"},
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{RCC_APB2ENR, 13, "spi4"},
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{RCC_APB2ENR, 12, "spi1"},
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{RCC_APB2ENR, 5, "usart6"},
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{RCC_APB2ENR, 4, "usart1"},
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{RCC_APB4ENR, 21, "sai4a"},
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{RCC_APB4ENR, 21, "sai4b"},
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{RCC_APB4ENR, 12, "lptim5"},
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{RCC_APB4ENR, 11, "lptim4"},
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{RCC_APB4ENR, 10, "lptim3"},
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{RCC_APB4ENR, 9, "lptim2"},
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{RCC_APB4ENR, 7, "i2c4"},
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{RCC_APB4ENR, 5, "spi6"},
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{RCC_APB4ENR, 3, "lpuart1"},
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};
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struct stm32_clk {
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