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imx: mx7: Add comment to describe OTP TESTER registers
The tester registers provide a unique chip-level identifier which get_board_serial() returns in a "struct tag_serialnr". This patch documents the properties of the registers; in summary. 31:0 OCOTP_TESTER0 (most significant) - FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID OCOTP_TESTER1 (least significant) 31:24 - The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 23:16 - The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 15:11 - The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID 10:0 - FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID The 64 bits of data generate a unique serial number per-chip. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
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@ -202,6 +202,27 @@ int arch_misc_init(void)
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#endif
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#ifdef CONFIG_SERIAL_TAG
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/*
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* OCOTP_TESTER
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* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
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* OCOTP_TESTER describes a unique ID based on silicon wafer
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* and die X/Y position
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*
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* OCOTOP_TESTER offset 0x410
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* 31:0 fuse 0
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* FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
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*
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* OCOTP_TESTER1 offset 0x420
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* 31:24 fuse 1
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* The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
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* 23:16 fuse 1
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* The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
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* 15:11 fuse 1
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* The wafer number of the wafer on which the device was fabricated/SJC
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* CHALLENGE/ Unique ID
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* 10:0 fuse 1
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* FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
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*/
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void get_board_serial(struct tag_serialnr *serialnr)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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