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watchdog: octeontx_wdt: Add MIPS Octeon support

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This patch adds support for the Marvell Octeon watchdog driver, which
currently only support the ARM64 Octeon TX & TX2 platforms. Since the
IP is pretty similar, it makes sense to extend this driver to also
support the MIPS Octeon SoC.

A follow-up patch will enable this watchdog support on the EBB7304
eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
This commit is contained in:
Stefan Roese 2022-05-11 09:08:47 +02:00
parent 88d931a710
commit 1aa2b85810
2 changed files with 53 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/watchdog/Kconfig
View File

@ -213,14 +213,13 @@ config WDT_NPCM
It performs full SoC reset.
config WDT_OCTEONTX
bool "OcteonTX core watchdog support"
depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2)
bool "Octeon core watchdog support"
depends on WDT && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2)
default y
imply WATCHDOG
help
This enables OcteonTX watchdog driver, which can be
found on OcteonTX/TX2 chipsets and inline with driver model.
Only supports watchdog reset.
This enables the Octeon watchdog driver, which can be found on
various Octeon parts such as Octeon II/III and OcteonTX/TX2.
config WDT_OMAP3
bool "TI OMAP watchdog timer support"

67
drivers/watchdog/octeontx_wdt.c
View File

@ -15,16 +15,22 @@
DECLARE_GLOBAL_DATA_PTR;
#define CORE0_WDOG_OFFSET 0x40000
#define CORE0_POKE_OFFSET 0x50000
#define CORE0_POKE_OFFSET_MASK 0xfffffULL
#define WDOG_MODE GENMASK_ULL(1, 0)
#define WDOG_LEN GENMASK_ULL(19, 4)
#define WDOG_CNT GENMASK_ULL(43, 20)
struct octeontx_wdt_data {
u32 wdog_offset;
u32 poke_offset;
int timer_shift;
bool has_clk;
};
struct octeontx_wdt {
void __iomem *reg;
const struct octeontx_wdt_data *data;
struct clk clk;
};
@ -34,12 +40,16 @@ static int octeontx_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
u64 clk_rate, val;
u64 tout_wdog;
clk_rate = clk_get_rate(&priv->clk);
if (IS_ERR_VALUE(clk_rate))
return -EINVAL;
if (priv->data->has_clk) {
clk_rate = clk_get_rate(&priv->clk);
if (IS_ERR_VALUE(clk_rate))
return -EINVAL;
} else {
clk_rate = gd->bus_clk;
}
/* Watchdog counts in 1024 cycle steps */
tout_wdog = (clk_rate * timeout_ms / 1000) >> 10;
/* Watchdog counts in configured cycle steps */
tout_wdog = (clk_rate * timeout_ms / 1000) >> priv->data->timer_shift;
/*
* We can only specify the upper 16 bits of a 24 bit value.
@ -54,7 +64,7 @@ static int octeontx_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
val = FIELD_PREP(WDOG_MODE, 0x3) |
FIELD_PREP(WDOG_LEN, tout_wdog) |
FIELD_PREP(WDOG_CNT, tout_wdog << 8);
writeq(val, priv->reg + CORE0_WDOG_OFFSET);
writeq(val, priv->reg + priv->data->wdog_offset);
return 0;
}
@ -63,7 +73,7 @@ static int octeontx_wdt_stop(struct udevice *dev)
{
struct octeontx_wdt *priv = dev_get_priv(dev);
writeq(0, priv->reg + CORE0_WDOG_OFFSET);
writeq(0, priv->reg + priv->data->wdog_offset);
return 0;
}
@ -82,7 +92,7 @@ static int octeontx_wdt_reset(struct udevice *dev)
{
struct octeontx_wdt *priv = dev_get_priv(dev);
writeq(~0ULL, priv->reg + CORE0_POKE_OFFSET);
writeq(~0ULL, priv->reg + priv->data->poke_offset);
return 0;
}
@ -103,6 +113,10 @@ static int octeontx_wdt_probe(struct udevice *dev)
if (!priv->reg)
return -EINVAL;
priv->data = (void *)dev_get_driver_data(dev);
if (!priv->data)
return -EINVAL;
/*
* Save base register address in reg masking lower 20 bits
* as 0xa0000 appears when extracted from the DT
@ -110,13 +124,15 @@ static int octeontx_wdt_probe(struct udevice *dev)
priv->reg = (void __iomem *)(((u64)priv->reg &
~CORE0_POKE_OFFSET_MASK));
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret < 0)
return ret;
if (priv->data->has_clk) {
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret < 0)
return ret;
ret = clk_enable(&priv->clk);
if (ret)
return ret;
ret = clk_enable(&priv->clk);
if (ret)
return ret;
}
return 0;
}
@ -128,8 +144,23 @@ static const struct wdt_ops octeontx_wdt_ops = {
.expire_now = octeontx_wdt_expire_now,
};
static const struct octeontx_wdt_data octeontx_data = {
.wdog_offset = 0x40000,
.poke_offset = 0x50000,
.timer_shift = 10,
.has_clk = true,
};
static const struct octeontx_wdt_data octeon_data = {
.wdog_offset = 0x20000,
.poke_offset = 0x30000,
.timer_shift = 10,
.has_clk = false,
};
static const struct udevice_id octeontx_wdt_ids[] = {
{ .compatible = "arm,sbsa-gwdt" },
{ .compatible = "arm,sbsa-gwdt", .data = (ulong)&octeontx_data },
{ .compatible = "cavium,octeon-7890-ciu3", .data = (ulong)&octeon_data },
{}
};
@ -138,7 +169,7 @@ U_BOOT_DRIVER(wdt_octeontx) = {
.id = UCLASS_WDT,
.of_match = octeontx_wdt_ids,
.ops = &octeontx_wdt_ops,
.priv_auto = sizeof(struct octeontx_wdt),
.priv_auto = sizeof(struct octeontx_wdt),
.probe = octeontx_wdt_probe,
.remove = octeontx_wdt_remove,
.flags = DM_FLAG_OS_PREPARE,