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i.mx: introduce the armv7/imx-common folder

Browse Source 
In order to support the coming MX6 platform and to reducde
the duplicated code, we had better move some common files
or functions to the imx-common folder for sharing.

This patch does the following:
- move speed.c file from armv7/mx5/speed.c to armv7/imx-common/speed.c
- move armv7/mx5/timer.c to armv7/imx-common/timer.c, no any new feature
  added but just fix the checkpatch errors in the old file and remove
  the CONFIG_SYS_MX5_CLK32 reference in the file
- create one new file cpu.c file to store the common function with i.mx5/6

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Jason Liu 2011-11-25 00:18:01 +00:00 committed by Albert ARIBAUD
parent 393cb36199
commit 18936ee2ad
7 changed files with 173 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Makefile
View File

@ -296,6 +296,14 @@ LIBS += post/libpost.o
ifneq ($(CONFIG_AM335X)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS += $(CPUDIR)/omap-common/libomap-common.o
endif
ifeq ($(SOC),mx5)
LIBS += $(CPUDIR)/imx-common/libimx-common.o
endif
ifeq ($(SOC),mx6)
LIBS += $(CPUDIR)/imx-common/libimx-common.o
endif
ifeq ($(SOC),s5pc1xx)
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif

47
arch/arm/cpu/armv7/imx-common/Makefile Normal file
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@ -0,0 +1,47 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)libimx-common.o
COBJS = timer.o cpu.o speed.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

108
arch/arm/cpu/armv7/imx-common/cpu.c Normal file
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@ -0,0 +1,108 @@
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
static char *get_reset_cause(void)
{
u32 cause;
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
cause = readl(&src_regs->srsr);
writel(cause, &src_regs->srsr);
switch (cause) {
case 0x00001:
return "POR";
case 0x00004:
return "CSU";
case 0x00008:
return "IPP USER";
case 0x00010:
return "WDOG";
case 0x00020:
return "JTAG HIGH-Z";
case 0x00040:
return "JTAG SW";
case 0x10000:
return "WARM BOOT";
default:
return "unknown reset";
}
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u32 cpurev;
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
(cpurev & 0xFF000) >> 12,
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
int cpu_eth_init(bd_t *bis)
{
int rc = -ENODEV;
#if defined(CONFIG_FEC_MXC)
rc = fecmxc_initialize(bis);
#endif
return rc;
}
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(bd_t *bis)
{
#ifdef CONFIG_FSL_ESDHC
return fsl_esdhc_mmc_init(bis);
#else
return 0;
#endif
}
void reset_cpu(ulong addr)
{
__raw_writew(4, WDOG1_BASE_ADDR);
}

0
arch/arm/cpu/armv7/mx5/speed.c → arch/arm/cpu/armv7/imx-common/speed.c
View File

17
arch/arm/cpu/armv7/mx5/timer.c → arch/arm/cpu/armv7/imx-common/timer.c Normal file → Executable file
View File

@ -39,10 +39,11 @@ struct mxc_gpt {
static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
#define GPTCR_TEN (1) /* Timer enable */
#define GPTCR_SWR (1 << 15) /* Software reset */
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
#define CLK_32KHZ 32768 /* 32Khz input */
DECLARE_GLOBAL_DATA_PTR;
@ -68,7 +69,7 @@ int timer_init(void)
__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
val = __raw_readl(&cur_gpt->counter);
lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
timestamp = 0;
return 0;
@ -77,11 +78,11 @@ int timer_init(void)
ulong get_timer_masked(void)
{
ulong val = __raw_readl(&cur_gpt->counter);
val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
val /= (CLK_32KHZ / CONFIG_SYS_HZ);
if (val >= lastinc)
timestamp += (val - lastinc);
else
timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
timestamp += ((0xFFFFFFFF / (CLK_32KHZ / CONFIG_SYS_HZ))
- lastinc) + val;
lastinc = val;
return timestamp;
@ -96,7 +97,7 @@ ulong get_timer(ulong base)
void __udelay(unsigned long usec)
{
unsigned long now, start, tmo;
tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
tmo = usec * (CLK_32KHZ / 1000) / 1000;
if (!tmo)
tmo = 1;

2
arch/arm/cpu/armv7/mx5/Makefile
View File

@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS = soc.o clock.o iomux.o timer.o speed.o
COBJS = soc.o clock.o iomux.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

77
arch/arm/cpu/armv7/mx5/soc.c
View File

@ -31,10 +31,6 @@
#include <asm/errno.h>
#include <asm/io.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
#error "CPU_TYPE not defined"
#endif
@ -75,61 +71,6 @@ u32 get_cpu_rev(void)
return system_rev;
}
static char *get_reset_cause(void)
{
u32 cause;
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
cause = readl(&src_regs->srsr);
writel(cause, &src_regs->srsr);
switch (cause) {
case 0x00001:
return "POR";
case 0x00004:
return "CSU";
case 0x00008:
return "IPP USER";
case 0x00010:
return "WDOG";
case 0x00020:
return "JTAG HIGH-Z";
case 0x00040:
return "JTAG SW";
case 0x10000:
return "WARM BOOT";
default:
return "unknown reset";
}
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u32 cpurev;
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
(cpurev & 0xFF000) >> 12,
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
int cpu_eth_init(bd_t *bis)
{
int rc = -ENODEV;
#if defined(CONFIG_FEC_MXC)
rc = fecmxc_initialize(bis);
#endif
return rc;
}
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(unsigned char *mac)
{
@ -144,19 +85,6 @@ void imx_get_mac_from_fuse(unsigned char *mac)
}
#endif
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(bd_t *bis)
{
#ifdef CONFIG_FSL_ESDHC
return fsl_esdhc_mmc_init(bis);
#else
return 0;
#endif
}
void set_chipselect_size(int const cs_size)
{
unsigned int reg;
@ -187,8 +115,3 @@ void set_chipselect_size(int const cs_size)
writel(reg, &iomuxc_regs->gpr1);
}
void reset_cpu(ulong addr)
{
__raw_writew(4, WDOG1_BASE_ADDR);
}