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mtd: mxs_nand: fix the gf_13/14 definition issue
gf_13/14 mask was not set correctly in register definition. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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@ -151,9 +151,9 @@ struct mxs_bch_regs {
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#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12)
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#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10)
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#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_MASK BIT(10)
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#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10
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#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff
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#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0x3ff
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#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0
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#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
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@ -182,9 +182,9 @@ struct mxs_bch_regs {
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#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12)
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#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10)
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#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK BIT(10)
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#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10
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#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff
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#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0x3ff
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#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0
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#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27)
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@ -1474,6 +1474,8 @@ void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l)
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BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET);
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l->eccn = (tmp & BCH_FLASHLAYOUT1_ECCN_MASK) >>
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BCH_FLASHLAYOUT1_ECCN_OFFSET;
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l->gf_len = (tmp & BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK) >>
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BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
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}
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/*
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@ -88,6 +88,7 @@ struct mxs_nand_layout {
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u32 ecc0;
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u32 datan_size;
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u32 eccn;
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u32 gf_len;
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};
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int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info);
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