mirrors/u-boot
0
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2024-11-30 08:03:32 +08:00
Code Issues Packages Projects Releases Wiki Activity

ARM: OMAP5: Add support for disabling clocks in uboot

Browse Source 
Add do_disable_clocks() to disable clock domains and module clocks.
These clocks are enabled using do_enable_clocks().

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
This commit is contained in:
Kishon Vijay Abraham I 2015-08-17 13:29:51 +05:30 committed by Jagan Teki
parent fca45722fb
commit 16ca1d09e6
2 changed files with 57 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
arch/arm/cpu/armv7/omap-common/clocks-common.c
View File

@ -648,6 +648,14 @@ static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
debug("Enable clock domain - %x\n", clkctrl_reg);
}
static inline void disable_clock_domain(u32 const clkctrl_reg)
{
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
CD_CLKCTRL_CLKTRCTRL_SHIFT);
debug("Disable clock domain - %x\n", clkctrl_reg);
}
static inline void wait_for_clk_enable(u32 clkctrl_addr)
{
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
@ -677,6 +685,34 @@ static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
wait_for_clk_enable(clkctrl_addr);
}
static inline void wait_for_clk_disable(u32 clkctrl_addr)
{
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
u32 bound = LDELAY;
while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
clkctrl = readl(clkctrl_addr);
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
MODULE_CLKCTRL_IDLEST_SHIFT;
if (--bound == 0) {
printf("Clock disable failed for 0x%x idlest 0x%x\n",
clkctrl_addr, clkctrl);
return;
}
}
}
static inline void disable_clock_module(u32 const clkctrl_addr,
u32 wait_for_disable)
{
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
debug("Disable clock module - %x\n", clkctrl_addr);
if (wait_for_disable)
wait_for_clk_disable(clkctrl_addr);
}
void freq_update_core(void)
{
u32 freq_config1 = 0;
@ -800,6 +836,23 @@ void do_enable_clocks(u32 const *clk_domains,
}
}
void do_disable_clocks(u32 const *clk_domains,
u32 const *clk_modules_disable,
u8 wait_for_disable)
{
u32 i, max = 100;
/* Clock modules that need to be put in SW_DISABLE */
for (i = 0; (i < max) && clk_modules_disable[i]; i++)
disable_clock_module(clk_modules_disable[i],
wait_for_disable);
/* Put the clock domains in SW_SLEEP mode */
for (i = 0; (i < max) && clk_domains[i]; i++)
disable_clock_domain(clk_domains[i]);
}
void prcm_init(void)
{
switch (omap_hw_init_context()) {

4
arch/arm/include/asm/omap_common.h
View File

@ -575,6 +575,10 @@ void do_enable_clocks(u32 const *clk_domains,
u32 const *clk_modules_explicit_en,
u8 wait_for_enable);
void do_disable_clocks(u32 const *clk_domains,
u32 const *clk_modules_disable,
u8 wait_for_disable);
void setup_post_dividers(u32 const base,
const struct dpll_params *params);
u32 omap_ddr_clk(void);