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riscv: Clean up initialization in Andes PLIC
This merges the PLIC initialization code from two functions into one. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
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@ -41,53 +41,45 @@ static int enable_ipi(int hart)
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return 0;
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}
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static int init_plic(void)
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int riscv_init_ipi(void)
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{
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struct udevice *dev;
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ofnode node;
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int ret;
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long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
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ofnode node;
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struct udevice *dev;
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u32 reg;
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if (IS_ERR(base))
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return PTR_ERR(base);
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gd->arch.plic = base;
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ret = uclass_find_first_device(UCLASS_CPU, &dev);
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if (ret)
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return ret;
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else if (!dev)
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return -ENODEV;
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if (dev) {
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ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
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const char *device_type;
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ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
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const char *device_type;
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device_type = ofnode_read_string(node, "device_type");
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if (!device_type)
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continue;
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device_type = ofnode_read_string(node, "device_type");
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if (!device_type)
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continue;
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if (strcmp(device_type, "cpu"))
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continue;
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if (strcmp(device_type, "cpu"))
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continue;
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/* skip if hart is marked as not available */
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if (!ofnode_is_available(node))
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continue;
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/* skip if hart is marked as not available */
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if (!ofnode_is_available(node))
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continue;
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/* read hart ID of CPU */
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ret = ofnode_read_u32(node, "reg", ®);
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if (ret == 0)
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enable_ipi(reg);
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}
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return 0;
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/* read hart ID of CPU */
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ret = ofnode_read_u32(node, "reg", ®);
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if (ret == 0)
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enable_ipi(reg);
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}
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return -ENODEV;
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}
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int riscv_init_ipi(void)
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{
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long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
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if (IS_ERR(ret))
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return PTR_ERR(ret);
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gd->arch.plic = ret;
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return init_plic();
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return 0;
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}
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int riscv_send_ipi(int hart)
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