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fpga: xilinx: Simplify load/dump/info function handling

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Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2014-03-13 13:07:57 +01:00
parent 2df9d5c431
commit 14cfc4f373
12 changed files with 104 additions and 223 deletions
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1
board/armadeus/apf27/fpga.c
View File

@ -48,6 +48,7 @@ xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
1196128l/8,
(void *)&fpga_fns,
0,
&spartan3_op,
"3s200aft256"}
};

3
board/astro/mcf5373l/fpga.c
View File

@ -379,7 +379,8 @@ xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
slave_serial,
XILINX_XC3S4000_SIZE,
(void *)&xilinx_fns,
0}
0,
&spartan3_op}
};
/* Initialize the fpga. Return 1 on success, 0 on failure. */

12
drivers/fpga/spartan2.c
View File

@ -41,7 +41,7 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@ -64,7 +64,7 @@ int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
return ret_val;
}
int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@ -87,7 +87,7 @@ int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
return ret_val;
}
int spartan2_info(xilinx_desc *desc)
static int spartan2_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@ -447,3 +447,9 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
__FUNCTION__);
return FPGA_FAIL;
}
struct xilinx_fpga_op spartan2_op = {
.load = spartan2_load,
.dump = spartan2_dump,
.info = spartan2_info,
};

12
drivers/fpga/spartan3.c
View File

@ -45,7 +45,7 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@ -68,7 +68,7 @@ int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
return ret_val;
}
int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@ -91,7 +91,7 @@ int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
return ret_val;
}
int spartan3_info(xilinx_desc *desc)
static int spartan3_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@ -465,3 +465,9 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
__FUNCTION__);
return FPGA_FAIL;
}
struct xilinx_fpga_op spartan3_op = {
.load = spartan3_load,
.dump = spartan3_dump,
.info = spartan3_info,
};

12
drivers/fpga/virtex2.c
View File

@ -90,7 +90,7 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@ -112,7 +112,7 @@ int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
return ret_val;
}
int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@ -134,7 +134,7 @@ int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
return ret_val;
}
int virtex2_info(xilinx_desc *desc)
static int virtex2_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@ -417,3 +417,9 @@ static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
}
/* vim: set ts=4 tw=78: */
struct xilinx_fpga_op virtex2_op = {
.load = virtex2_load,
.dump = virtex2_dump,
.info = virtex2_info,
};

159
drivers/fpga/xilinx.c
View File

@ -19,17 +19,6 @@
#include <spartan3.h>
#include <zynqpl.h>
#if 0
#define FPGA_DEBUG
#endif
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
/* Local Static Functions */
static int xilinx_validate(xilinx_desc *desc, char *fn);
@ -143,116 +132,22 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
} else
switch (desc->family) {
case xilinx_spartan2:
#if defined(CONFIG_FPGA_SPARTAN2)
PRINTF ("%s: Launching the Spartan-II Loader...\n",
__FUNCTION__);
ret_val = spartan2_load(desc, buf, bsize);
#else
printf ("%s: No support for Spartan-II devices.\n",
__FUNCTION__);
#endif
break;
case xilinx_spartan3:
#if defined(CONFIG_FPGA_SPARTAN3)
PRINTF ("%s: Launching the Spartan-III Loader...\n",
__FUNCTION__);
ret_val = spartan3_load(desc, buf, bsize);
#else
printf ("%s: No support for Spartan-III devices.\n",
__FUNCTION__);
#endif
break;
case xilinx_virtex2:
#if defined(CONFIG_FPGA_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Loader...\n",
__FUNCTION__);
ret_val = virtex2_load(desc, buf, bsize);
#else
printf ("%s: No support for Virtex-II devices.\n",
__FUNCTION__);
#endif
break;
case xilinx_zynq:
#if defined(CONFIG_FPGA_ZYNQPL)
PRINTF("%s: Launching the Zynq PL Loader...\n",
__func__);
ret_val = zynq_load(desc, buf, bsize);
#else
printf("%s: No support for Zynq devices.\n",
__func__);
#endif
break;
return FPGA_FAIL;
}
default:
printf ("%s: Unsupported family type, %d\n",
__FUNCTION__, desc->family);
}
return ret_val;
return desc->operations->load(desc, buf, bsize);
}
int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
} else
switch (desc->family) {
case xilinx_spartan2:
#if defined(CONFIG_FPGA_SPARTAN2)
PRINTF ("%s: Launching the Spartan-II Reader...\n",
__FUNCTION__);
ret_val = spartan2_dump(desc, buf, bsize);
#else
printf ("%s: No support for Spartan-II devices.\n",
__FUNCTION__);
#endif
break;
case xilinx_spartan3:
#if defined(CONFIG_FPGA_SPARTAN3)
PRINTF ("%s: Launching the Spartan-III Reader...\n",
__FUNCTION__);
ret_val = spartan3_dump(desc, buf, bsize);
#else
printf ("%s: No support for Spartan-III devices.\n",
__FUNCTION__);
#endif
break;
case xilinx_virtex2:
#if defined( CONFIG_FPGA_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Reader...\n",
__FUNCTION__);
ret_val = virtex2_dump(desc, buf, bsize);
#else
printf ("%s: No support for Virtex-II devices.\n",
__FUNCTION__);
#endif
break;
case xilinx_zynq:
#if defined(CONFIG_FPGA_ZYNQPL)
PRINTF("%s: Launching the Zynq PL Reader...\n",
__func__);
ret_val = zynq_dump(desc, buf, bsize);
#else
printf("%s: No support for Zynq devices.\n",
__func__);
#endif
break;
return FPGA_FAIL;
}
default:
printf ("%s: Unsupported family type, %d\n",
__FUNCTION__, desc->family);
}
return ret_val;
return desc->operations->dump(desc, buf, bsize);
}
int xilinx_info(xilinx_desc *desc)
@ -315,47 +210,7 @@ int xilinx_info(xilinx_desc *desc)
if (desc->iface_fns) {
printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
switch (desc->family) {
case xilinx_spartan2:
#if defined(CONFIG_FPGA_SPARTAN2)
spartan2_info(desc);
#else
/* just in case */
printf ("%s: No support for Spartan-II devices.\n",
__FUNCTION__);
#endif
break;
case xilinx_spartan3:
#if defined(CONFIG_FPGA_SPARTAN3)
spartan3_info(desc);
#else
/* just in case */
printf ("%s: No support for Spartan-III devices.\n",
__FUNCTION__);
#endif
break;
case xilinx_virtex2:
#if defined(CONFIG_FPGA_VIRTEX2)
virtex2_info(desc);
#else
/* just in case */
printf ("%s: No support for Virtex-II devices.\n",
__FUNCTION__);
#endif
break;
case xilinx_zynq:
#if defined(CONFIG_FPGA_ZYNQPL)
zynq_info(desc);
#else
/* just in case */
printf("%s: No support for Zynq devices.\n",
__func__);
#endif
/* Add new family types here */
default:
/* we don't need a message here - we give one up above */
;
}
desc->operations->info(desc);
} else
printf ("No Device Function Table.\n");

13
drivers/fpga/zynqpl.c
View File

@ -36,7 +36,7 @@
#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
#endif
int zynq_info(xilinx_desc *desc)
static int zynq_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@ -152,8 +152,7 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap)
return 0;
}
int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
unsigned long ts; /* Timestamp */
u32 partialbit = 0;
@ -358,7 +357,13 @@ int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
return FPGA_SUCCESS;
}
int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
return FPGA_FAIL;
}
struct xilinx_fpga_op zynq_op = {
.load = zynq_load,
.dump = zynq_dump,
.info = zynq_info,
};

28
include/spartan2.h
View File

@ -10,10 +10,6 @@
#include <xilinx.h>
int spartan2_load(xilinx_desc *desc, const void *image, size_t size);
int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize);
int spartan2_info(xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
xilinx_pre_fn pre;
@ -42,6 +38,8 @@ typedef struct {
xilinx_post_fn post;
} xilinx_spartan2_slave_serial_fns;
extern struct xilinx_fpga_op spartan2_op;
/* Device Image Sizes
*********************************************************************/
/* Spartan-II (2.5V) */
@ -63,36 +61,36 @@ typedef struct {
*********************************************************************/
/* Spartan-II devices */
#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie }
{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie }
{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie }
{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie }
{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie }
{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op }
#endif /* _SPARTAN2_H_ */

36
include/spartan3.h
View File

@ -10,10 +10,6 @@
#include <xilinx.h>
int spartan3_load(xilinx_desc *desc, const void *image, size_t size);
int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize);
int spartan3_info(xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
xilinx_pre_fn pre;
@ -44,6 +40,8 @@ typedef struct {
xilinx_abort_fn abort;
} xilinx_spartan3_slave_serial_fns;
extern struct xilinx_fpga_op spartan3_op;
/* Device Image Sizes
*********************************************************************/
/* Spartan-III (1.2V) */
@ -73,46 +71,48 @@ typedef struct {
*********************************************************************/
/* Spartan-III devices */
#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op }
/* Spartan-3E devices */
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
&spartan3_op }
#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
&spartan3_op }
#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie }
{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op }
#endif /* _SPARTAN3_H_ */

28
include/virtex2.h
View File

@ -11,9 +11,7 @@
#include <xilinx.h>
int virtex2_load(xilinx_desc *desc, const void *image, size_t size);
int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize);
int virtex2_info(xilinx_desc *desc);
extern struct xilinx_fpga_op virtex2_op;
/*
* Slave SelectMap Implementation function table.
@ -60,39 +58,39 @@ typedef struct {
/* Descriptor Macros
*********************************************************************/
#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op }
#endif /* _VIRTEX2_H_ */

7
include/xilinx.h
View File

@ -40,9 +40,16 @@ typedef struct { /* typedef xilinx_desc */
size_t size; /* bytes of data part can accept */
void *iface_fns; /* interface function table */
int cookie; /* implementation specific cookie */
struct xilinx_fpga_op *operations; /* operations */
char *name; /* device name in bitstream */
} xilinx_desc; /* end, typedef xilinx_desc */
struct xilinx_fpga_op {
int (*load)(xilinx_desc *, const void *, size_t);
int (*dump)(xilinx_desc *, const void *, size_t);
int (*info)(xilinx_desc *);
};
/* Generic Xilinx Functions
*********************************************************************/
int xilinx_load(xilinx_desc *desc, const void *image, size_t size);

16
include/zynqpl.h
View File

@ -12,9 +12,7 @@
#include <xilinx.h>
int zynq_load(xilinx_desc *desc, const void *image, size_t size);
int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize);
int zynq_info(xilinx_desc *desc);
extern struct xilinx_fpga_op zynq_op;
#define XILINX_ZYNQ_7010 0x2
#define XILINX_ZYNQ_7015 0x1b
@ -33,21 +31,21 @@ int zynq_info(xilinx_desc *desc);
/* Descriptor Macros */
#define XILINX_XC7Z010_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" }
#define XILINX_XC7Z015_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" }
{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" }
#define XILINX_XC7Z020_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" }
#define XILINX_XC7Z030_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" }
{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" }
#define XILINX_XC7Z045_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" }
#define XILINX_XC7Z100_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" }
{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" }
#endif /* _ZYNQPL_H_ */