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net: fec_mxc: add PHYLIB support
Surround non PHYLIB routines miiphy_restart_aneg and miiphy_wait_aneg with ifndef CONFIG_PHYLIB. When later PHYLIB is required it is easy to delete the non-PHYLIB code. This separation idea came from Andy Fleming. fec_miiphy_read, and fec_miiphy_write changed to fec_phy_read, and fec_phy_write with argument changes. Deprecated miiphy_register is no longer used. Both old and new PHYLIB code now use mdio_register. Cleanup some debug prints. Inline function fec_miiphy_fec_to_eth is no longer necessary. Moved to the single call location. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
This commit is contained in:
Troy Kisky
Albert ARIBAUD
parent
28774cbaac
commit
13947f43c9
@ -69,35 +69,16 @@ static void swap_packet(uint32_t *packet, int length)
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}
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#endif
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/*
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* The i.MX28 has two ethernet interfaces, but they are not equal.
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* Only the first one can access the MDIO bus.
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*/
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#ifdef CONFIG_MX28
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static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
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{
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return (struct ethernet_regs *)MXS_ENET0_BASE;
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}
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#else
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static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
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{
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return fec->eth;
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}
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#endif
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/*
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* MII-interface related functions
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*/
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static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
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uint16_t *retVal)
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static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
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uint8_t regAddr)
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{
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struct eth_device *edev = eth_get_dev_by_name(dev);
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struct fec_priv *fec = (struct fec_priv *)edev->priv;
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struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
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uint32_t reg; /* convenient holder for the PHY register */
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uint32_t phy; /* convenient holder for the PHY */
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uint32_t start;
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int val;
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/*
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* reading from any PHY's register is done by properly
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@ -129,10 +110,10 @@ static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
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/*
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* it's now safe to read the PHY's register
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*/
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*retVal = readl(ð->mii_data);
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debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
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regAddr, *retVal);
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return 0;
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val = (unsigned short)readl(ð->mii_data);
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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
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regAddr, val);
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return val;
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}
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static void fec_mii_setspeed(struct fec_priv *fec)
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@ -143,16 +124,12 @@ static void fec_mii_setspeed(struct fec_priv *fec)
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*/
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writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
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&fec->eth->mii_speed);
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debug("fec_init: mii_speed %08x\n",
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readl(&fec->eth->mii_speed));
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debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed));
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}
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static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
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uint16_t data)
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{
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struct eth_device *edev = eth_get_dev_by_name(dev);
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struct fec_priv *fec = (struct fec_priv *)edev->priv;
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struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
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static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
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uint8_t regAddr, uint16_t data)
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{
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uint32_t reg; /* convenient holder for the PHY register */
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uint32_t phy; /* convenient holder for the PHY */
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uint32_t start;
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@ -178,15 +155,28 @@ static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
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* clear MII interrupt bit
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*/
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writel(FEC_IEVENT_MII, ð->ievent);
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debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
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regAddr, data);
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return 0;
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}
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int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
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{
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return fec_mdio_read(bus->priv, phyAddr, regAddr);
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}
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int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
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u16 data)
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{
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return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
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}
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#ifndef CONFIG_PHYLIB
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static int miiphy_restart_aneg(struct eth_device *dev)
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{
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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struct ethernet_regs *eth = fec->bus->priv;
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int ret = 0;
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/*
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@ -194,19 +184,18 @@ static int miiphy_restart_aneg(struct eth_device *dev)
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* Reset PHY, then delay 300ns
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*/
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#ifdef CONFIG_MX27
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miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF);
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fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
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#endif
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miiphy_write(dev->name, fec->phy_id, MII_BMCR,
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BMCR_RESET);
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fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
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udelay(1000);
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/*
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* Set the auto-negotiation advertisement register bits
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*/
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miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
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fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
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LPA_100FULL | LPA_100HALF | LPA_10FULL |
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LPA_10HALF | PHY_ANLPAR_PSB_802_3);
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miiphy_write(dev->name, fec->phy_id, MII_BMCR,
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fec_mdio_write(eth, fec->phy_id, MII_BMCR,
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BMCR_ANENABLE | BMCR_ANRESTART);
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if (fec->mii_postcall)
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@ -218,8 +207,9 @@ static int miiphy_restart_aneg(struct eth_device *dev)
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static int miiphy_wait_aneg(struct eth_device *dev)
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{
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uint32_t start;
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uint16_t status;
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int status;
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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struct ethernet_regs *eth = fec->bus->priv;
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/*
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* Wait for AN completion
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@ -231,9 +221,9 @@ static int miiphy_wait_aneg(struct eth_device *dev)
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return -1;
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}
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if (miiphy_read(dev->name, fec->phy_id,
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MII_BMSR, &status)) {
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printf("%s: Autonegotiation failed. status: 0x%04x\n",
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status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
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if (status < 0) {
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printf("%s: Autonegotiation failed. status: %d\n",
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dev->name, status);
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return -1;
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}
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@ -241,6 +231,8 @@ static int miiphy_wait_aneg(struct eth_device *dev)
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return 0;
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}
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#endif
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static int fec_rx_task_enable(struct fec_priv *fec)
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{
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writel(1 << 24, &fec->eth->r_des_active);
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@ -372,6 +364,21 @@ static int fec_set_hwaddr(struct eth_device *dev)
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return 0;
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}
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static void fec_eth_phy_config(struct eth_device *dev)
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{
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#ifdef CONFIG_PHYLIB
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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struct phy_device *phydev;
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phydev = phy_connect(fec->bus, fec->phy_id, dev,
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PHY_INTERFACE_MODE_RGMII);
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if (phydev) {
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fec->phydev = phydev;
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phy_config(phydev);
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}
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#endif
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}
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/**
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* Start the FEC engine
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* @param[in] dev Our device to handle
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@ -428,9 +435,21 @@ static int fec_open(struct eth_device *edev)
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}
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#endif
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#ifdef CONFIG_PHYLIB
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if (!fec->phydev)
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fec_eth_phy_config(edev);
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if (fec->phydev) {
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/* Start up the PHY */
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phy_startup(fec->phydev);
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speed = fec->phydev->speed;
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} else {
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speed = _100BASET;
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}
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#else
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miiphy_wait_aneg(edev);
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speed = miiphy_speed(edev->name, fec->phy_id);
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miiphy_duplex(edev->name, fec->phy_id);
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#endif
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#ifdef FEC_QUIRK_ENET_MAC
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{
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@ -558,9 +577,10 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
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fec_tbd_init(fec);
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#ifndef CONFIG_PHYLIB
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if (fec->xcv_type != SEVENWIRE)
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miiphy_restart_aneg(dev);
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#endif
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fec_open(dev);
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return 0;
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}
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@ -762,6 +782,7 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
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{
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struct eth_device *edev;
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struct fec_priv *fec;
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struct mii_dev *bus;
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unsigned char ethaddr[6];
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uint32_t start;
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int ret = 0;
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@ -836,15 +857,40 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
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}
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fec->phy_id = phy_id;
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miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
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bus = mdio_alloc();
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if (!bus) {
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printf("mdio_alloc failed\n");
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ret = -ENOMEM;
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goto err3;
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}
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bus->read = fec_phy_read;
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bus->write = fec_phy_write;
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sprintf(bus->name, edev->name);
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#ifdef CONFIG_MX28
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/*
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* The i.MX28 has two ethernet interfaces, but they are not equal.
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* Only the first one can access the MDIO bus.
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*/
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bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE;
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#else
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bus->priv = fec->eth;
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#endif
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ret = mdio_register(bus);
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if (ret) {
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printf("mdio_register failed\n");
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free(bus);
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ret = -ENOMEM;
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goto err3;
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}
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fec->bus = bus;
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eth_register(edev);
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if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
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debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
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memcpy(edev->enetaddr, ethaddr, 6);
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}
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/* Configure phy */
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fec_eth_phy_config(edev);
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return ret;
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err3:
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@ -877,9 +923,11 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
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return lout;
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}
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#ifndef CONFIG_PHYLIB
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int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
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{
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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fec->mii_postcall = cb;
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return 0;
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}
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#endif
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@ -286,7 +286,12 @@ struct fec_priv {
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void *base_ptr;
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int dev_id;
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int phy_id;
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struct mii_dev *bus;
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#ifdef CONFIG_PHYLIB
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struct phy_device *phydev;
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#else
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int (*mii_postcall)(int);
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#endif
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};
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/**
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