mirror of
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Subtree merge tag 'v6.11-dts' of dts repo [1] into dts/upstream
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
This commit is contained in:
Tom Rini
commit
136b7b6d2e
@ -22,6 +22,10 @@ properties:
|
||||
- enum:
|
||||
- airoha,en7523-evb
|
||||
- const: airoha,en7523
|
||||
- items:
|
||||
- enum:
|
||||
- airoha,en7581-evb
|
||||
- const: airoha,en7581
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
|
||||
@ -91,6 +91,7 @@ properties:
|
||||
- libretech,aml-s905x-cc
|
||||
- libretech,aml-s905x-cc-v2
|
||||
- nexbox,a95x
|
||||
- osmc,vero4k
|
||||
- const: amlogic,s905x
|
||||
- const: amlogic,meson-gxl
|
||||
|
||||
@ -107,6 +108,13 @@ properties:
|
||||
- const: amlogic,s905d
|
||||
- const: amlogic,meson-gxl
|
||||
|
||||
- description: Boards with the Amlogic Meson GXLX S905L SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,p271
|
||||
- const: amlogic,s905l
|
||||
- const: amlogic,meson-gxlx
|
||||
|
||||
- description: Boards with the Amlogic Meson GXM S912 SoC
|
||||
items:
|
||||
- enum:
|
||||
@ -169,6 +177,8 @@ properties:
|
||||
- azw,gtking
|
||||
- azw,gtking-pro
|
||||
- bananapi,bpi-m2s
|
||||
- dream,dreambox-one
|
||||
- dream,dreambox-two
|
||||
- hardkernel,odroid-go-ultra
|
||||
- hardkernel,odroid-n2
|
||||
- hardkernel,odroid-n2l
|
||||
|
||||
@ -1,20 +0,0 @@
|
||||
Amlogic Meson8 and Meson8b "analog top" registers:
|
||||
--------------------------------------------------
|
||||
|
||||
The analog top registers contain information about the so-called
|
||||
"metal revision" (which encodes the "minor version") of the SoC.
|
||||
|
||||
Required properties:
|
||||
- reg: the register range of the analog top registers
|
||||
- compatible: depending on the SoC this should be one of:
|
||||
- "amlogic,meson8-analog-top"
|
||||
- "amlogic,meson8b-analog-top"
|
||||
along with "syscon"
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
analog_top: analog-top@81a8 {
|
||||
compatible = "amlogic,meson8-analog-top", "syscon";
|
||||
reg = <0x81a8 0x14>;
|
||||
};
|
||||
@ -1,17 +0,0 @@
|
||||
Amlogic Meson6/Meson8/Meson8b assist registers:
|
||||
-----------------------------------------------
|
||||
|
||||
The assist registers contain basic information about the SoC,
|
||||
for example the encoded SoC part number.
|
||||
|
||||
Required properties:
|
||||
- reg: the register range of the assist registers
|
||||
- compatible: should be "amlogic,meson-mx-assist" along with "syscon"
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
assist: assist@7c00 {
|
||||
compatible = "amlogic,meson-mx-assist", "syscon";
|
||||
reg = <0x7c00 0x200>;
|
||||
};
|
||||
@ -1,17 +0,0 @@
|
||||
Amlogic Meson6/Meson8/Meson8b bootrom:
|
||||
--------------------------------------
|
||||
|
||||
The bootrom register area can be used to access SoC specific
|
||||
information, such as the "misc version".
|
||||
|
||||
Required properties:
|
||||
- reg: the register range of the bootrom registers
|
||||
- compatible: should be "amlogic,meson-mx-bootrom" along with "syscon"
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
bootrom: bootrom@d9040000 {
|
||||
compatible = "amlogic,meson-mx-bootrom", "syscon";
|
||||
reg = <0xd9040000 0x10000>;
|
||||
};
|
||||
@ -1,18 +0,0 @@
|
||||
Amlogic Meson8 and Meson8b power-management-unit:
|
||||
-------------------------------------------------
|
||||
|
||||
The pmu is used to turn off and on different power domains of the SoCs
|
||||
This includes the power to the CPU cores.
|
||||
|
||||
Required node properties:
|
||||
- compatible value : depending on the SoC this should be one of:
|
||||
"amlogic,meson8-pmu"
|
||||
"amlogic,meson8b-pmu"
|
||||
- reg : physical base address and the size of the registers window
|
||||
|
||||
Example:
|
||||
|
||||
pmu@c81000e4 {
|
||||
compatible = "amlogic,meson8b-pmu", "syscon";
|
||||
reg = <0xc81000e0 0x18>;
|
||||
};
|
||||
@ -30,7 +30,7 @@ description: |
|
||||
maintainers:
|
||||
- Mike Leach <mike.leach@linaro.org>
|
||||
- Suzuki K Poulose <suzuki.poulose@arm.com>
|
||||
- James Clark <james.clark@arm.com>
|
||||
- James Clark <james.clark@linaro.org>
|
||||
- Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
- Hao Zhang <quic_hazha@quicinc.com>
|
||||
|
||||
|
||||
@ -29,7 +29,7 @@ description: |
|
||||
maintainers:
|
||||
- Mike Leach <mike.leach@linaro.org>
|
||||
- Suzuki K Poulose <suzuki.poulose@arm.com>
|
||||
- James Clark <james.clark@arm.com>
|
||||
- James Clark <james.clark@linaro.org>
|
||||
- Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
- Hao Zhang <quic_hazha@quicinc.com>
|
||||
|
||||
|
||||
61
dts/upstream/Bindings/arm/arm,juno-fpga-apb-regs.yaml
Normal file
61
dts/upstream/Bindings/arm/arm,juno-fpga-apb-regs.yaml
Normal file
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/arm,juno-fpga-apb-regs.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Juno FPGA APB Registers
|
||||
|
||||
maintainers:
|
||||
- Sudeep Holla <sudeep.holla@arm.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: arm,juno-fpga-apb-regs
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ranges: true
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^led@[0-9a-f]+,[0-9a-f]$":
|
||||
$ref: /schemas/leds/register-bit-led.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ranges
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
syscon@10000 {
|
||||
compatible = "arm,juno-fpga-apb-regs", "syscon", "simple-mfd";
|
||||
reg = <0x010000 0x1000>;
|
||||
ranges = <0x0 0x10000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
led@8,0 {
|
||||
compatible = "register-bit-led";
|
||||
reg = <0x08 0x04>;
|
||||
offset = <0x08>;
|
||||
mask = <0x01>;
|
||||
label = "vexpress:0";
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
@ -41,35 +41,6 @@ Examples:
|
||||
reg = <0xffffe800 0x200>;
|
||||
};
|
||||
|
||||
RAMC PHY Controller required properties:
|
||||
- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
Example:
|
||||
|
||||
ddr3phy: ddr3phy@e3804000 {
|
||||
compatible = "microchip,sama7g5-ddr3phy", "syscon";
|
||||
reg = <0xe3804000 0x1000>;
|
||||
};
|
||||
|
||||
Special Function Registers (SFR)
|
||||
|
||||
Special Function Registers (SFR) manage specific aspects of the integrated
|
||||
memory, bridge implementations, processor and other functionality not controlled
|
||||
elsewhere.
|
||||
|
||||
required properties:
|
||||
- compatible: Should be "atmel,<chip>-sfr", "syscon" or
|
||||
"atmel,<chip>-sfrbu", "syscon"
|
||||
<chip> can be "sama5d3", "sama5d4" or "sama5d2".
|
||||
It also can be "microchip,sam9x60-sfr", "syscon".
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
sfr@f0038000 {
|
||||
compatible = "atmel,sama5d3-sfr", "syscon";
|
||||
reg = <0xf0038000 0x60>;
|
||||
};
|
||||
|
||||
Security Module (SECUMOD)
|
||||
|
||||
The Security Module macrocell provides all necessary secure functions to avoid
|
||||
|
||||
@ -7,22 +7,6 @@ ARTPEC-6 ARM SoC
|
||||
Required root node properties:
|
||||
- compatible = "axis,artpec6";
|
||||
|
||||
ARTPEC-6 System Controller
|
||||
--------------------------
|
||||
|
||||
The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe
|
||||
and resets.
|
||||
|
||||
Required properties:
|
||||
- compatible: "axis,artpec6-syscon", "syscon"
|
||||
- reg: Address and length of the register bank.
|
||||
|
||||
Example:
|
||||
syscon {
|
||||
compatible = "axis,artpec6-syscon", "syscon";
|
||||
reg = <0xf8000000 0x48>;
|
||||
};
|
||||
|
||||
ARTPEC-6 Development board:
|
||||
---------------------------
|
||||
Required root node properties:
|
||||
|
||||
@ -23,6 +23,12 @@ properties:
|
||||
- raspberrypi,4-model-b
|
||||
- const: brcm,bcm2711
|
||||
|
||||
- description: BCM2712 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- raspberrypi,5-model-b
|
||||
- const: brcm,bcm2712
|
||||
|
||||
- description: BCM2835 based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -27,16 +27,6 @@ Properties:
|
||||
- reg : Offset and length of the register set for the device
|
||||
|
||||
|
||||
* Alpine System-Fabric Service Registers
|
||||
|
||||
The System-Fabric Service Registers allow various operation on CPU and
|
||||
system fabric, like powering CPUs off.
|
||||
|
||||
Properties:
|
||||
- compatible : Should contain "al,alpine-sysfabric-service" and "syscon".
|
||||
- reg : Offset and length of the register set for the device
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
cpus {
|
||||
|
||||
@ -147,6 +147,7 @@ properties:
|
||||
- arm,cortex-a710
|
||||
- arm,cortex-a715
|
||||
- arm,cortex-a720
|
||||
- arm,cortex-a725
|
||||
- arm,cortex-m0
|
||||
- arm,cortex-m0+
|
||||
- arm,cortex-m1
|
||||
@ -161,10 +162,15 @@ properties:
|
||||
- arm,cortex-x2
|
||||
- arm,cortex-x3
|
||||
- arm,cortex-x4
|
||||
- arm,cortex-x925
|
||||
- arm,neoverse-e1
|
||||
- arm,neoverse-n1
|
||||
- arm,neoverse-n2
|
||||
- arm,neoverse-n3
|
||||
- arm,neoverse-v1
|
||||
- arm,neoverse-v2
|
||||
- arm,neoverse-v3
|
||||
- arm,neoverse-v3ae
|
||||
- brcm,brahma-b15
|
||||
- brcm,brahma-b53
|
||||
- brcm,vulcan
|
||||
|
||||
@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Freescale i.MX7ULP System Integration Module
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <anson.huang@nxp.com>
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
- Sascha Hauer <s.hauer@pengutronix.de>
|
||||
- Fabio Estevam <festevam@gmail.com>
|
||||
|
||||
description: |
|
||||
The system integration module (SIM) provides system control and chip configuration
|
||||
|
||||
@ -1,14 +0,0 @@
|
||||
Freescale Vybrid Miscellaneous System Control - CPU Configuration
|
||||
|
||||
The MSCM IP contains multiple sub modules, this binding describes the first
|
||||
block of registers which contains CPU configuration information.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,vf610-mscm-cpucfg", "syscon"
|
||||
- reg: the register range of the MSCM CPU configuration registers
|
||||
|
||||
Example:
|
||||
mscm_cpucfg: cpucfg@40001000 {
|
||||
compatible = "fsl,vf610-mscm-cpucfg", "syscon";
|
||||
reg = <0x40001000 0x800>;
|
||||
}
|
||||
@ -8,7 +8,6 @@ title: Freescale i.MX Platforms
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
- Li Yang <leoyang.li@nxp.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
@ -363,6 +362,12 @@ properties:
|
||||
- const: gw,ventana
|
||||
- const: fsl,imx6q
|
||||
|
||||
- description: i.MX6Q Kontron SMARC-sAMX6i on SMARC Eval Carrier 2.0
|
||||
items:
|
||||
- const: kontron,imx6q-samx6i-ads2
|
||||
- const: kontron,imx6q-samx6i
|
||||
- const: fsl,imx6q
|
||||
|
||||
- description: i.MX6Q PHYTEC phyBOARD-Mira
|
||||
items:
|
||||
- enum:
|
||||
@ -544,6 +549,12 @@ properties:
|
||||
- const: gw,ventana
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6DL Kontron SMARC-sAMX6i on SMARC Eval Carrier 2.0
|
||||
items:
|
||||
- const: kontron,imx6dl-samx6i-ads2
|
||||
- const: kontron,imx6dl-samx6i
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6DL PHYTEC phyBOARD-Mira
|
||||
items:
|
||||
- enum:
|
||||
@ -946,6 +957,13 @@ properties:
|
||||
- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: Compulab i.MX8MM UCM SoM based boards
|
||||
items:
|
||||
- enum:
|
||||
- compulab,imx8mm-iot-gateway # i.MX8MM Compulab IoT-Gateway
|
||||
- const: compulab,imx8mm-ucm-som # i.MX8MM Compulab UCM SoM
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: Emtop i.MX8MM based Boards
|
||||
items:
|
||||
- const: ees,imx8mm-emtop-baseboard # i.MX8MM Emtop SoM on i.MX8M Mini Baseboard V1
|
||||
@ -1145,8 +1163,9 @@ properties:
|
||||
version as an industrial computing device.
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL
|
||||
- const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM
|
||||
- tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL
|
||||
- tq,imx8mp-tqma8mpql-mba8mp-ras314 # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MP-RAS314
|
||||
- const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: i.MX8MQ based Boards
|
||||
@ -1272,9 +1291,16 @@ properties:
|
||||
- description: i.MX93 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board
|
||||
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
|
||||
- const: fsl,imx93
|
||||
|
||||
- description: i.MX95 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board
|
||||
- const: fsl,imx95
|
||||
|
||||
- description: i.MXRT1050 based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -20,7 +20,7 @@ description: |
|
||||
initialized early into boot process and provides services to Operating Systems
|
||||
on multiple processors including ones running Linux.
|
||||
|
||||
See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
|
||||
See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
|
||||
|
||||
The TI-SCI node describes the Texas Instrument's System Controller entity node.
|
||||
This parent node may optionally have additional children nodes which describe
|
||||
|
||||
@ -82,4 +82,22 @@ properties:
|
||||
- const: marvell,armada-ap807-quad
|
||||
- const: marvell,armada-ap807
|
||||
|
||||
- description:
|
||||
SolidRun CN9130 SoM based single-board computers
|
||||
items:
|
||||
- enum:
|
||||
- solidrun,cn9130-clearfog-base
|
||||
- solidrun,cn9130-clearfog-pro
|
||||
- solidrun,cn9131-solidwan
|
||||
- const: solidrun,cn9130-sr-som
|
||||
- const: marvell,cn9130
|
||||
|
||||
- description:
|
||||
SolidRun CN9132 COM-Express Type 7 based single-board computers
|
||||
items:
|
||||
- enum:
|
||||
- solidrun,cn9132-clearfog
|
||||
- const: solidrun,cn9132-sr-cex7
|
||||
- const: marvell,cn9130
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@ -5,18 +5,3 @@ Boards with a Marvell Dove SoC shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
- compatible: must contain "marvell,dove";
|
||||
|
||||
* Global Configuration registers
|
||||
|
||||
Global Configuration registers of Dove SoC are shared by a syscon node.
|
||||
|
||||
Required properties:
|
||||
- compatible: must contain "marvell,dove-global-config" and "syscon".
|
||||
- reg: base address and size of the Global Configuration registers.
|
||||
|
||||
Example:
|
||||
|
||||
gconf: global-config@e802c {
|
||||
compatible = "marvell,dove-global-config", "syscon";
|
||||
reg = <0xe802c 0x14>;
|
||||
};
|
||||
|
||||
@ -85,12 +85,15 @@ properties:
|
||||
- const: mediatek,mt7629
|
||||
- items:
|
||||
- enum:
|
||||
- cudy,wr3000-v1
|
||||
- openwrt,one
|
||||
- xiaomi,ax3000t
|
||||
- const: mediatek,mt7981b
|
||||
- items:
|
||||
- enum:
|
||||
- acelink,ew-7886cax
|
||||
- bananapi,bpi-r3
|
||||
- bananapi,bpi-r3mini
|
||||
- mediatek,mt7986a-rfb
|
||||
- const: mediatek,mt7986a
|
||||
- items:
|
||||
@ -293,6 +296,13 @@ properties:
|
||||
- const: google,tentacruel-sku327683
|
||||
- const: google,tentacruel
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Voltorb (Acer Chromebook 311 C723/C732T)
|
||||
items:
|
||||
- enum:
|
||||
- google,voltorb-sku589824
|
||||
- google,voltorb-sku589825
|
||||
- const: google,voltorb
|
||||
- const: mediatek,mt8186
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-evb
|
||||
@ -342,6 +352,14 @@ properties:
|
||||
- const: google,tomato-rev3
|
||||
- const: google,tomato
|
||||
- const: mediatek,mt8195
|
||||
- description: HP Dojo sku1, 3, 5, 7 (HP Chromebook x360 13b-ca0002sa)
|
||||
items:
|
||||
- const: google,dojo-sku7
|
||||
- const: google,dojo-sku5
|
||||
- const: google,dojo-sku3
|
||||
- const: google,dojo-sku1
|
||||
- const: google,dojo
|
||||
- const: mediatek,mt8195
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8195-demo
|
||||
@ -353,6 +371,12 @@ properties:
|
||||
- const: mediatek,mt8365
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8390-evk
|
||||
- const: mediatek,mt8390
|
||||
- const: mediatek,mt8188
|
||||
- items:
|
||||
- enum:
|
||||
- kontron,3-5-sbc-i1200
|
||||
- mediatek,mt8395-evk
|
||||
- radxa,nio-12l
|
||||
- const: mediatek,mt8395
|
||||
|
||||
@ -53,14 +53,20 @@ properties:
|
||||
- arm,cortex-a710-pmu
|
||||
- arm,cortex-a715-pmu
|
||||
- arm,cortex-a720-pmu
|
||||
- arm,cortex-a725-pmu
|
||||
- arm,cortex-x1-pmu
|
||||
- arm,cortex-x2-pmu
|
||||
- arm,cortex-x3-pmu
|
||||
- arm,cortex-x4-pmu
|
||||
- arm,cortex-x925-pmu
|
||||
- arm,neoverse-e1-pmu
|
||||
- arm,neoverse-n1-pmu
|
||||
- arm,neoverse-n2-pmu
|
||||
- arm,neoverse-n3-pmu
|
||||
- arm,neoverse-v1-pmu
|
||||
- arm,neoverse-v2-pmu
|
||||
- arm,neoverse-v3-pmu
|
||||
- arm,neoverse-v3ae-pmu
|
||||
- brcm,vulcan-pmu
|
||||
- cavium,thunder-pmu
|
||||
- nvidia,denver-pmu
|
||||
|
||||
@ -42,6 +42,7 @@ description: |
|
||||
msm8996
|
||||
msm8998
|
||||
qcs404
|
||||
qcs8550
|
||||
qcm2290
|
||||
qcm6490
|
||||
qdu1000
|
||||
@ -96,6 +97,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,apq8016-sbc
|
||||
- schneider,apq8016-hmibsc
|
||||
- const: qcom,apq8016
|
||||
|
||||
- items:
|
||||
@ -104,6 +106,7 @@ properties:
|
||||
- huawei,sturgeon
|
||||
- lg,lenok
|
||||
- samsung,matisse-wifi
|
||||
- samsung,milletwifi
|
||||
- const: qcom,apq8026
|
||||
|
||||
- items:
|
||||
@ -138,6 +141,7 @@ properties:
|
||||
- microsoft,makepeace
|
||||
- microsoft,moneypenny
|
||||
- motorola,falcon
|
||||
- samsung,ms013g
|
||||
- samsung,s3ve3g
|
||||
- const: qcom,msm8226
|
||||
|
||||
@ -175,6 +179,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- lge,hammerhead
|
||||
- samsung,hlte
|
||||
- sony,xperia-amami
|
||||
- sony,xperia-honami
|
||||
- const: qcom,msm8974
|
||||
@ -182,8 +187,10 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- fairphone,fp2
|
||||
- htc,m8
|
||||
- oneplus,bacon
|
||||
- samsung,klte
|
||||
- sony,xperia-aries
|
||||
- sony,xperia-castor
|
||||
- sony,xperia-leo
|
||||
- const: qcom,msm8974pro
|
||||
@ -203,8 +210,13 @@ properties:
|
||||
- asus,z00l
|
||||
- gplus,fl8005a
|
||||
- huawei,g7
|
||||
- lg,c50
|
||||
- lg,m216
|
||||
- longcheer,l8910
|
||||
- longcheer,l8150
|
||||
- motorola,harpia
|
||||
- motorola,osprey
|
||||
- motorola,surnia
|
||||
- qcom,msm8916-mtp
|
||||
- samsung,a3u-eur
|
||||
- samsung,a5u-eur
|
||||
@ -316,6 +328,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq5018-rdp432-c2
|
||||
- tplink,archer-ax55-v1
|
||||
- const: qcom,ipq5018
|
||||
|
||||
- items:
|
||||
@ -366,6 +379,7 @@ properties:
|
||||
- fairphone,fp5
|
||||
- qcom,qcm6490-idp
|
||||
- qcom,qcs6490-rb3gen2
|
||||
- shift,otter
|
||||
- const: qcom,qcm6490
|
||||
|
||||
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
|
||||
@ -802,6 +816,7 @@ properties:
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,tbx605f
|
||||
- motorola,ali
|
||||
- const: qcom,sdm450
|
||||
|
||||
@ -883,6 +898,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sa8775p-ride
|
||||
- qcom,sa8775p-ride-r3
|
||||
- const: qcom,sa8775p
|
||||
|
||||
- items:
|
||||
@ -1004,17 +1020,28 @@ properties:
|
||||
- qcom,sm8550-hdk
|
||||
- qcom,sm8550-mtp
|
||||
- qcom,sm8550-qrd
|
||||
- samsung,q5q
|
||||
- sony,pdx234
|
||||
- const: qcom,sm8550
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs8550-aim300-aiot
|
||||
- const: qcom,qcs8550-aim300
|
||||
- const: qcom,qcs8550
|
||||
- const: qcom,sm8550
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8650-hdk
|
||||
- qcom,sm8650-mtp
|
||||
- qcom,sm8650-qrd
|
||||
- const: qcom,sm8650
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- asus,vivobook-s15
|
||||
- lenovo,yoga-slim7x
|
||||
- qcom,x1e80100-crd
|
||||
- qcom,x1e80100-qcp
|
||||
- const: qcom,x1e80100
|
||||
|
||||
@ -248,6 +248,13 @@ properties:
|
||||
- const: friendlyarm,nanopc-t6
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: FriendlyElec CM3588-based boards
|
||||
items:
|
||||
- enum:
|
||||
- friendlyarm,cm3588-nas
|
||||
- const: friendlyarm,cm3588
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: GameForce Chi
|
||||
items:
|
||||
- const: gameforce,chi
|
||||
@ -627,6 +634,11 @@ properties:
|
||||
- const: mqmaker,miqi
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Neardi LBA3368
|
||||
items:
|
||||
- const: neardi,lba3368
|
||||
- const: rockchip,rk3368
|
||||
|
||||
- description: Netxeon R89 board
|
||||
items:
|
||||
- const: netxeon,r89
|
||||
@ -799,11 +811,21 @@ properties:
|
||||
- const: radxa,rock3a
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Radxa ROCK 3B
|
||||
items:
|
||||
- const: radxa,rock-3b
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Radxa ROCK 3C
|
||||
items:
|
||||
- const: radxa,rock-3c
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Radxa ROCK 5 ITX
|
||||
items:
|
||||
- const: radxa,rock-5-itx
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Radxa ROCK 5A
|
||||
items:
|
||||
- const: radxa,rock-5a
|
||||
@ -814,6 +836,18 @@ properties:
|
||||
- const: radxa,rock-5b
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Radxa ROCK S0
|
||||
items:
|
||||
- const: radxa,rock-s0
|
||||
- const: rockchip,rk3308
|
||||
|
||||
- description: Radxa ZERO 3W/3E
|
||||
items:
|
||||
- enum:
|
||||
- radxa,zero-3e
|
||||
- radxa,zero-3w
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Rikomagic MK808 v1
|
||||
items:
|
||||
- const: rikomagic,mk808
|
||||
@ -959,6 +993,14 @@ properties:
|
||||
- const: wolfvision,rk3568-pf5
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Xunlong Orange Pi 3B
|
||||
items:
|
||||
- enum:
|
||||
- xunlong,orangepi-3b-v1.1
|
||||
- xunlong,orangepi-3b-v2.1
|
||||
- const: xunlong,orangepi-3b
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Xunlong Orange Pi 5 Plus
|
||||
items:
|
||||
- const: xunlong,orangepi-5-plus
|
||||
|
||||
@ -1,19 +0,0 @@
|
||||
ARM Dual Cluster System Configuration Block
|
||||
-------------------------------------------
|
||||
|
||||
The Dual Cluster System Configuration Block (DCSCB) provides basic
|
||||
functionality for controlling clocks, resets and configuration pins in
|
||||
the Dual Cluster System implemented by the Real-Time System Model (RTSM).
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "arm,rtsm,dcscb"
|
||||
|
||||
- reg : physical base address and the size of the registers window
|
||||
|
||||
Example:
|
||||
|
||||
dcscb@60000000 {
|
||||
compatible = "arm,rtsm,dcscb";
|
||||
reg = <0x60000000 0x1000>;
|
||||
};
|
||||
@ -1,9 +0,0 @@
|
||||
SPEAr Misc configuration
|
||||
===========================
|
||||
SPEAr SOCs have some miscellaneous registers which are used to configure
|
||||
few properties of different peripheral controllers.
|
||||
|
||||
misc node required properties:
|
||||
|
||||
- compatible Should be "st,spear1340-misc", "syscon".
|
||||
- reg: Address range of misc space up to 8K
|
||||
@ -59,6 +59,12 @@ properties:
|
||||
- prt,prtt1s # Protonic PRTT1S
|
||||
- const: st,stm32mp151
|
||||
|
||||
- description: DH STM32MP135 DHCOR SoM based Boards
|
||||
items:
|
||||
- const: dh,stm32mp135f-dhcor-dhsbc
|
||||
- const: dh,stm32mp135f-dhcor-som
|
||||
- const: st,stm32mp135
|
||||
|
||||
- description: DH STM32MP151 DHCOR SoM based Boards
|
||||
items:
|
||||
- const: dh,stm32mp151a-dhcor-testbench
|
||||
|
||||
@ -708,12 +708,12 @@ properties:
|
||||
- const: olimex,a64-teres-i
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64
|
||||
- description: Pine64 PINE A64
|
||||
items:
|
||||
- const: pine64,pine64
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64+
|
||||
- description: Pine64 PINE A64+
|
||||
items:
|
||||
- const: pine64,pine64-plus
|
||||
- const: allwinner,sun50i-a64
|
||||
@ -724,17 +724,17 @@ properties:
|
||||
- const: sochip,s3
|
||||
- const: allwinner,sun8i-v3
|
||||
|
||||
- description: Pine64 PineH64 model A
|
||||
- description: Pine64 PINE H64 Model A
|
||||
items:
|
||||
- const: pine64,pine-h64
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: Pine64 PineH64 model B
|
||||
- description: Pine64 PINE H64 Model B
|
||||
items:
|
||||
- const: pine64,pine-h64-model-b
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: Pine64 LTS
|
||||
- description: Pine64 PINE A64 LTS
|
||||
items:
|
||||
- const: pine64,pine64-lts
|
||||
- const: allwinner,sun50i-r18
|
||||
@ -763,17 +763,17 @@ properties:
|
||||
- const: pine64,pinephone
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PineTab, Development Sample
|
||||
- description: Pine64 PineTab Developer Sample
|
||||
items:
|
||||
- const: pine64,pinetab
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PineTab, Early Adopter's batch (and maybe later ones)
|
||||
- description: Pine64 PineTab Early Adopter
|
||||
items:
|
||||
- const: pine64,pinetab-early-adopter
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 SoPine Baseboard
|
||||
- description: Pine64 SOPINE
|
||||
items:
|
||||
- const: pine64,sopine-baseboard
|
||||
- const: pine64,sopine
|
||||
|
||||
@ -25,6 +25,12 @@ properties:
|
||||
- ti,am62a7-sk
|
||||
- const: ti,am62a7
|
||||
|
||||
- description: K3 AM62A7 SoC PHYTEC phyBOARD-Lyra
|
||||
items:
|
||||
- const: phytec,am62a7-phyboard-lyra-rdk
|
||||
- const: phytec,am62a-phycore-som
|
||||
- const: ti,am62a7
|
||||
|
||||
- description: K3 AM62P5 SoC and Boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -1,21 +0,0 @@
|
||||
Binding for Freescale QorIQ AHCI SATA Controller
|
||||
|
||||
Required properties:
|
||||
- reg: Physical base address and size of the controller's register area.
|
||||
- compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
|
||||
chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc.
|
||||
- clocks: Input clock specifier. Refer to common clock bindings.
|
||||
- interrupts: Interrupt specifier. Refer to interrupt binding.
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent: Enable AHCI coherent DMA operation.
|
||||
- reg-names: register area names when there are more than 1 register area.
|
||||
|
||||
Examples:
|
||||
sata@3200000 {
|
||||
compatible = "fsl,ls1021a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&platform_clk 1>;
|
||||
dma-coherent;
|
||||
};
|
||||
64
dts/upstream/Bindings/ata/fsl,ahci.yaml
Normal file
64
dts/upstream/Bindings/ata/fsl,ahci.yaml
Normal file
@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/fsl,ahci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale QorIQ AHCI SATA Controller
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: SATA controller for ls1012a
|
||||
items:
|
||||
- const: fsl,ls1012a-ahci
|
||||
- const: fsl,ls1043a-ahci
|
||||
- enum:
|
||||
- fsl,ls1021a-ahci
|
||||
- fsl,ls1028a-ahci
|
||||
- fsl,ls1043a-ahci
|
||||
- fsl,ls1046a-ahci
|
||||
- fsl,ls1088a-ahci
|
||||
- fsl,ls2080a-ahci
|
||||
- fsl,lx2160a-ahci
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: ahci
|
||||
- const: sata-ecc
|
||||
minItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
sata@3200000 {
|
||||
compatible = "fsl,ls1021a-ahci";
|
||||
reg = <0x3200000 0x10000>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&platform_clk 1>;
|
||||
dma-coherent;
|
||||
};
|
||||
@ -35,6 +35,9 @@ properties:
|
||||
ports-implemented:
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
sata-port@0:
|
||||
$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
|
||||
|
||||
|
||||
57
dts/upstream/Bindings/cache/qcom,llcc.yaml
vendored
57
dts/upstream/Bindings/cache/qcom,llcc.yaml
vendored
@ -21,6 +21,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qdu1000-llcc
|
||||
- qcom,sa8775p-llcc
|
||||
- qcom,sc7180-llcc
|
||||
- qcom,sc7280-llcc
|
||||
- qcom,sc8180x-llcc
|
||||
@ -79,6 +80,33 @@ allOf:
|
||||
- const: llcc0_base
|
||||
- const: llcc_broadcast_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sa8775p-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC0 base register region
|
||||
- description: LLCC1 base register region
|
||||
- description: LLCC2 base register region
|
||||
- description: LLCC3 base register region
|
||||
- description: LLCC4 base register region
|
||||
- description: LLCC5 base register region
|
||||
- description: LLCC broadcast base register region
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
- const: llcc1_base
|
||||
- const: llcc2_base
|
||||
- const: llcc3_base
|
||||
- const: llcc4_base
|
||||
- const: llcc5_base
|
||||
- const: llcc_broadcast_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
@ -141,8 +169,6 @@ allOf:
|
||||
- qcom,sm8150-llcc
|
||||
- qcom,sm8250-llcc
|
||||
- qcom,sm8350-llcc
|
||||
- qcom,sm8450-llcc
|
||||
- qcom,sm8550-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
@ -160,6 +186,33 @@ allOf:
|
||||
- const: llcc3_base
|
||||
- const: llcc_broadcast_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sm8450-llcc
|
||||
- qcom,sm8550-llcc
|
||||
- qcom,sm8650-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC0 base register region
|
||||
- description: LLCC1 base register region
|
||||
- description: LLCC2 base register region
|
||||
- description: LLCC3 base register region
|
||||
- description: LLCC broadcast OR register region
|
||||
- description: LLCC broadcast AND register region
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
- const: llcc1_base
|
||||
- const: llcc2_base
|
||||
- const: llcc3_base
|
||||
- const: llcc_broadcast_base
|
||||
- const: llcc_broadcast_and_base
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
66
dts/upstream/Bindings/cache/starfive,jh8100-starlink-cache.yaml
vendored
Normal file
66
dts/upstream/Bindings/cache/starfive,jh8100-starlink-cache.yaml
vendored
Normal file
@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive StarLink Cache Controller
|
||||
|
||||
maintainers:
|
||||
- Joshua Yeong <joshua.yeong@starfivetech.com>
|
||||
|
||||
description:
|
||||
StarFive's StarLink Cache Controller manages the L3 cache shared between
|
||||
clusters of CPU cores. The cache driver enables RISC-V non-standard cache
|
||||
management as an alternative to instructions in the RISC-V Zicbom extension.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/cache-controller.yaml#
|
||||
|
||||
# We need a select here so we don't match all nodes with 'cache'
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- starfive,jh8100-starlink-cache
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: starfive,jh8100-starlink-cache
|
||||
- const: cache
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- cache-block-size
|
||||
- cache-level
|
||||
- cache-sets
|
||||
- cache-size
|
||||
- cache-unified
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cache-controller@15000000 {
|
||||
compatible = "starfive,jh8100-starlink-cache", "cache";
|
||||
reg = <0x0 0x15000000 0x0 0x278>;
|
||||
cache-block-size = <64>;
|
||||
cache-level = <3>;
|
||||
cache-sets = <8192>;
|
||||
cache-size = <0x400000>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
@ -35,7 +35,7 @@ properties:
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
maxItems: 4
|
||||
|
||||
"#clock-cells":
|
||||
description:
|
||||
@ -43,6 +43,10 @@ properties:
|
||||
clocks.
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
description: ID of the controller reset line
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -60,6 +64,8 @@ allOf:
|
||||
- description: scu base address
|
||||
- description: misc scu base address
|
||||
|
||||
'#reset-cells': false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
@ -70,6 +76,7 @@ allOf:
|
||||
items:
|
||||
- description: scu base address
|
||||
- description: misc scu base address
|
||||
- description: reset base address
|
||||
- description: pb scu base address
|
||||
|
||||
additionalProperties: false
|
||||
@ -83,3 +90,19 @@ examples:
|
||||
<0x1fb00000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
scuclk: clock-controller@1fa20000 {
|
||||
compatible = "airoha,en7581-scu";
|
||||
reg = <0x0 0x1fa20000 0x0 0x400>,
|
||||
<0x0 0x1fb00000 0x0 0x90>,
|
||||
<0x0 0x1fb00830 0x0 0x8>,
|
||||
<0x0 0x1fbe3400 0x0 0xfc>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -30,6 +30,8 @@ properties:
|
||||
- description: input fixed pll div7
|
||||
- description: input hifi pll
|
||||
- description: input oscillator (usually at 24MHz)
|
||||
- description: input sys pll
|
||||
minItems: 6 # sys_pll is optional
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
@ -39,6 +41,8 @@ properties:
|
||||
- const: fclk_div7
|
||||
- const: hifi_pll
|
||||
- const: xtal
|
||||
- const: sys_pll
|
||||
minItems: 6 # sys_pll is optional
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -65,9 +69,10 @@ examples:
|
||||
<&clkc_pll CLKID_FCLK_DIV5>,
|
||||
<&clkc_pll CLKID_FCLK_DIV7>,
|
||||
<&clkc_pll CLKID_HIFI_PLL>,
|
||||
<&xtal>;
|
||||
<&xtal>,
|
||||
<&clkc_pll CLKID_SYS_PLL>;
|
||||
clock-names = "fclk_div2", "fclk_div3",
|
||||
"fclk_div5", "fclk_div7",
|
||||
"hifi_pll", "xtal";
|
||||
"hifi_pll", "xtal", "sys_pll";
|
||||
};
|
||||
};
|
||||
|
||||
@ -26,11 +26,15 @@ properties:
|
||||
items:
|
||||
- description: input fixpll_in
|
||||
- description: input hifipll_in
|
||||
- description: input syspll_in
|
||||
minItems: 2 # syspll_in is optional
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: fixpll_in
|
||||
- const: hifipll_in
|
||||
- const: syspll_in
|
||||
minItems: 2 # syspll_in is optional
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -53,7 +57,8 @@ examples:
|
||||
reg = <0 0x7c80 0 0x18c>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
|
||||
<&clkc_periphs CLKID_HIFIPLL_IN>;
|
||||
clock-names = "fixpll_in", "hifipll_in";
|
||||
<&clkc_periphs CLKID_HIFIPLL_IN>,
|
||||
<&clkc_periphs CLKID_SYSPLL_IN>;
|
||||
clock-names = "fixpll_in", "hifipll_in", "syspll_in";
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,59 +0,0 @@
|
||||
* Amlogic AXG Audio Clock Controllers
|
||||
|
||||
The Amlogic AXG audio clock controller generates and supplies clock to the
|
||||
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
|
||||
devices.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
|
||||
"amlogic,g12a-audio-clkc" for G12A,
|
||||
"amlogic,sm1-audio-clkc" for S905X3.
|
||||
- reg : physical base address of the clock controller and length of
|
||||
memory mapped region.
|
||||
- clocks : a list of phandle + clock-specifier pairs for the clocks listed
|
||||
in clock-names.
|
||||
- clock-names : must contain the following:
|
||||
* "pclk" - Main peripheral bus clock
|
||||
may contain the following:
|
||||
* "mst_in[0-7]" - 8 input plls to generate clock signals
|
||||
* "slv_sclk[0-9]" - 10 slave bit clocks provided by external
|
||||
components.
|
||||
* "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
|
||||
components.
|
||||
- resets : phandle of the internal reset line
|
||||
- #clock-cells : should be 1.
|
||||
- #reset-cells : should be 1 on the g12a (and following) soc family
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
|
||||
used in device tree sources.
|
||||
|
||||
Example:
|
||||
|
||||
clkc_audio: clock-controller@0 {
|
||||
compatible = "amlogic,axg-audio-clkc";
|
||||
reg = <0x0 0x0 0x0 0xb4>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&clkc CLKID_AUDIO>,
|
||||
<&clkc CLKID_MPLL0>,
|
||||
<&clkc CLKID_MPLL1>,
|
||||
<&clkc CLKID_MPLL2>,
|
||||
<&clkc CLKID_MPLL3>,
|
||||
<&clkc CLKID_HIFI_PLL>,
|
||||
<&clkc CLKID_FCLK_DIV3>,
|
||||
<&clkc CLKID_FCLK_DIV4>,
|
||||
<&clkc CLKID_GP0_PLL>;
|
||||
clock-names = "pclk",
|
||||
"mst_in0",
|
||||
"mst_in1",
|
||||
"mst_in2",
|
||||
"mst_in3",
|
||||
"mst_in4",
|
||||
"mst_in5",
|
||||
"mst_in6",
|
||||
"mst_in7";
|
||||
resets = <&reset RESET_AUDIO>;
|
||||
};
|
||||
201
dts/upstream/Bindings/clock/amlogic,axg-audio-clkc.yaml
Normal file
201
dts/upstream/Bindings/clock/amlogic,axg-audio-clkc.yaml
Normal file
@ -0,0 +1,201 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic AXG Audio Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Jerome Brunet <jbrunet@baylibre.com>
|
||||
|
||||
description:
|
||||
The Amlogic AXG audio clock controller generates and supplies clock to the
|
||||
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
|
||||
devices.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,axg-audio-clkc
|
||||
- amlogic,g12a-audio-clkc
|
||||
- amlogic,sm1-audio-clkc
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: main peripheral bus clock
|
||||
- description: input plls to generate clock signals N0
|
||||
- description: input plls to generate clock signals N1
|
||||
- description: input plls to generate clock signals N2
|
||||
- description: input plls to generate clock signals N3
|
||||
- description: input plls to generate clock signals N4
|
||||
- description: input plls to generate clock signals N5
|
||||
- description: input plls to generate clock signals N6
|
||||
- description: input plls to generate clock signals N7
|
||||
- description: slave bit clock N0 provided by external components
|
||||
- description: slave bit clock N1 provided by external components
|
||||
- description: slave bit clock N2 provided by external components
|
||||
- description: slave bit clock N3 provided by external components
|
||||
- description: slave bit clock N4 provided by external components
|
||||
- description: slave bit clock N5 provided by external components
|
||||
- description: slave bit clock N6 provided by external components
|
||||
- description: slave bit clock N7 provided by external components
|
||||
- description: slave bit clock N8 provided by external components
|
||||
- description: slave bit clock N9 provided by external components
|
||||
- description: slave sample clock N0 provided by external components
|
||||
- description: slave sample clock N1 provided by external components
|
||||
- description: slave sample clock N2 provided by external components
|
||||
- description: slave sample clock N3 provided by external components
|
||||
- description: slave sample clock N4 provided by external components
|
||||
- description: slave sample clock N5 provided by external components
|
||||
- description: slave sample clock N6 provided by external components
|
||||
- description: slave sample clock N7 provided by external components
|
||||
- description: slave sample clock N8 provided by external components
|
||||
- description: slave sample clock N9 provided by external components
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: pclk
|
||||
- const: mst_in0
|
||||
- const: mst_in1
|
||||
- const: mst_in2
|
||||
- const: mst_in3
|
||||
- const: mst_in4
|
||||
- const: mst_in5
|
||||
- const: mst_in6
|
||||
- const: mst_in7
|
||||
- const: slv_sclk0
|
||||
- const: slv_sclk1
|
||||
- const: slv_sclk2
|
||||
- const: slv_sclk3
|
||||
- const: slv_sclk4
|
||||
- const: slv_sclk5
|
||||
- const: slv_sclk6
|
||||
- const: slv_sclk7
|
||||
- const: slv_sclk8
|
||||
- const: slv_sclk9
|
||||
- const: slv_lrclk0
|
||||
- const: slv_lrclk1
|
||||
- const: slv_lrclk2
|
||||
- const: slv_lrclk3
|
||||
- const: slv_lrclk4
|
||||
- const: slv_lrclk5
|
||||
- const: slv_lrclk6
|
||||
- const: slv_lrclk7
|
||||
- const: slv_lrclk8
|
||||
- const: slv_lrclk9
|
||||
|
||||
resets:
|
||||
description: internal reset line
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- amlogic,g12a-audio-clkc
|
||||
- amlogic,sm1-audio-clkc
|
||||
then:
|
||||
required:
|
||||
- '#reset-cells'
|
||||
else:
|
||||
properties:
|
||||
'#reset-cells': false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/axg-clkc.h>
|
||||
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
|
||||
apb {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clkc_audio: clock-controller@0 {
|
||||
compatible = "amlogic,axg-audio-clkc";
|
||||
reg = <0x0 0x0 0x0 0xb4>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&clkc CLKID_AUDIO>,
|
||||
<&clkc CLKID_MPLL0>,
|
||||
<&clkc CLKID_MPLL1>,
|
||||
<&clkc CLKID_MPLL2>,
|
||||
<&clkc CLKID_MPLL3>,
|
||||
<&clkc CLKID_HIFI_PLL>,
|
||||
<&clkc CLKID_FCLK_DIV3>,
|
||||
<&clkc CLKID_FCLK_DIV4>,
|
||||
<&clkc CLKID_GP0_PLL>,
|
||||
<&slv_sclk0>,
|
||||
<&slv_sclk1>,
|
||||
<&slv_sclk2>,
|
||||
<&slv_sclk3>,
|
||||
<&slv_sclk4>,
|
||||
<&slv_sclk5>,
|
||||
<&slv_sclk6>,
|
||||
<&slv_sclk7>,
|
||||
<&slv_sclk8>,
|
||||
<&slv_sclk9>,
|
||||
<&slv_lrclk0>,
|
||||
<&slv_lrclk1>,
|
||||
<&slv_lrclk2>,
|
||||
<&slv_lrclk3>,
|
||||
<&slv_lrclk4>,
|
||||
<&slv_lrclk5>,
|
||||
<&slv_lrclk6>,
|
||||
<&slv_lrclk7>,
|
||||
<&slv_lrclk8>,
|
||||
<&slv_lrclk9>;
|
||||
clock-names = "pclk",
|
||||
"mst_in0",
|
||||
"mst_in1",
|
||||
"mst_in2",
|
||||
"mst_in3",
|
||||
"mst_in4",
|
||||
"mst_in5",
|
||||
"mst_in6",
|
||||
"mst_in7",
|
||||
"slv_sclk0",
|
||||
"slv_sclk1",
|
||||
"slv_sclk2",
|
||||
"slv_sclk3",
|
||||
"slv_sclk4",
|
||||
"slv_sclk5",
|
||||
"slv_sclk6",
|
||||
"slv_sclk7",
|
||||
"slv_sclk8",
|
||||
"slv_sclk9",
|
||||
"slv_lrclk0",
|
||||
"slv_lrclk1",
|
||||
"slv_lrclk2",
|
||||
"slv_lrclk3",
|
||||
"slv_lrclk4",
|
||||
"slv_lrclk5",
|
||||
"slv_lrclk6",
|
||||
"slv_lrclk7",
|
||||
"slv_lrclk8",
|
||||
"slv_lrclk9";
|
||||
resets = <&reset RESET_AUDIO>;
|
||||
};
|
||||
};
|
||||
120
dts/upstream/Bindings/clock/amlogic,c3-peripherals-clkc.yaml
Normal file
120
dts/upstream/Bindings/clock/amlogic,c3-peripherals-clkc.yaml
Normal file
@ -0,0 +1,120 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic C3 series Peripheral Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Jerome Brunet <jbrunet@baylibre.com>
|
||||
- Xianwei Zhao <xianwei.zhao@amlogic.com>
|
||||
- Chuan Liu <chuan.liu@amlogic.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: amlogic,c3-peripherals-clkc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 16
|
||||
items:
|
||||
- description: input oscillator (usually at 24MHz)
|
||||
- description: input oscillators multiplexer
|
||||
- description: input fix pll
|
||||
- description: input fclk div 2
|
||||
- description: input fclk div 2p5
|
||||
- description: input fclk div 3
|
||||
- description: input fclk div 4
|
||||
- description: input fclk div 5
|
||||
- description: input fclk div 7
|
||||
- description: input gp0 pll
|
||||
- description: input gp1 pll
|
||||
- description: input hifi pll
|
||||
- description: input sys clk
|
||||
- description: input axi clk
|
||||
- description: input sys pll div 16
|
||||
- description: input cpu clk div 16
|
||||
- description: input pad clock for rtc clk (optional)
|
||||
|
||||
clock-names:
|
||||
minItems: 16
|
||||
items:
|
||||
- const: xtal_24m
|
||||
- const: oscin
|
||||
- const: fix
|
||||
- const: fdiv2
|
||||
- const: fdiv2p5
|
||||
- const: fdiv3
|
||||
- const: fdiv4
|
||||
- const: fdiv5
|
||||
- const: fdiv7
|
||||
- const: gp0
|
||||
- const: gp1
|
||||
- const: hifi
|
||||
- const: sysclk
|
||||
- const: axiclk
|
||||
- const: sysplldiv16
|
||||
- const: cpudiv16
|
||||
- const: pad_osc
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
apb {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@0 {
|
||||
compatible = "amlogic,c3-peripherals-clkc";
|
||||
reg = <0x0 0x0 0x0 0x49c>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal_24m>,
|
||||
<&scmi_clk 8>,
|
||||
<&scmi_clk 12>,
|
||||
<&clkc_pll 3>,
|
||||
<&clkc_pll 5>,
|
||||
<&clkc_pll 7>,
|
||||
<&clkc_pll 9>,
|
||||
<&clkc_pll 11>,
|
||||
<&clkc_pll 13>,
|
||||
<&clkc_pll 15>,
|
||||
<&scmi_clk 13>,
|
||||
<&clkc_pll 17>,
|
||||
<&scmi_clk 9>,
|
||||
<&scmi_clk 10>,
|
||||
<&scmi_clk 14>,
|
||||
<&scmi_clk 15>;
|
||||
clock-names = "xtal_24m",
|
||||
"oscin",
|
||||
"fix",
|
||||
"fdiv2",
|
||||
"fdiv2p5",
|
||||
"fdiv3",
|
||||
"fdiv4",
|
||||
"fdiv5",
|
||||
"fdiv7",
|
||||
"gp0",
|
||||
"gp1",
|
||||
"hifi",
|
||||
"sysclk",
|
||||
"axiclk",
|
||||
"sysplldiv16",
|
||||
"cpudiv16";
|
||||
};
|
||||
};
|
||||
59
dts/upstream/Bindings/clock/amlogic,c3-pll-clkc.yaml
Normal file
59
dts/upstream/Bindings/clock/amlogic,c3-pll-clkc.yaml
Normal file
@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic C3 series PLL Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Jerome Brunet <jbrunet@baylibre.com>
|
||||
- Chuan Liu <chuan.liu@amlogic.com>
|
||||
- Xianwei Zhao <xianwei.zhao@amlogic.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: amlogic,c3-pll-clkc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: input top pll
|
||||
- description: input mclk pll
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: top
|
||||
- const: mclk
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
apb {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@8000 {
|
||||
compatible = "amlogic,c3-pll-clkc";
|
||||
reg = <0x0 0x8000 0x0 0x1a4>;
|
||||
clocks = <&scmi_clk 2>,
|
||||
<&scmi_clk 5>;
|
||||
clock-names = "top", "mclk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
84
dts/upstream/Bindings/clock/fsl,qoriq-clock-legacy.yaml
Normal file
84
dts/upstream/Bindings/clock/fsl,qoriq-clock-legacy.yaml
Normal file
@ -0,0 +1,84 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Legacy Clock Block on Freescale QorIQ Platforms
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
description: |
|
||||
These nodes are deprecated. Kernels should continue to support
|
||||
device trees with these nodes, but new device trees should not use them.
|
||||
|
||||
Most of the bindings are from the common clock binding[1].
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,qoriq-core-pll-1.0
|
||||
- fsl,qoriq-core-pll-2.0
|
||||
- fsl,qoriq-core-mux-1.0
|
||||
- fsl,qoriq-core-mux-2.0
|
||||
- fsl,qoriq-sysclk-1.0
|
||||
- fsl,qoriq-sysclk-2.0
|
||||
- fsl,qoriq-platform-pll-1.0
|
||||
- fsl,qoriq-platform-pll-2.0
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
clock-output-names:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
'#clock-cells':
|
||||
minimum: 0
|
||||
maximum: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,qoriq-sysclk-1.0
|
||||
- fsl,qoriq-sysclk-2.0
|
||||
then:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,qoriq-core-pll-1.0
|
||||
- fsl,qoriq-core-pll-2.0
|
||||
then:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description: |
|
||||
* 0 - equal to the PLL frequency
|
||||
* 1 - equal to the PLL frequency divided by 2
|
||||
* 2 - equal to the PLL frequency divided by 4
|
||||
|
||||
207
dts/upstream/Bindings/clock/fsl,qoriq-clock.yaml
Normal file
207
dts/upstream/Bindings/clock/fsl,qoriq-clock.yaml
Normal file
@ -0,0 +1,207 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock Block on Freescale QorIQ Platforms
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
description: |
|
||||
Freescale QorIQ chips take primary clocking input from the external
|
||||
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
|
||||
multiple phase locked loops (PLL) to create a variety of frequencies
|
||||
which can then be passed to a variety of internal logic, including
|
||||
cores and peripheral IP blocks.
|
||||
Please refer to the Reference Manual for details.
|
||||
|
||||
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
|
||||
which the chip complies.
|
||||
|
||||
Chassis Version Example Chips
|
||||
--------------- -------------
|
||||
1.0 p4080, p5020, p5040
|
||||
2.0 t4240
|
||||
|
||||
Clock Provider
|
||||
|
||||
The clockgen node should act as a clock provider, though in older device
|
||||
trees the children of the clockgen node are the clock providers.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,p2041-clockgen
|
||||
- fsl,p3041-clockgen
|
||||
- fsl,p4080-clockgen
|
||||
- fsl,p5020-clockgen
|
||||
- fsl,p5040-clockgen
|
||||
- const: fsl,qoriq-clockgen-1.0
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,t1023-clockgen
|
||||
- fsl,t1024-clockgen
|
||||
- fsl,t1040-clockgen
|
||||
- fsl,t1042-clockgen
|
||||
- fsl,t2080-clockgen
|
||||
- fsl,t2081-clockgen
|
||||
- fsl,t4240-clockgen
|
||||
- const: fsl,qoriq-clockgen-2.0
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,b4420-clockgen
|
||||
- fsl,b4860-clockgen
|
||||
- const: fsl,b4-clockgen
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,ls1012a-clockgen
|
||||
- fsl,ls1021a-clockgen
|
||||
- fsl,ls1028a-clockgen
|
||||
- fsl,ls1043a-clockgen
|
||||
- fsl,ls1046a-clockgen
|
||||
- fsl,ls1088a-clockgen
|
||||
- fsl,ls2080a-clockgen
|
||||
- fsl,lx2160a-clockgen
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ranges: true
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 2
|
||||
description: |
|
||||
The first cell of the clock specifier is the clock type, and the
|
||||
second cell is the clock index for the specified type.
|
||||
|
||||
Type# Name Index Cell
|
||||
0 sysclk must be 0
|
||||
1 cmux index (n in CLKCnCSR)
|
||||
2 hwaccel index (n in CLKCGnHWACSR)
|
||||
3 fman 0 for fm1, 1 for fm2
|
||||
4 platform pll n=pll/(n+1). For example, when n=1,
|
||||
that means output_freq=PLL_freq/2.
|
||||
5 coreclk must be 0
|
||||
|
||||
clock-frequency:
|
||||
description: Input system clock frequency (SYSCLK)
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description:
|
||||
sysclk may be provided as an input clock. Either clock-frequency
|
||||
or clocks must be provided.
|
||||
- description:
|
||||
A second input clock, called "coreclk", may be provided if
|
||||
core PLLs are based on a different input clock from the
|
||||
platform PLL.
|
||||
minItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: sysclk
|
||||
- const: coreclk
|
||||
|
||||
patternProperties:
|
||||
'^mux[0-9]@[a-f0-9]+$':
|
||||
deprecated: true
|
||||
$ref: fsl,qoriq-clock-legacy.yaml
|
||||
|
||||
'^sysclk(-[a-z0-9]+)?$':
|
||||
deprecated: true
|
||||
$ref: fsl,qoriq-clock-legacy.yaml
|
||||
|
||||
'^pll[0-9]@[a-f0-9]+$':
|
||||
deprecated: true
|
||||
$ref: fsl,qoriq-clock-legacy.yaml
|
||||
|
||||
'^platform\-pll@[a-f0-9]+$':
|
||||
deprecated: true
|
||||
$ref: fsl,qoriq-clock-legacy.yaml
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
/* clock provider example */
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <133333333>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
- |
|
||||
/* Legacy example */
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
clock-frequency = <133333333>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#clock-cells = <2>;
|
||||
|
||||
sysclk: sysclk {
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
reg = <0x800 0x4>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
reg = <0x820 0x4>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
reg = <0x0 0x4>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
reg = <0x20 0x4>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
|
||||
platform-pll@c00 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0xc00 0x4>;
|
||||
compatible = "fsl,qoriq-platform-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "platform-pll", "platform-pll-div2";
|
||||
};
|
||||
};
|
||||
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Freescale i.MX6 Quad Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
- Abel Vesa <abelvesa@kernel.org>
|
||||
- Peng Fan <peng.fan@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Freescale i.MX6 SoloLite Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
- Abel Vesa <abelvesa@kernel.org>
|
||||
- Peng Fan <peng.fan@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Freescale i.MX6 SLL Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
- Abel Vesa <abelvesa@kernel.org>
|
||||
- Peng Fan <peng.fan@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Freescale i.MX6 SoloX Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
- Abel Vesa <abelvesa@kernel.org>
|
||||
- Peng Fan <peng.fan@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Freescale i.MX6 UltraLite Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
- Abel Vesa <abelvesa@kernel.org>
|
||||
- Peng Fan <peng.fan@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -8,7 +8,6 @@ title: Freescale i.MX7 Dual Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
|
||||
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: NXP i.MX8M Family Clock Control Module
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
- Abel Vesa <abelvesa@kernel.org>
|
||||
- Peng Fan <peng.fan@nxp.com>
|
||||
|
||||
description: |
|
||||
NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock
|
||||
|
||||
@ -14,9 +14,11 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt7622-pciesys
|
||||
- mediatek,mt7629-pciesys
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt7622-pciesys
|
||||
- const: syscon
|
||||
- const: mediatek,mt7629-pciesys
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -38,7 +40,7 @@ additionalProperties: false
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1a100800 {
|
||||
compatible = "mediatek,mt7622-pciesys";
|
||||
compatible = "mediatek,mt7622-pciesys", "syscon";
|
||||
reg = <0x1a100800 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
@ -39,6 +39,9 @@ properties:
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -40,38 +40,11 @@ required:
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node:
|
||||
- |
|
||||
m10v-clk-ctrl@1d021000 {
|
||||
clock-controller@1d021000 {
|
||||
compatible = "socionext,milbeaut-m10v-ccu";
|
||||
reg = <0x1d021000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clki40mhz>;
|
||||
};
|
||||
|
||||
# Required an external clock for Clock controller node:
|
||||
- |
|
||||
clocks {
|
||||
clki40mhz: clki40mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <40000000>;
|
||||
};
|
||||
/* other clocks */
|
||||
};
|
||||
|
||||
# The clock consumer shall specify the desired clock-output of the clock
|
||||
# controller as below by specifying output-id in its "clk" phandle cell.
|
||||
# 2: uart
|
||||
# 4: 32-bit timer
|
||||
# 7: UHS-I/II
|
||||
- |
|
||||
serial@1e700010 {
|
||||
compatible = "socionext,milbeaut-usio-uart";
|
||||
reg = <0x1e700010 0x10>;
|
||||
interrupts = <0 141 0x4>, <0 149 0x4>;
|
||||
interrupt-names = "rx", "tx";
|
||||
clocks = <&clk 2>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
@ -40,31 +40,19 @@ properties:
|
||||
- description: DSI 1 PLL byte clock
|
||||
- description: DSI 1 PLL DSI clock
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: MMCX power domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm Display Clock & Reset Controller on SM6350
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
@ -37,28 +37,16 @@ properties:
|
||||
- const: dp_phy_pll_link_clk
|
||||
- const: dp_phy_pll_vco_div_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -27,6 +27,7 @@ properties:
|
||||
- qcom,sm8350-dispcc
|
||||
|
||||
clocks:
|
||||
minItems: 7
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Byte clock from DSI PHY0
|
||||
@ -35,8 +36,15 @@ properties:
|
||||
- description: Pixel clock from DSI PHY1
|
||||
- description: Link clock from DP PHY
|
||||
- description: VCO DIV clock from DP PHY
|
||||
- description: Link clock from eDP PHY
|
||||
- description: VCO DIV clock from eDP PHY
|
||||
- description: Link clock from DP1 PHY
|
||||
- description: VCO DIV clock from DP1 PHY
|
||||
- description: Link clock from DP2 PHY
|
||||
- description: VCO DIV clock from DP2 PHY
|
||||
|
||||
clock-names:
|
||||
minItems: 7
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: dsi0_phy_pll_out_byteclk
|
||||
@ -45,18 +53,12 @@ properties:
|
||||
- const: dsi1_phy_pll_out_dsiclk
|
||||
- const: dp_phy_pll_link_clk
|
||||
- const: dp_phy_pll_vco_div_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
- const: edp_phy_pll_link_clk
|
||||
- const: edp_phy_pll_vco_div_clk
|
||||
- const: dptx1_phy_pll_link_clk
|
||||
- const: dptx1_phy_pll_vco_div_clk
|
||||
- const: dptx2_phy_pll_link_clk
|
||||
- const: dptx2_phy_pll_vco_div_clk
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
@ -70,14 +72,26 @@ properties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,sc8180x-dispcc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
maxItems: 7
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -69,6 +69,8 @@ properties:
|
||||
const: 1
|
||||
deprecated: true
|
||||
|
||||
'#power-domain-cells': false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -81,7 +83,6 @@ examples:
|
||||
reg = <0x00900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
thermal-sensor {
|
||||
compatible = "qcom,msm8960-tsens";
|
||||
|
||||
@ -51,6 +51,7 @@ properties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
||||
@ -34,6 +34,8 @@ properties:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
|
||||
'#power-domain-cells': false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -45,7 +47,6 @@ examples:
|
||||
compatible = "qcom,gcc-ipq4019";
|
||||
reg = <0x1800000 0x60000>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&xo>, <&sleep_clk>;
|
||||
clock-names = "xo", "sleep_clk";
|
||||
|
||||
@ -36,6 +36,8 @@ properties:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
|
||||
'#power-domain-cells': false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
@ -51,7 +53,6 @@ examples:
|
||||
clocks = <&xo>, <&sleep_clk>;
|
||||
clock-names = "xo", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
||||
@ -46,6 +46,8 @@ properties:
|
||||
allOf:
|
||||
- $ref: /schemas/thermal/qcom-tsens.yaml#
|
||||
|
||||
'#power-domain-cells': false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
@ -65,7 +67,6 @@ examples:
|
||||
clock-names = "pxo", "cxo", "pll4";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
tsens: thermal-sensor {
|
||||
compatible = "qcom,ipq8064-tsens";
|
||||
|
||||
@ -39,6 +39,7 @@ properties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9607.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller
|
||||
@ -15,7 +15,6 @@ description: |
|
||||
domains.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
include/dt-bindings/clock/qcom,gcc-mdm9607.h
|
||||
|
||||
allOf:
|
||||
@ -28,6 +27,7 @@ properties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
50
dts/upstream/Bindings/clock/qcom,gcc-mdm9615.yaml
Normal file
50
dts/upstream/Bindings/clock/qcom,gcc-mdm9615.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-mdm9615.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-mdm9615
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: CXO clock
|
||||
- description: PLL4 from LLC
|
||||
|
||||
'#power-domain-cells': false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-mdm9615";
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&cxo_board>,
|
||||
<&lcc_pll4>;
|
||||
};
|
||||
...
|
||||
@ -34,6 +34,8 @@ properties:
|
||||
- const: pxo
|
||||
- const: cxo
|
||||
|
||||
'#power-domain-cells': false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -47,7 +49,6 @@ examples:
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clocks = <&pxo_board>, <&cxo_board>;
|
||||
clock-names = "pxo", "cxo";
|
||||
};
|
||||
|
||||
@ -42,6 +42,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -48,6 +48,7 @@ properties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -42,6 +42,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -41,6 +41,7 @@ properties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
||||
@ -49,6 +49,7 @@ required:
|
||||
- clocks
|
||||
- clock-names
|
||||
- vdd_gfx-supply
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8994
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
@ -35,6 +35,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -50,6 +50,7 @@ properties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -38,6 +38,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -33,6 +33,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -40,6 +40,7 @@ properties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -40,6 +40,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -51,6 +51,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -40,6 +40,7 @@ required:
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -65,6 +65,7 @@ properties:
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -40,6 +40,7 @@ properties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
||||
@ -35,6 +35,7 @@ properties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -34,6 +34,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -39,6 +39,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -33,6 +33,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm Global Clock & Reset Controller on SM6125
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
@ -33,6 +33,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm Global Clock & Reset Controller on SM6350
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
@ -35,6 +35,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -34,6 +34,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -36,6 +36,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -55,6 +55,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -49,6 +49,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
@ -35,7 +35,6 @@ required:
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
|
||||
@ -33,28 +33,16 @@ properties:
|
||||
- const: gcc_gpu_gpll0_clk
|
||||
- const: gcc_gpu_gpll0_div_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -56,25 +56,10 @@ properties:
|
||||
vdd-gfx-supply:
|
||||
description: Regulator supply for the VDD_GFX pads
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
# Require that power-domains and vdd-gfx-supply are not both present
|
||||
@ -83,7 +68,10 @@ not:
|
||||
- power-domains
|
||||
- vdd-gfx-supply
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -33,6 +33,8 @@ properties:
|
||||
- description: UNIPHY RX clock source
|
||||
- description: UNIPHY TX clk source
|
||||
|
||||
'#power-domain-cells': false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
@ -58,6 +60,5 @@ examples:
|
||||
<&uniphy_tx_clk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
||||
@ -30,6 +30,8 @@ properties:
|
||||
- description: PCIE 2lane x1 PHY pipe clock source (For second lane)
|
||||
- description: USB PCIE wrapper pipe clock source
|
||||
|
||||
'#power-domain-cells': false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
@ -47,7 +49,6 @@ examples:
|
||||
<&pcie_2lane_phy_pipe_clk_x1>,
|
||||
<&usb_pcie_wrapper_pipe_clk>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
||||
@ -33,6 +33,11 @@ properties:
|
||||
- description: PCIE30 PHY3 pipe clock source
|
||||
- description: USB3 PHY pipe clock source
|
||||
|
||||
'#power-domain-cells': false
|
||||
|
||||
'#interconnect-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
@ -57,6 +62,5 @@ examples:
|
||||
<&usb3phy_0_cc_pipe_clk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
||||
@ -29,28 +29,16 @@ properties:
|
||||
- const: xo
|
||||
- const: gpll0
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
86
dts/upstream/Bindings/clock/qcom,qca8k-nsscc.yaml
Normal file
86
dts/upstream/Bindings/clock/qcom,qca8k-nsscc.yaml
Normal file
@ -0,0 +1,86 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Luo Jie <quic_luoj@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm NSS clock control module provides the clocks and resets
|
||||
on QCA8386(switch mode)/QCA8084(PHY mode)
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,qca8k-nsscc.h
|
||||
include/dt-bindings/reset/qcom,qca8k-nsscc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,qca8084-nsscc
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qca8082-nsscc
|
||||
- qcom,qca8085-nsscc
|
||||
- qcom,qca8384-nsscc
|
||||
- qcom,qca8385-nsscc
|
||||
- qcom,qca8386-nsscc
|
||||
- const: qcom,qca8084-nsscc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Chip reference clock source
|
||||
- description: UNIPHY0 RX 312P5M/125M clock source
|
||||
- description: UNIPHY0 TX 312P5M/125M clock source
|
||||
- description: UNIPHY1 RX 312P5M/125M clock source
|
||||
- description: UNIPHY1 TX 312P5M/125M clock source
|
||||
- description: UNIPHY1 RX 312P5M clock source
|
||||
- description: UNIPHY1 TX 312P5M clock source
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: MDIO bus address for Clock & Reset Controller register
|
||||
|
||||
reset-gpios:
|
||||
description: GPIO connected to the chip
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- reg
|
||||
- reset-gpios
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-controller@18 {
|
||||
compatible = "qcom,qca8084-nsscc";
|
||||
reg = <0x18>;
|
||||
reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&pcs0_pll>,
|
||||
<&qca8k_uniphy0_rx>,
|
||||
<&qca8k_uniphy0_tx>,
|
||||
<&qca8k_uniphy1_rx>,
|
||||
<&qca8k_uniphy1_tx>,
|
||||
<&qca8k_uniphy1_rx312p5m>,
|
||||
<&qca8k_uniphy1_tx312p5m>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -37,28 +37,16 @@ properties:
|
||||
- const: dsi0_phy_pll_out_byteclk
|
||||
- const: dsi0_phy_pll_out_dsiclk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
77
dts/upstream/Bindings/clock/qcom,qcm2290-gpucc.yaml
Normal file
77
dts/upstream/Bindings/clock/qcom,qcm2290-gpucc.yaml
Normal file
@ -0,0 +1,77 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller on QCM2290
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module provides the clocks, resets and power
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,qcm2290-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,qcm2290-gpucc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AHB interface clock,
|
||||
- description: SoC CXO clock
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the CX power domain.
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing required CX performance point.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@5990000 {
|
||||
compatible = "qcom,qcm2290-gpucc";
|
||||
reg = <0x0 0x05990000 0x0 0x9000>;
|
||||
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
|
||||
<&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
power-domains = <&rpmpd QCM2290_VDDCX>;
|
||||
required-opps = <&rpmpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
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Reference in New Issue
Block a user