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clk: ccf: mux: change the get_rate helper

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The previous version of the get_rate helper does not work if the mux
clock parent is changed after the probe. This error has not been
detected because this condition has not been tested. The error occurs
because the set_parent helper does not change the parent of the clock
device but only the clock selection register. Since changing the parent
of a probed device can be tricky, the new version of the get_rate helper
provides the rate of the selected clock and not that of the parent.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
This commit is contained in:
Dario Binacchi 2020-06-03 15:36:25 +02:00 committed by Lukasz Majewski
parent e3b5d74c77
commit 12d152620d
2 changed files with 49 additions and 1 deletions
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26
drivers/clk/clk-mux.c
View File

@ -149,8 +149,32 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
return 0;
}
static ulong clk_mux_get_rate(struct clk *clk)
{
struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
dev_get_clk_ptr(clk->dev) : clk);
struct udevice *parent;
struct clk *pclk;
int err, index;
index = clk_mux_get_parent(clk);
if (index >= mux->num_parents)
return -EFAULT;
err = uclass_get_device_by_name(UCLASS_CLK, mux->parent_names[index],
&parent);
if (err)
return err;
pclk = dev_get_clk_ptr(parent);
if (!pclk)
return -ENODEV;
return clk_get_rate(pclk);
}
const struct clk_ops clk_mux_ops = {
.get_rate = clk_generic_get_rate,
.get_rate = clk_mux_get_rate,
.set_parent = clk_mux_set_parent,
};

24
test/dm/clk_ccf.c
View File

@ -59,6 +59,18 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
rate = clk_get_parent_rate(clk);
ut_asserteq(rate, 60000000);
rate = clk_get_rate(clk);
ut_asserteq(rate, 60000000);
ret = clk_get_by_id(SANDBOX_CLK_PLL3_80M, &pclk);
ut_assertok(ret);
ret = clk_set_parent(clk, pclk);
ut_assertok(ret);
rate = clk_get_rate(clk);
ut_asserteq(rate, 80000000);
ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
ut_assertok(ret);
ut_asserteq_str("usdhc2_sel", clk->dev->name);
@ -71,6 +83,18 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
ut_asserteq_str("pll3_80m", pclk->dev->name);
ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);
rate = clk_get_rate(clk);
ut_asserteq(rate, 80000000);
ret = clk_get_by_id(SANDBOX_CLK_PLL3_60M, &pclk);
ut_assertok(ret);
ret = clk_set_parent(clk, pclk);
ut_assertok(ret);
rate = clk_get_rate(clk);
ut_asserteq(rate, 60000000);
/* Test the composite of CCF */
ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
ut_assertok(ret);