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taihu: Remove
This board has not compiled for me for quite some time due to size constraints, remove. Cc: John Otken <jotken@softadvances.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Tom Rini
Stefan Roese
parent
677f970bc6
commit
123b6cd7a4
@ -1,16 +0,0 @@
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if TARGET_TAIHU
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config SYS_BOARD
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default "taihu"
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config SYS_VENDOR
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default "amcc"
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config SYS_CONFIG_NAME
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default "taihu"
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config DISPLAY_BOARDINFO
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bool
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default y
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endif
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@ -1,6 +0,0 @@
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TAIHU BOARD
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M: John Otken <jotken@softadvances.com>
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S: Maintained
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F: board/amcc/taihu/
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F: include/configs/taihu.h
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F: configs/taihu_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = taihu.o flash.o lcd.o update.o
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File diff suppressed because it is too large
Load Diff
@ -1,237 +0,0 @@
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/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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#define LCD_CMD_ADDR 0x50100002
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#define LCD_DATA_ADDR 0x50100003
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#define LCD_BLK_CTRL CPLD_REG1_ADDR
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static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT";
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static int addr_flag = 0x80;
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static void lcd_bl_ctrl(char val)
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{
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out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val);
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}
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static void lcd_putc(int val)
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{
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int i = 100;
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char addr;
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while (i--) {
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if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
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udelay(50);
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break;
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}
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udelay(50);
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}
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if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
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printf("LCD is busy\n");
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return;
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}
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addr = in_8((u8 *) LCD_CMD_ADDR);
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udelay(50);
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if ((addr != 0) && (addr % 0x10 == 0)) {
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addr_flag ^= 0x40;
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out_8((u8 *) LCD_CMD_ADDR, addr_flag);
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}
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udelay(50);
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out_8((u8 *) LCD_DATA_ADDR, val);
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udelay(50);
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}
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static void lcd_puts(char *s)
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{
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char *p = s;
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int i = 100;
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while (i--) {
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if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
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udelay(50);
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break;
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}
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udelay(50);
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}
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if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
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printf("LCD is busy\n");
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return;
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}
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while (*p)
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lcd_putc(*p++);
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}
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static void lcd_put_logo(void)
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{
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int i = 100;
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char *p = amcc_logo;
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while (i--) {
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if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
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udelay(50);
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break;
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}
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udelay(50);
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}
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if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
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printf("LCD is busy\n");
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return;
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}
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out_8((u8 *) LCD_CMD_ADDR, 0x80);
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while (*p)
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lcd_putc(*p++);
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}
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int lcd_init(void)
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{
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puts("LCD: ");
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out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */
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udelay(50);
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out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */
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udelay(50);
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out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */
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udelay(2000);
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out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */
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udelay(50);
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lcd_bl_ctrl(0x02); /* set backlight on */
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lcd_put_logo();
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puts("ready\n");
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return 0;
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}
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static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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out_8((u8 *) LCD_CMD_ADDR, 0x01);
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udelay(2000);
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return 0;
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}
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static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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if (argc < 2)
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return cmd_usage(cmdtp);
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lcd_puts(argv[1]);
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return 0;
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}
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static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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if (argc < 2)
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return cmd_usage(cmdtp);
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lcd_putc((char)argv[1][0]);
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return 0;
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}
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static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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ulong count;
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ulong dir;
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char cur_addr;
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if (argc < 3)
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return cmd_usage(cmdtp);
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count = simple_strtoul(argv[1], NULL, 16);
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if (count > 31) {
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printf("unable to shift > 0x20\n");
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count = 0;
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}
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dir = simple_strtoul(argv[2], NULL, 16);
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cur_addr = in_8((u8 *) LCD_CMD_ADDR);
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udelay(50);
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if (dir == 0x0) {
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if (addr_flag == 0x80) {
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if (count >= (cur_addr & 0xf)) {
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out_8((u8 *) LCD_CMD_ADDR, 0x80);
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udelay(50);
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count = 0;
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}
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} else {
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if (count >= ((cur_addr & 0x0f) + 0x0f)) {
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out_8((u8 *) LCD_CMD_ADDR, 0x80);
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addr_flag = 0x80;
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udelay(50);
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count = 0x0;
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} else if (count >= ( cur_addr & 0xf)) {
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count -= cur_addr & 0xf ;
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out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf);
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addr_flag = 0x80;
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udelay(50);
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}
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}
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} else {
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if (addr_flag == 0x80) {
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if (count >= (0x1f - (cur_addr & 0xf))) {
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count = 0x0;
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addr_flag = 0xc0;
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out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf);
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udelay(50);
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} else if ((count + (cur_addr & 0xf ))>= 0x0f) {
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count = count + (cur_addr & 0xf) - 0x0f;
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addr_flag = 0xc0;
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out_8((u8 *) LCD_CMD_ADDR, 0xc0);
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udelay(50);
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}
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} else if ((count + (cur_addr & 0xf )) >= 0x0f) {
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count = 0x0;
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out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F);
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udelay(50);
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}
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}
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while (count--) {
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if (dir == 0)
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out_8((u8 *) LCD_CMD_ADDR, 0x10);
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else
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out_8((u8 *) LCD_CMD_ADDR, 0x14);
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udelay(50);
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}
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return 0;
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}
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U_BOOT_CMD(
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lcd_cls, 1, 1, do_lcd_clear,
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"lcd clear display",
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""
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);
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U_BOOT_CMD(
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lcd_puts, 2, 1, do_lcd_puts,
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"display string on lcd",
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"<string> - <string> to be displayed"
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);
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U_BOOT_CMD(
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lcd_putc, 2, 1, do_lcd_putc,
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"display char on lcd",
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"<char> - <char> to be displayed"
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);
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U_BOOT_CMD(
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lcd_cur, 3, 1, do_lcd_cur,
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"shift cursor on lcd",
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"<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n"
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" <count> - 0..31\n"
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" <dir> - 0=backward 1=forward"
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);
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@ -1,180 +0,0 @@
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/*
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* (C) Copyright 2000-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2005-2007
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* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <spi.h>
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#include <netdev.h>
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#include <asm/ppc4xx-gpio.h>
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extern int lcd_init(void);
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/*
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* board_early_init_f
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*/
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int board_early_init_f(void)
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{
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lcd_init();
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */
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mtdcr(UIC0CR, 0x00000000);
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mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
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mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
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mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
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/*
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* Configure CPC0_PCI to enable PerWE as output
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* and enable the internal PCI arbiter
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*/
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mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return 0;
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}
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static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[])
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{
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char stat;
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int i;
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stat = in_8((u8 *) CPLD_REG0_ADDR);
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printf("SW2 status: ");
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for (i=0; i<4; i++) /* 4-position */
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printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
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printf("\n");
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return 0;
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}
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U_BOOT_CMD (
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sw2_stat, 1, 1, do_sw_stat,
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"show status of switch 2",
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""
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);
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static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[])
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{
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int led_no;
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if (argc != 3)
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return cmd_usage(cmd_tp);
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led_no = simple_strtoul(argv[1], NULL, 16);
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if (led_no != 1 && led_no != 2)
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return cmd_usage(cmd_tp);
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if (strcmp(argv[2],"off") == 0x0) {
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if (led_no == 1)
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gpio_write_bit(30, 1);
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else
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gpio_write_bit(31, 1);
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} else if (strcmp(argv[2],"on") == 0x0) {
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if (led_no == 1)
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gpio_write_bit(30, 0);
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else
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gpio_write_bit(31, 0);
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} else {
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return cmd_usage(cmd_tp);
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}
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return 0;
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}
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U_BOOT_CMD (
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led_ctl, 3, 1, do_led_ctl,
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"make led 1 or 2 on or off",
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"<led_no> <on/off> - make led <led_no> on/off,\n"
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"\tled_no is 1 or 2"
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);
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#define SPI_CS_GPIO0 0
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#define SPI_SCLK_GPIO14 14
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#define SPI_DIN_GPIO15 15
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#define SPI_DOUT_GPIO16 16
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void spi_scl(int bit)
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{
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gpio_write_bit(SPI_SCLK_GPIO14, bit);
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}
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void spi_sda(int bit)
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{
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gpio_write_bit(SPI_DOUT_GPIO16, bit);
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}
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unsigned char spi_read(void)
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{
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return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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gpio_write_bit(SPI_CS_GPIO0, 1);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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gpio_write_bit(SPI_CS_GPIO0, 0);
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}
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#ifdef CONFIG_PCI
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static unsigned char int_lines[32] = {
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29, 30, 27, 28, 29, 30, 25, 27,
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29, 30, 27, 28, 29, 30, 27, 28,
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29, 30, 27, 28, 29, 30, 27, 28,
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29, 30, 27, 28, 29, 30, 27, 28};
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static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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{
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unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
|
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
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}
|
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int pci_pre_init(struct pci_controller *hose)
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{
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hose->fixup_irq = taihu_pci_fixup_irq;
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return 1;
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}
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#endif /* CONFIG_PCI */
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis);
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return pci_eth_init(bis);
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}
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@ -1,116 +0,0 @@
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/*
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* SPDX-License-Identifier: GPL-2.0+
|
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*/
|
||||
|
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#include <config.h>
|
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#include <common.h>
|
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#include <command.h>
|
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#include <asm/processor.h>
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#include <i2c.h>
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|
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#define PCI_M66EN 0x10
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static uchar buf_33[] =
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{
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0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
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0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
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0x00,
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0x00,
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0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
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0x00,
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0x00,
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0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
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0x00,
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0x00,
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0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
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0x00,
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0x00,
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0x10, /* 0x0d~0x0e:vendor id 0x1014*/
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0x14,
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0x00, /* 0x0f~0x10:device id 0x0000*/
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0x00,
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0x00, /* 0x11:revision 0x00 */
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0x00, /* 0x12~0x14:class 0x000000 */
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0x00,
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0x00,
|
||||
0x10, /* 0x15~0x16:subsystem vendor id */
|
||||
0xe8,
|
||||
0x00, /* 0x17~0x18:subsystem device id */
|
||||
0x00,
|
||||
0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
|
||||
0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
|
||||
0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
|
||||
0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
|
||||
0xbe, /* 0x1d: tun[24-31]=0xbe */
|
||||
0x00,
|
||||
0x00
|
||||
};
|
||||
|
||||
static uchar buf_66[] =
|
||||
{
|
||||
0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
|
||||
0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x10, /* 0x0d~0x0e:vendor id 0x1014*/
|
||||
0x14,
|
||||
0x00, /* 0x0f~0x10:device id 0x0000*/
|
||||
0x00,
|
||||
0x00, /* 0x11:revision 0x00 */
|
||||
0x00, /* 0x12~0x14:class 0x000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x10, /* 0x15~0x16:subsystem vendor id */
|
||||
0xe8,
|
||||
0x00, /* 0x17~0x18:subsystem device id */
|
||||
0x00,
|
||||
0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
|
||||
0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
|
||||
0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
|
||||
0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
|
||||
0xbe, /* 0x1d: tun[24-31]=0xbe */
|
||||
0x00,
|
||||
0x00
|
||||
};
|
||||
|
||||
static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
ulong len = 0x20;
|
||||
uchar chip = CONFIG_SYS_I2C_EEPROM_ADDR;
|
||||
uchar *pbuf;
|
||||
uchar base;
|
||||
int i;
|
||||
|
||||
if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) {
|
||||
pbuf = buf_33;
|
||||
base = 0x00;
|
||||
} else {
|
||||
pbuf = buf_66;
|
||||
base = 0x40;
|
||||
}
|
||||
|
||||
for (i = 0; i< len; i++, base++) {
|
||||
if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) {
|
||||
printf("i2c_write fail\n");
|
||||
return 1;
|
||||
}
|
||||
udelay(11000);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD (
|
||||
update_boot_eeprom, 1, 1, update_boot_eeprom,
|
||||
"update boot eeprom content",
|
||||
""
|
||||
);
|
||||
@ -1,3 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_4xx=y
|
||||
CONFIG_TARGET_TAIHU=y
|
||||
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
||||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
taihu powerpc ppc4xx - - John Otken <jotken@softadvances.com>
|
||||
lcd4_lwmon5 powerpc ppc4xx b6b5e394 2015-10-02 Stefan Roese <sr@denx.de>
|
||||
da830evm arm arm926ejs d7e8b2b9 2015-09-12 Nick Thompson <nick.thompson@gefanuc.com>
|
||||
wireless_space arm arm926ejs b352182a 2015-09-12 Albert ARIBAUD <albert.u.boot@aribaud.net>
|
||||
|
||||
@ -1,307 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2005-2007
|
||||
* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
|
||||
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
|
||||
#define CONFIG_TAIHU 1 /* on a taihu board */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
|
||||
|
||||
/*
|
||||
* Include common defines/options for all AMCC eval boards
|
||||
*/
|
||||
#define CONFIG_HOSTNAME taihu
|
||||
#include "amcc-common.h"
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
|
||||
|
||||
#define CONFIG_NO_SERIAL_EEPROM
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#ifdef CONFIG_NO_SERIAL_EEPROM
|
||||
|
||||
/*
|
||||
!-------------------------------------------------------------------------------
|
||||
! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
|
||||
! assuming a 33MHz input clock to the 405EP from the C9531.
|
||||
!-------------------------------------------------------------------------------
|
||||
*/
|
||||
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_3)
|
||||
#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_1)
|
||||
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
|
||||
#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
|
||||
#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
|
||||
#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
|
||||
#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
|
||||
|
||||
#endif
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_AMCC_DEF_ENV \
|
||||
CONFIG_AMCC_DEF_ENV_PPC \
|
||||
CONFIG_AMCC_DEF_ENV_NOR_UPD \
|
||||
"kernel_addr=FC000000\0" \
|
||||
"ramdisk_addr=FC180000\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_PHY_ADDR 0x14 /* PHY address */
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
|
||||
#define CONFIG_PHY_RESET 1
|
||||
|
||||
/*
|
||||
* Commands additional to the ones defined in amcc-common.h
|
||||
*/
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_SPI
|
||||
|
||||
#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
|
||||
#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
|
||||
#define CONFIG_SYS_SDRAM_BANKS 2
|
||||
|
||||
/*
|
||||
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
|
||||
*/
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
|
||||
|
||||
/* SDRAM timings used in datasheet */
|
||||
#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
|
||||
#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
|
||||
#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
|
||||
#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
|
||||
#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
|
||||
|
||||
/*
|
||||
* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
|
||||
* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
|
||||
* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
|
||||
* The Linux BASE_BAUD define should match this configuration.
|
||||
* baseBaud = cpuClock/(uartDivisor*16)
|
||||
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
|
||||
* set Linux BASE_BAUD to 403200.
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
|
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
|
||||
#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
|
||||
#define CONFIG_SYS_BASE_BAUD 691200
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
|
||||
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* avoid i2c probe hangup (?) */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
|
||||
#define CONFIG_SOFT_SPI
|
||||
#define SPI_SCL spi_scl
|
||||
#define SPI_SDA spi_sda
|
||||
#define SPI_READ spi_read()
|
||||
#define SPI_DELAY udelay(2)
|
||||
#ifndef __ASSEMBLY__
|
||||
void spi_scl(int);
|
||||
void spi_sda(int);
|
||||
unsigned char spi_read(void);
|
||||
#endif
|
||||
|
||||
/* standard dtt sensor configuration */
|
||||
#define CONFIG_DTT_DS1775 1
|
||||
#define CONFIG_DTT_SENSORS { 0 }
|
||||
#define CONFIG_SYS_I2C_DTT_ADDR 0x49
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
|
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */
|
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
|
||||
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
/* resource configuration */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
#define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
|
||||
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
|
||||
#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
|
||||
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
|
||||
#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
|
||||
#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
|
||||
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
|
||||
#define CONFIG_EEPRO100 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFFE00000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ADDR0 0x555
|
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2aa
|
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
#endif /* CONFIG_ENV_IS_IN_FLASH */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization
|
||||
*/
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
|
||||
#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_NVRAM
|
||||
#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
|
||||
#define CONFIG_ENV_ADDR \
|
||||
(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env*/
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PPC405 GPIO Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
|
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
|
||||
} \
|
||||
}
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache)
|
||||
*/
|
||||
/* use on chip memory (OCM) for temperary stack until sdram is tested */
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
|
||||
/* On Chip Memory location */
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
|
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
|
||||
/* Memory Bank 0 (Flash/SRAM) initialization */
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x03815600
|
||||
#define CONFIG_SYS_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 1 (NVRAM/RTC) initialization */
|
||||
#define CONFIG_SYS_EBC_PB1AP 0x05815600
|
||||
#define CONFIG_SYS_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 2 (USB device) initialization */
|
||||
#define CONFIG_SYS_EBC_PB2AP 0x03016600
|
||||
#define CONFIG_SYS_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 3 (LCM and D-flip-flop) initialization */
|
||||
#define CONFIG_SYS_EBC_PB3AP 0x158FF600
|
||||
#define CONFIG_SYS_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 4 (not install) initialization */
|
||||
#define CONFIG_SYS_EBC_PB4AP 0x158FF600
|
||||
#define CONFIG_SYS_EBC_PB4CR 0x5021A000
|
||||
|
||||
#define CPLD_REG0_ADDR 0x50100000
|
||||
#define CPLD_REG1_ADDR 0x50100001
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user