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ARM: k2g: Correct base addresses

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Coreect base addresses for SPI, Queue Manager, Ethernet, GPIO,
and MSMC segments.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Vitaly Andrianov 2015-09-19 16:26:46 +05:30 committed by Tom Rini
parent dd78b8cf30
commit 11d8222a26
3 changed files with 57 additions and 0 deletions
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23
arch/arm/mach-keystone/include/mach/hardware-k2g.h
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@ -48,4 +48,27 @@
#define KS2_LPSC_CPGMAC KS2_LPSC_NSS
#define KS2_LPSC_CRYPTO KS2_LPSC_SA
/* SGMII SerDes */
#define KS2_LANES_PER_SGMII_SERDES 4
/* NETCP pktdma */
#define KS2_NETCP_PDMA_CTRL_BASE 0x04010000
#define KS2_NETCP_PDMA_TX_BASE 0x04011000
#define KS2_NETCP_PDMA_TX_CH_NUM 21
#define KS2_NETCP_PDMA_RX_BASE 0x04012000
#define KS2_NETCP_PDMA_RX_CH_NUM 32
#define KS2_NETCP_PDMA_SCHED_BASE 0x04010100
#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x04013000
#define KS2_NETCP_PDMA_RX_FLOW_NUM 32
#define KS2_NETCP_PDMA_TX_SND_QUEUE 5
/* NETCP */
#define KS2_NETCP_BASE 0x04000000
#define K2G_GPIO0_BASE 0X02603000
#define K2G_GPIO1_BASE 0X0260a000
#define K2G_GPIO1_BANK2_BASE K2G_GPIO1_BASE + 0x38
#define K2G_GPIO_DIR_OFFSET 0x0
#define K2G_GPIO_SETDATA_OFFSET 0x8
#endif /* __ASM_ARCH_HARDWARE_K2G_H */

32
arch/arm/mach-keystone/include/mach/hardware.h
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@ -147,6 +147,8 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
#define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
#define KS2_ETHERNET_CFG (KS2_DEVICE_STATE_CTRL_BASE + 0xe20)
#define KS2_ETHERNET_RGMII 2
/* PSC */
#define KS2_PSC_BASE 0x02350000
@ -185,10 +187,17 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_RSTYPE_PLL_SOFT BIT(13)
/* SPI */
#ifdef CONFIG_SOC_K2G
#define KS2_SPI0_BASE 0x21805400
#define KS2_SPI1_BASE 0x21805800
#define KS2_SPI2_BASE 0x21805c00
#define KS2_SPI3_BASE 0x21806000
#else
#define KS2_SPI0_BASE 0x21000400
#define KS2_SPI1_BASE 0x21000600
#define KS2_SPI2_BASE 0x21000800
#define KS2_SPI_BASE KS2_SPI0_BASE
#endif
/* AEMIF */
#define KS2_AEMIF_CNTRL_BASE 0x21000a00
@ -200,10 +209,16 @@ typedef volatile unsigned int *dv_reg_p;
/* MSMC control */
#define KS2_MSMC_CTRL_BASE 0x0bc00000
#define KS2_MSMC_DATA_BASE 0x0c000000
#ifndef CONFIG_SOC_K2G
#define KS2_MSMC_SEGMENT_TETRIS 8
#define KS2_MSMC_SEGMENT_NETCP 9
#define KS2_MSMC_SEGMENT_QM_PDSP 10
#define KS2_MSMC_SEGMENT_PCIE0 11
#else
#define KS2_MSMC_SEGMENT_TETRIS 1
#define KS2_MSMC_SEGMENT_NETCP 4
#define KS2_MSMC_SEGMENT_PCIE0 5
#endif
/* MSMC segment size shift bits */
#define KS2_MSMC_SEG_SIZE_SHIFT 12
@ -217,6 +232,22 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
/* Queue manager */
#ifdef CONFIG_SOC_K2G
#define KS2_QM_BASE_ADDRESS 0x040C0000
#define KS2_QM_CONF_BASE 0x04040000
#define KS2_QM_DESC_SETUP_BASE 0x04080000
#define KS2_QM_STATUS_RAM_BASE 0x0 /* K2G doesn't have it */
#define KS2_QM_INTD_CONF_BASE 0x0
#define KS2_QM_PDSP1_CMD_BASE 0x0
#define KS2_QM_PDSP1_CTRL_BASE 0x0
#define KS2_QM_PDSP1_IRAM_BASE 0x0
#define KS2_QM_MANAGER_QUEUES_BASE 0x040c0000
#define KS2_QM_MANAGER_Q_PROXY_BASE 0x04040200
#define KS2_QM_QUEUE_STATUS_BASE 0x04100000
#define KS2_QM_LINK_RAM_BASE 0x04020000
#define KS2_QM_REGION_NUM 8
#define KS2_QM_QPOOL_NUM 112
#else
#define KS2_QM_BASE_ADDRESS 0x23a80000
#define KS2_QM_CONF_BASE 0x02a02000
#define KS2_QM_DESC_SETUP_BASE 0x02a03000
@ -231,6 +262,7 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_QM_LINK_RAM_BASE 0x00100000
#define KS2_QM_REGION_NUM 64
#define KS2_QM_QPOOL_NUM 4000
#endif
/* USB */
#define KS2_USB_SS_BASE 0x02680000

2
arch/arm/mach-keystone/init.c
View File

@ -103,7 +103,9 @@ int arch_cpu_init(void)
msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
#ifdef KS2_MSMC_SEGMENT_QM_PDSP
msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
#endif
msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
/* Initialize the PCIe-0 to work as Root Complex */