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board/BuR: provide real clock-frequency instead a divider
Actual am335x-fb implementation takes now a real clock frequency instead a divider. So this component doesn't need to know anymore some base frequency of the LCDC, we simply provide the pixel-clock frequency. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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@ -139,13 +139,7 @@ int load_lcdtiming(struct am335x_lcdpanel *panel)
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pnltmp.vsw = FDTPROP(PATHTIM, "vsync-len");
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pnltmp.pup_delay = FDTPROP(PATHTIM, "pupdelay");
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pnltmp.pon_delay = FDTPROP(PATHTIM, "pondelay");
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/* calc. proper clk-divisor */
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dtbprop = FDTPROP(PATHTIM, "clock-frequency");
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if (dtbprop != ~0UL)
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pnltmp.pxl_clk_div = 192000000 / dtbprop;
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else
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pnltmp.pxl_clk_div = ~0UL;
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pnltmp.pxl_clk = FDTPROP(PATHTIM, "clock-frequency");
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/* check polarity of control-signals */
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dtbprop = FDTPROP(PATHTIM, "hsync-active");
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@ -195,7 +189,7 @@ int load_lcdtiming(struct am335x_lcdpanel *panel)
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pnltmp.vfp = env_get_ulong("ds1_vfp", 10, ~0UL);
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pnltmp.vbp = env_get_ulong("ds1_vbp", 10, ~0UL);
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pnltmp.vsw = env_get_ulong("ds1_vsw", 10, ~0UL);
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pnltmp.pxl_clk_div = env_get_ulong("ds1_pxlclkdiv", 10, ~0UL);
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pnltmp.pxl_clk = env_get_ulong("ds1_pxlclk", 10, ~0UL);
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pnltmp.pol = env_get_ulong("ds1_pol", 16, ~0UL);
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pnltmp.pup_delay = env_get_ulong("ds1_pupdelay", 10, ~0UL);
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pnltmp.pon_delay = env_get_ulong("ds1_tondelay", 10, ~0UL);
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@ -211,7 +205,7 @@ int load_lcdtiming(struct am335x_lcdpanel *panel)
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~0UL == (pnltmp.vfp) ||
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~0UL == (pnltmp.vbp) ||
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~0UL == (pnltmp.vsw) ||
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~0UL == (pnltmp.pxl_clk_div) ||
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~0UL == (pnltmp.pxl_clk) ||
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~0UL == (pnltmp.pol) ||
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~0UL == (pnltmp.pup_delay) ||
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~0UL == (pnltmp.pon_delay)
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@ -234,7 +228,7 @@ int load_lcdtiming(struct am335x_lcdpanel *panel)
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pnltmp.hactive, pnltmp.vactive, pnltmp.bpp,
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pnltmp.hfp, pnltmp.hbp, pnltmp.hsw,
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pnltmp.vfp, pnltmp.vbp, pnltmp.vsw,
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pnltmp.pxl_clk_div, pnltmp.pol, pnltmp.pon_delay);
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pnltmp.pxl_clk, pnltmp.pol, pnltmp.pon_delay);
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return -1;
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}
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