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Cosmetic changes to ECC POST for AMCC Denali core
Signed-off-by: Larry Johnson <lrj@acm.org>
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@ -50,7 +50,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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const static unsigned char syndrome_codes[] = {
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0xF4, 0XF1, 0XEC ,0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
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0xF4, 0XF1, 0XEC, 0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
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0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
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0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
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0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
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@ -171,7 +171,7 @@ static int test_ecc(unsigned long ecc_addr)
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/* test for correctable error */
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/* disconnect from ecc storage */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
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mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_ECC_DISABLE);
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/* creating (correctable) single-bit error */
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@ -179,7 +179,7 @@ static int test_ecc(unsigned long ecc_addr)
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/* enable ecc */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
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mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_ECC_ENABLE);
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sync();
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eieio();
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@ -194,7 +194,7 @@ static int test_ecc(unsigned long ecc_addr)
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/* test for uncorrectable error */
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/* disconnect from ecc storage */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
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mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_NO_ECC_RAM);
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/* creating (uncorrectable) multiple-bit error */
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@ -202,7 +202,7 @@ static int test_ecc(unsigned long ecc_addr)
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/* enable ecc */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
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mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_ECC_ENABLE);
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sync();
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eieio();
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@ -242,7 +242,7 @@ int ecc_post_test (int flags)
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/* mask all int */
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mfsdram(DDR0_01, value);
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mtsdram(DDR0_01, (value &~ DDR0_01_INT_MASK_MASK)
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mtsdram(DDR0_01, (value & ~DDR0_01_INT_MASK_MASK)
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| DDR0_01_INT_MASK_ALL_OFF);
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/* clear error status */
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