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Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx

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This commit is contained in:
Tom Rini 2014-10-27 11:03:00 -04:00
commit 0cf8761549
205 changed files with 44 additions and 62636 deletions
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16
arch/powerpc/cpu/74xx_7xx/Kconfig
View File

@ -19,30 +19,14 @@ config TARGET_PPMC7XX
config TARGET_ELPPC
bool "Support ELPPC"
config TARGET_CPCI750
bool "Support CPCI750"
config TARGET_MPC7448HPC2
bool "Support mpc7448hpc2"
config TARGET_DB64360
bool "Support DB64360"
config TARGET_DB64460
bool "Support DB64460"
config TARGET_P3MX
bool "Support p3mx"
endchoice
source "board/Marvell/db64360/Kconfig"
source "board/Marvell/db64460/Kconfig"
source "board/eltec/elppc/Kconfig"
source "board/esd/cpci750/Kconfig"
source "board/evb64260/Kconfig"
source "board/freescale/mpc7448hpc2/Kconfig"
source "board/ppmc7xx/Kconfig"
source "board/prodrive/p3mx/Kconfig"
endmenu

13
arch/powerpc/cpu/74xx_7xx/start.S
View File

@ -28,13 +28,6 @@
#include <asm/mmu.h>
#include <asm/u-boot.h>
#if !defined(CONFIG_DB64360) && \
!defined(CONFIG_DB64460) && \
!defined(CONFIG_CPCI750) && \
!defined(CONFIG_P3Mx)
#include <galileo/gt64260R.h>
#endif
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
@ -712,11 +705,7 @@ in_ram:
bne 5b
6:
mr r3, r10 /* Destination Address */
#if defined(CONFIG_DB64360) || \
defined(CONFIG_DB64460) || \
defined(CONFIG_CPCI750) || \
defined(CONFIG_PPMC7XX) || \
defined(CONFIG_P3Mx)
#if defined(CONFIG_PPMC7XX)
mr r4, r9 /* Use RAM copy of the global data */
#endif
bl after_reloc

16
arch/powerpc/cpu/mpc8260/Kconfig
View File

@ -28,9 +28,6 @@ config TARGET_EP82XXM
config TARGET_GW8260
bool "Support gw8260"
config TARGET_HYMOD
bool "Support hymod"
config TARGET_IPHASE4539
bool "Support IPHASE4539"
@ -55,18 +52,9 @@ config TARGET_MPC8266ADS
config TARGET_VOVPN_GW
bool "Support VoVPN-GW"
config TARGET_IDS8247
bool "Support IDS8247"
config TARGET_KM82XX
bool "Support km82xx"
config TARGET_TQM8260
bool "Support TQM8260"
config TARGET_TQM8272
bool "Support TQM8272"
endchoice
source "board/atc/Kconfig"
@ -78,8 +66,6 @@ source "board/ep82xxm/Kconfig"
source "board/freescale/mpc8266ads/Kconfig"
source "board/funkwerk/vovpn-gw/Kconfig"
source "board/gw8260/Kconfig"
source "board/hymod/Kconfig"
source "board/ids/ids8247/Kconfig"
source "board/iphase4539/Kconfig"
source "board/keymile/km82xx/Kconfig"
source "board/muas3001/Kconfig"
@ -87,7 +73,5 @@ source "board/pm826/Kconfig"
source "board/pm828/Kconfig"
source "board/ppmc8260/Kconfig"
source "board/sacsng/Kconfig"
source "board/tqc/tqm8260/Kconfig"
source "board/tqc/tqm8272/Kconfig"
endmenu

27
arch/powerpc/cpu/mpc8260/ether_fcc.c
View File

@ -645,32 +645,7 @@ eth_loopback_test (void)
/* 28.9 - (1-2): ioports have been set up already */
#if defined(CONFIG_HYMOD)
/*
* Attention: this is board-specific
* 0, FCC1
* 1, FCC2
* 2, FCC3
*/
# define FCC_START_LOOP 0
# define FCC_END_LOOP 2
/*
* Attention: this is board-specific
* - FCC1 Rx-CLK is CLK10
* - FCC1 Tx-CLK is CLK11
* - FCC2 Rx-CLK is CLK13
* - FCC2 Tx-CLK is CLK14
* - FCC3 Rx-CLK is CLK15
* - FCC3 Tx-CLK is CLK16
*/
/* 28.9 - (3): connect FCC's tx and rx clocks */
immr->im_cpmux.cmx_uar = 0;
immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
#elif defined(CONFIG_SACSng)
#if defined(CONFIG_SACSng)
/*
* Attention: this is board-specific
* 1, FCC2

10
arch/powerpc/cpu/mpc8260/interrupts.c
View File

@ -142,15 +142,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
immr->im_intctl.ic_sipnrh = 0xffffffff;
immr->im_intctl.ic_sipnrl = 0xffffffff;
#ifdef CONFIG_HYMOD
/*
* ensure all external interrupt sources default to trigger on
* high-to-low transition (i.e. edge triggered active low)
*/
immr->im_intctl.ic_siexr = -1;
#endif
return (0);
return 0;
}
/****************************************************************************/

2
arch/powerpc/cpu/mpc8260/pci.c
View File

@ -262,8 +262,6 @@ void pci_mpc8250_init (struct pci_controller *hose)
| SIUMCR_CS10PC00
| SIUMCR_BCTLC00
| SIUMCR_MMR11;
#elif defined(CONFIG_TQM8272)
/* nothing to do for this Board here */
#else
/*
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),

14
arch/powerpc/cpu/mpc8260/start.S
View File

@ -48,9 +48,6 @@
GOT_ENTRY(__init_end)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
#if defined(CONFIG_HYMOD)
GOT_ENTRY(environment)
#endif
END_GOT
/*
@ -878,18 +875,7 @@ clear_bss:
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
#if defined(CONFIG_HYMOD)
/*
* For HYMOD - the environment is the very last item in flash.
* The real .bss stops just before environment starts, so only
* clear up to that point.
*
* taken from mods for FADS board
*/
lwz r4,GOT(environment)
#else
lwz r4,GOT(__bss_end)
#endif
cmplw 0, r3, r4
beq 6f

11
arch/powerpc/cpu/mpc83xx/start.S
View File

@ -958,18 +958,7 @@ clear_bss:
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
#if defined(CONFIG_HYMOD)
/*
* For HYMOD - the environment is the very last item in flash.
* The real .bss stops just before environment starts, so only
* clear up to that point.
*
* taken from mods for FADS board
*/
lwz r4,GOT(environment)
#else
lwz r4,GOT(__bss_end)
#endif
cmplw 0, r3, r4
beq 6f

4
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -13,9 +13,6 @@ config TARGET_SBC8548
config TARGET_SOCRATES
bool "Support socrates"
config TARGET_HWW1U1A
bool "Support HWW1U1A"
config TARGET_B4860QDS
bool "Support B4860QDS"
@ -144,7 +141,6 @@ config TARGET_XPEDITE550X
endchoice
source "board/exmeritus/hww1u1a/Kconfig"
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"

8
arch/powerpc/cpu/mpc8xx/Kconfig
View File

@ -16,9 +16,6 @@ config TARGET_ESTEEM192E
config TARGET_HERMES
bool "Support hermes"
config TARGET_ICU862
bool "Support ICU862"
config TARGET_IP860
bool "Support IP860"
@ -43,9 +40,6 @@ config TARGET_RRVISION
config TARGET_SPD823TS
bool "Support SPD823TS"
config TARGET_MHPC
bool "Support MHPC"
config TARGET_TOP860
bool "Support TOP860"
@ -120,11 +114,9 @@ endchoice
source "board/LEOX/elpt860/Kconfig"
source "board/RRvision/Kconfig"
source "board/cogent/Kconfig"
source "board/eltec/mhpc/Kconfig"
source "board/emk/top860/Kconfig"
source "board/esteem192e/Kconfig"
source "board/hermes/Kconfig"
source "board/icu862/Kconfig"
source "board/ip860/Kconfig"
source "board/ivm/Kconfig"
source "board/kup/kup4k/Kconfig"

2
arch/powerpc/cpu/mpc8xx/cpu_init.c
View File

@ -126,12 +126,10 @@ void cpu_init_f (volatile immap_t * immr)
*/
#if defined(CONFIG_HERMES) || \
defined(CONFIG_ICU862) || \
defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
defined(CONFIG_MHPC) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU) || \
defined(CONFIG_SPD823TS)

40
arch/powerpc/cpu/mpc8xx/fec.c
View File

@ -205,11 +205,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
j = 0;
while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
#if defined(CONFIG_ICU862)
udelay(10);
#else
udelay(1);
#endif
j++;
}
if (j>=TOUT_LOOP) {
@ -424,7 +420,7 @@ static void fec_pin_init(int fecidx)
#endif /* !CONFIG_RMII */
#elif !defined(CONFIG_ICU862)
#else
/*
* Configure all of port D for MII.
*/
@ -437,42 +433,8 @@ static void fec_pin_init(int fecidx)
immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
else
immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
#else
/*
* Configure port A for MII.
*/
#if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY)
/*
* On the ICU862 board the MII-MDC pin is routed to PD8 pin
* * of CPU, so for this board we need to configure Utopia and
* * enable PD8 to MII-MDC function
*/
immr->im_ioport.iop_pdpar |= 0x4080;
#endif
/*
* Has Utopia been configured?
*/
if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
/*
* YES - Use MUXED mode for UTOPIA bus.
* This frees Port A for use by MII (see 862UM table 41-6).
*/
immr->im_ioport.utmode &= ~0x80;
} else {
/*
* NO - set SPLIT mode for UTOPIA bus.
*
* This doesn't really effect UTOPIA (which isn't
* enabled anyway) but just tells the 862
* to use port A for MII (see 862UM table 41-6).
*/
immr->im_ioport.utmode |= 0x80;
}
#endif /* !defined(CONFIG_ICU862) */
#endif /* CONFIG_ETHER_ON_FEC1 */
} else if (fecidx == 1) {

1
arch/powerpc/include/asm/immap_512x.h
View File

@ -59,6 +59,7 @@ typedef struct sysconf512x {
u8 res2[0x28];
law512x_t ddrlaw; /* DDR Local Access Window */
u8 res3[0x18];
u32 mbxbar; /* MBX Base Address */
u32 srambar; /* SRAM Base Address */
u32 nfcbar; /* NFC Base Address */
u8 res4[0x34];

3
arch/powerpc/include/asm/u-boot.h
View File

@ -77,9 +77,6 @@ typedef struct bd_info {
unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
#endif
#if defined(CONFIG_HYMOD)
hymod_conf_t bi_hymod_conf; /* hymod configuration information */
#endif
#ifdef CONFIG_HAS_ETH1
unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */

1056
board/Marvell/common/flash.c
View File

File diff suppressed because it is too large Load Diff

521
board/Marvell/common/i2c.c
View File

@ -1,521 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Hacked for the DB64360 board by Ingo.Assmus@keymile.com
* extra improvments by Brain Waite
*/
#include <common.h>
#include <mpc8xx.h>
#include <malloc.h>
#include <i2c.h>
#include "../include/mv_gen_reg.h"
#include "../include/core.h"
#define MAX_I2C_RETRYS 10
#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */
#undef DEBUG_I2C
/*#define DEBUG_I2C*/
#ifdef DEBUG_I2C
#define DP(x) x
#else
#define DP(x)
#endif
/* Assuming that there is only one master on the bus (us) */
void i2c_init (int speed, int slaveaddr)
{
unsigned int n, m, freq, margin, power;
unsigned int actualN = 0, actualM = 0;
unsigned int control, status;
unsigned int minMargin = 0xffffffff;
unsigned int tclk = CONFIG_SYS_TCLK;
unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */
DP (puts ("i2c_init\n"));
/* gtI2cMasterInit */
for (n = 0; n < 8; n++) {
for (m = 0; m < 16; m++) {
power = 2 << n; /* power = 2^(n+1) */
freq = tclk / (10 * (m + 1) * power);
if (i2cFreq > freq)
margin = i2cFreq - freq;
else
margin = freq - i2cFreq;
if (margin < minMargin) {
minMargin = margin;
actualN = n;
actualM = m;
}
}
}
DP (puts ("setup i2c bus\n"));
/* Setup bus */
/* gtI2cReset */
GT_REG_WRITE (I2C_SOFT_RESET, 0);
DP (puts ("udelay...\n"));
udelay (I2C_DELAY);
DP (puts ("set baudrate\n"));
GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
udelay (I2C_DELAY * 10);
DP (puts ("read control, baudrate\n"));
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
GT_REG_READ (I2C_CONTROL, &control);
}
static uchar i2c_start (void)
{ /* DB64360 checked -> ok */
unsigned int control, status;
int count = 0;
DP (puts ("i2c_start\n"));
/* Set the start bit */
/* gtI2cGenerateStartBit() */
GT_REG_READ (I2C_CONTROL, &control);
control |= (0x1 << 5); /* generate the I2C_START_BIT */
GT_REG_WRITE (I2C_CONTROL, control);
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count = 0;
while ((status & 0xff) != 0x08) {
udelay (I2C_DELAY);
if (count > 20) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
return (0);
}
static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
{
unsigned int status, data, bits = 7;
int count = 0;
DP (puts ("i2c_select_device\n"));
/* Output slave address */
if (ten_bit) {
bits = 10;
}
data = (dev_addr << 1);
/* set the read bit */
data |= read;
GT_REG_WRITE (I2C_DATA, data);
/* assert the address */
RESET_REG_BITS (I2C_CONTROL, BIT3);
udelay (I2C_DELAY);
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count = 0;
while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
udelay (I2C_DELAY);
if (count > 20) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
if (bits == 10) {
printf ("10 bit I2C addressing not yet implemented\n");
return (0xff);
}
return (0);
}
static uchar i2c_get_data (uchar * return_data, int len)
{
unsigned int data, status = 0;
int count = 0;
DP (puts ("i2c_get_data\n"));
while (len) {
/* Get and return the data */
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
udelay (I2C_DELAY * 5);
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
while ((status & 0xff) != 0x50) {
udelay (I2C_DELAY);
if (count > 2) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return 0;
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
GT_REG_READ (I2C_DATA, &data);
len--;
*return_data = (uchar) data;
return_data++;
}
RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
while ((status & 0xff) != 0x58) {
udelay (I2C_DELAY);
if (count > 200) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */
return (0);
}
static uchar i2c_write_data (unsigned int *data, int len)
{
unsigned int status;
int count = 0;
unsigned int temp;
unsigned int *temp_ptr = data;
DP (puts ("i2c_write_data\n"));
while (len) {
temp = (unsigned int) (*temp_ptr);
GT_REG_WRITE (I2C_DATA, temp);
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
udelay (I2C_DELAY);
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
while ((status & 0xff) != 0x28) {
udelay (I2C_DELAY);
if (count > 20) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
len--;
temp_ptr++;
}
/* 11-14-2002 Paul Marchese */
/* Can't have the write issuing a stop command */
/* it's wrong to have a stop bit in read stream or write stream */
/* since we don't know if it's really the end of the command */
/* or whether we have just send the device address + offset */
/* we will push issuing the stop command off to the original */
/* calling function */
/* set the interrupt bit in the control register */
GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
udelay (I2C_DELAY * 10);
return (0);
}
/* 11-14-2002 Paul Marchese */
/* created this function to get the i2c_write() */
/* function working properly. */
/* function to write bytes out on the i2c bus */
/* this is identical to the function i2c_write_data() */
/* except that it requires a buffer that is an */
/* unsigned character array. You can't use */
/* i2c_write_data() to send an array of unsigned characters */
/* since the byte of interest ends up on the wrong end of the bus */
/* aah, the joys of big endian versus little endian! */
/* */
/* returns 0 = success */
/* anything other than zero is failure */
static uchar i2c_write_byte (unsigned char *data, int len)
{
unsigned int status;
int count = 0;
unsigned int temp;
unsigned char *temp_ptr = data;
DP (puts ("i2c_write_byte\n"));
while (len) {
/* Set and assert the data */
temp = *temp_ptr;
GT_REG_WRITE (I2C_DATA, temp);
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
udelay (I2C_DELAY);
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
while ((status & 0xff) != 0x28) {
udelay (I2C_DELAY);
if (count > 20) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
len--;
temp_ptr++;
}
/* Can't have the write issuing a stop command */
/* it's wrong to have a stop bit in read stream or write stream */
/* since we don't know if it's really the end of the command */
/* or whether we have just send the device address + offset */
/* we will push issuing the stop command off to the original */
/* calling function */
/* GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); */
/* set the interrupt bit in the control register */
GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
udelay (I2C_DELAY * 10);
return (0);
}
static uchar
i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
int alen)
{
uchar status;
unsigned int table[2];
/* initialize the table of address offset bytes */
/* utilized for 2 byte address offsets */
/* NOTE: the order is high byte first! */
table[1] = offset & 0xff; /* low byte */
table[0] = offset / 0x100; /* high byte */
DP (puts ("i2c_set_dev_offset\n"));
status = i2c_select_device (dev_addr, 0, ten_bit);
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to select device setting offset: 0x%02x\n",
status);
#endif
return status;
}
/* check the address offset length */
if (alen == 0)
/* no address offset */
return (0);
else if (alen == 1) {
/* 1 byte address offset */
status = i2c_write_data (&offset, 1);
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to write data: 0x%02x\n", status);
#endif
return status;
}
} else if (alen == 2) {
/* 2 bytes address offset */
status = i2c_write_data (table, 2);
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to write data: 0x%02x\n", status);
#endif
return status;
}
} else {
/* address offset unknown or not supported */
printf ("Address length offset %d is not supported\n", alen);
return 1;
}
return 0; /* sucessful completion */
}
int
i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
int len)
{
uchar status = 0;
unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_read\n"));
/* set the i2c frequency */
i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
status = i2c_start ();
if (status) {
#ifdef DEBUG_I2C
printf ("Transaction start failed: 0x%02x\n", status);
#endif
return status;
}
status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to set slave address & offset: 0x%02x\n",
status);
#endif
return status;
}
/* set the i2c frequency again */
i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
status = i2c_start ();
if (status) {
#ifdef DEBUG_I2C
printf ("Transaction restart failed: 0x%02x\n", status);
#endif
return status;
}
status = i2c_select_device (dev_addr, 1, 0); /* send the slave address */
if (status) {
#ifdef DEBUG_I2C
printf ("Address not acknowledged: 0x%02x\n", status);
#endif
return status;
}
status = i2c_get_data (data, len);
if (status) {
#ifdef DEBUG_I2C
printf ("Data not received: 0x%02x\n", status);
#endif
return status;
}
return 0;
}
/* 11-14-2002 Paul Marchese */
/* Function to set the I2C stop bit */
void i2c_stop (void)
{
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
}
/* 11-14-2002 Paul Marchese */
/* I2C write function */
/* dev_addr = device address */
/* offset = address offset */
/* alen = length in bytes of the address offset */
/* data = pointer to buffer to read data into */
/* len = # of bytes to read */
/* */
/* returns 0 = succesful */
/* anything but zero is failure */
int
i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
int len)
{
uchar status = 0;
unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_write\n"));
/* set the i2c frequency */
i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
status = i2c_start (); /* send a start bit */
if (status) {
#ifdef DEBUG_I2C
printf ("Transaction start failed: 0x%02x\n", status);
#endif
return status;
}
status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to set slave address & offset: 0x%02x\n",
status);
#endif
return status;
}
status = i2c_write_byte (data, len); /* write the data */
if (status) {
#ifdef DEBUG_I2C
printf ("Data not written: 0x%02x\n", status);
#endif
return status;
}
/* issue a stop bit */
i2c_stop ();
return 0;
}
/* 11-14-2002 Paul Marchese */
/* function to determine if an I2C device is present */
/* chip = device address of chip to check for */
/* */
/* returns 0 = sucessful, the device exists */
/* anything other than zero is failure, no device */
int i2c_probe (uchar chip)
{
/* We are just looking for an <ACK> back. */
/* To see if the device/chip is there */
#ifdef DEBUG_I2C
unsigned int i2c_status;
#endif
uchar status = 0;
unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_probe\n"));
/* set the i2c frequency */
i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
status = i2c_start (); /* send a start bit */
if (status) {
#ifdef DEBUG_I2C
printf ("Transaction start failed: 0x%02x\n", status);
#endif
return (int) status;
}
status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to set slave address: 0x%02x\n", status);
#endif
return (int) status;
}
#ifdef DEBUG_I2C
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
printf ("address %#x returned %#x\n", chip, i2c_status);
#endif
/* issue a stop bit */
i2c_stop ();
return 0; /* successful completion */
}

253
board/Marvell/common/intel_flash.c
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@ -1,253 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Hacked for the marvell db64360 eval board by
* Ingo Assmus <ingo.assmus@keymile.com>
*/
#include <common.h>
#include <mpc8xx.h>
#include "../include/mv_gen_reg.h"
#include "../include/memory.h"
#include "intel_flash.h"
/*-----------------------------------------------------------------------
* Protection Flags:
*/
#define FLAG_PROTECT_SET 0x01
#define FLAG_PROTECT_CLEAR 0x02
static void bank_reset (flash_info_t * info, int sect)
{
bank_addr_t addrw, eaddrw;
addrw = (bank_addr_t) info->start[sect];
eaddrw = BANK_ADDR_NEXT_WORD (addrw);
while (addrw < eaddrw) {
#ifdef FLASH_DEBUG
printf (" writing reset cmd to addr 0x%08lx\n",
(unsigned long) addrw);
#endif
*addrw = BANK_CMD_RST;
addrw++;
}
}
static void bank_erase_init (flash_info_t * info, int sect)
{
bank_addr_t addrw, saddrw, eaddrw;
int flag;
#ifdef FLASH_DEBUG
printf ("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG);
printf ("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1);
printf ("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2);
printf ("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT);
printf ("0x%08x BANK_CMD_RST\n", BANK_CMD_RST);
printf ("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY);
printf ("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR);
#endif
saddrw = (bank_addr_t) info->start[sect];
eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
#ifdef FLASH_DEBUG
printf ("erasing sector %d, start addr = 0x%08lx "
"(bank next word addr = 0x%08lx)\n", sect,
(unsigned long) saddrw, (unsigned long) eaddrw);
#endif
/* Disable intrs which might cause a timeout here */
flag = disable_interrupts ();
for (addrw = saddrw; addrw < eaddrw; addrw++) {
#ifdef FLASH_DEBUG
printf (" writing erase cmd to addr 0x%08lx\n",
(unsigned long) addrw);
#endif
*addrw = BANK_CMD_ERASE1;
*addrw = BANK_CMD_ERASE2;
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
}
static int bank_erase_poll (flash_info_t * info, int sect)
{
bank_addr_t addrw, saddrw, eaddrw;
int sectdone, haderr;
saddrw = (bank_addr_t) info->start[sect];
eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
sectdone = 1;
haderr = 0;
for (addrw = saddrw; addrw < eaddrw; addrw++) {
bank_word_t stat = *addrw;
#ifdef FLASH_DEBUG
printf (" checking status at addr "
"0x%08x [0x%08x]\n", (unsigned long) addrw, stat);
#endif
if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY)
sectdone = 0;
else if ((stat & BANK_STAT_ERR) != 0) {
printf (" failed on sector %d "
"(stat = 0x%08x) at "
"address 0x%p\n", sect, stat, addrw);
*addrw = BANK_CMD_CLR_STAT;
haderr = 1;
}
}
if (haderr)
return (-1);
else
return (sectdone);
}
int write_word_intel (bank_addr_t addr, bank_word_t value)
{
bank_word_t stat;
ulong start;
int flag, retval;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
*addr = BANK_CMD_PROG;
*addr = value;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
retval = 0;
/* data polling for D7 */
start = get_timer (0);
do {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
retval = 1;
goto done;
}
stat = *addr;
} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
if ((stat & BANK_STAT_ERR) != 0) {
printf ("flash program failed (stat = 0x%08lx) "
"at address 0x%08lx\n", (ulong) stat, (ulong) addr);
*addr = BANK_CMD_CLR_STAT;
retval = 3;
}
done:
/* reset to read mode */
*addr = BANK_CMD_RST;
return (retval);
}
/*-----------------------------------------------------------------------
*/
int flash_erase_intel (flash_info_t * info, int s_first, int s_last)
{
int prot, sect, haderr;
ulong start, now, last;
#ifdef FLASH_DEBUG
printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
" Bank # %d: ", s_last - s_first + 1, s_first, s_last,
(info - flash_info) + 1);
flash_print_info (info);
#endif
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sector%s will not be erased!\n", prot, (prot > 1 ? "s" : ""));
}
start = get_timer (0);
last = 0;
haderr = 0;
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
ulong estart;
int sectdone;
bank_erase_init (info, sect);
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
estart = get_timer (start);
do {
now = get_timer (start);
if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout (sect %d)\n", sect);
haderr = 1;
break;
}
#ifndef FLASH_DEBUG
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
#endif
sectdone = bank_erase_poll (info, sect);
if (sectdone < 0) {
haderr = 1;
break;
}
} while (!sectdone);
if (haderr)
break;
}
}
if (haderr > 0)
printf (" failed\n");
else
printf (" done\n");
/* reset to read mode */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
bank_reset (info, sect);
}
}
return haderr;
}

235
board/Marvell/common/misc.S
View File

@ -1,235 +0,0 @@
#include <config.h>
#include <74xx_7xx.h>
#include "version.h"
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include "../include/mv_gen_reg.h"
#ifdef CONFIG_ECC
/* Galileo specific asm code for initializing ECC */
.globl board_relocate_rom
board_relocate_rom:
mflr r7
/* update the location of the GT registers */
lis r11, CONFIG_SYS_GT_REGS@h
/* if we're using ECC, we must use the DMA engine to copy ourselves */
bl start_idma_transfer_0
bl wait_for_idma_0
bl stop_idma_engine_0
mtlr r7
blr
.globl board_init_ecc
board_init_ecc:
mflr r7
/* NOTE: r10 still contains the location we've been relocated to
* which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
/* now that we're running from ram, init the rest of main memory
* for ECC use */
lis r8, CONFIG_SYS_MONITOR_LEN@h
ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
divw r3, r10, r8
/* set up the counter, and init the starting address */
mtctr r3
li r12, 0
/* bytes per transfer */
mr r5, r8
about_to_init_ecc:
1: mr r3, r12
mr r4, r12
bl start_idma_transfer_0
bl wait_for_idma_0
bl stop_idma_engine_0
add r12, r12, r8
bdnz 1b
mtlr r7
blr
/* r3: dest addr
* r4: source addr
* r5: byte count
* r11: gt regbase
* trashes: r6, r5
*/
start_idma_transfer_0:
/* set the byte count, including the OWN bit */
mr r6, r11
ori r6, r6, CHANNEL0_DMA_BYTE_COUNT
stwbrx r5, 0, (r6)
/* set the source address */
mr r6, r11
ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
stwbrx r4, 0, (r6)
/* set the dest address */
mr r6, r11
ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
stwbrx r3, 0, (r6)
/* set the next record pointer */
li r5, 0
mr r6, r11
ori r6, r6, CHANNEL0NEXT_RECORD_POINTER
stwbrx r5, 0, (r6)
/* set the low control register */
/* bit 9 is NON chained mode, bit 31 is new style descriptors.
bit 12 is channel enable */
ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
/* 15 shifted by 16 (oris) == bit 31 */
oris r5, r5, (1 << 15)
mr r6, r11
ori r6, r6, CHANNEL0CONTROL
stwbrx r5, 0, (r6)
blr
/* this waits for the bytecount to return to zero, indicating
* that the trasfer is complete */
wait_for_idma_0:
mr r5, r11
lis r6, 0xff
ori r6, r6, 0xffff
ori r5, r5, CHANNEL0_DMA_BYTE_COUNT
1: lwbrx r4, 0, (r5)
and. r4, r4, r6
bne 1b
blr
/* this turns off channel 0 of the idma engine */
stop_idma_engine_0:
/* shut off the DMA engine */
li r5, 0
mr r6, r11
ori r6, r6, CHANNEL0CONTROL
stwbrx r5, 0, (r6)
blr
#endif
#ifdef CONFIG_SYS_BOARD_ASM_INIT
/* NOTE: trashes r3-r7 */
.globl board_asm_init
board_asm_init:
/* just move the GT registers to where they belong */
lis r3, CONFIG_SYS_DFL_GT_REGS@h
ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
lis r4, CONFIG_SYS_GT_REGS@h
ori r4, r4, CONFIG_SYS_GT_REGS@l
li r5, INTERNAL_SPACE_DECODE
/* test to see if we've already moved */
lwbrx r6, r5, r4
andi. r6, r6, 0xffff
/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
/* rlwinm r7, r4, 8, 16, 31
rlwinm r7, r4, 12, 16, 31 */ /* original */
rlwinm r7, r4, 16, 16, 31
/* -----------------------------------------------------*/
cmp cr0, r7, r6
beqlr
/* nope, have to move the registers */
lwbrx r6, r5, r3
andis. r6, r6, 0xffff
or r6, r6, r7
stwbrx r6, r5, r3
/* now, poll for the change */
1: lwbrx r7, r5, r4
cmp cr0, r7, r6
bne 1b
/* done! */
blr
#endif
/* For use of the debug LEDs */
.global led_on0_relocated
led_on0_relocated:
xor r21, r21, r21
xor r18, r18, r18
lis r18, 0xFC80
ori r18, r18, 0x8000
stw r21, 0x0(r18)
/* stw r18, 0x0(r18) */
sync
blr
.global led_off0_relocated
led_off0_relocated:
xor r21, r21, r21
xor r18, r18, r18
lis r18, 0xFC81
ori r18, r18, 0x4000
stw r21, 0x0(r18)
/* stw r18, 0x0(r18) */
sync
blr
.global led_on0
led_on0:
xor r18, r18, r18
lis r18, 0x1c80
ori r18, r18, 0x8000
stw r18, 0x0(r18)
sync
blr
.global led_off0
led_off0:
xor r18, r18, r18
lis r18, 0x1c81
ori r18, r18, 0x4000
stw r18, 0x0(r18)
sync
blr
.global led_on1
led_on1:
xor r18, r18, r18
lis r18, 0x1c80
ori r18, r18, 0xc000
stw r18, 0x0(r18)
sync
blr
.global led_off1
led_off1:
xor r18, r18, r18
lis r18, 0x1c81
ori r18, r18, 0x8000
stw r18, 0x0(r18)
sync
blr
.global led_on2
led_on2:
xor r18, r18, r18
lis r18, 0x1c81
ori r18, r18, 0x0000
stw r18, 0x0(r18)
sync
blr
.global led_off2
led_off2:
xor r18, r18, r18
lis r18, 0x1c81
ori r18, r18, 0xc000
stw r18, 0x0(r18)
sync
blr

8
board/Marvell/common/serial.c
View File

@ -21,14 +21,6 @@
#include "../include/memory.h"
#ifdef CONFIG_DB64360
#include "../db64360/mpsc.h"
#endif
#ifdef CONFIG_DB64460
#include "../db64460/mpsc.h"
#endif
#include "ns16550.h"
DECLARE_GLOBAL_DATA_PTR;

36
board/Marvell/db64360/64360.h
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@ -1,36 +0,0 @@
/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* main board support/init for the Galileo Eval board DB64360.
*/
#ifndef __64360_H__
#define __64360_H__
/* CPU Configuration bits */
#define CPU_CONF_ADDR_MISS_EN (1 << 8)
#define CPU_CONF_SINGLE_CPU (1 << 11)
#define CPU_CONF_ENDIANESS (1 << 12)
#define CPU_CONF_PIPELINE (1 << 13)
#define CPU_CONF_STOP_RETRY (1 << 17)
#define CPU_CONF_MULTI_DECODE (1 << 18)
#define CPU_CONF_DP_VALID (1 << 19)
#define CPU_CONF_PERR_PROP (1 << 22)
#define CPU_CONF_AACK_DELAY_2 (1 << 25)
#define CPU_CONF_AP_VALID (1 << 26)
#define CPU_CONF_REMAP_WR_DIS (1 << 27)
/* CPU Master Control bits */
#define CPU_MAST_CTL_ARB_EN (1 << 8)
#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
#endif /* __64360_H__ */

12
board/Marvell/db64360/Kconfig
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@ -1,12 +0,0 @@
if TARGET_DB64360
config SYS_BOARD
default "db64360"
config SYS_VENDOR
default "Marvell"
config SYS_CONFIG_NAME
default "DB64360"
endif

6
board/Marvell/db64360/MAINTAINERS
View File

@ -1,6 +0,0 @@
DB64360 BOARD
#M: -
S: Maintained
F: board/Marvell/db64360/
F: include/configs/DB64360.h
F: configs/DB64360_defconfig

13
board/Marvell/db64360/Makefile
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@ -1,13 +0,0 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = db64360.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
sdram_init.o ../common/intel_flash.o ../common/misc.o

105
board/Marvell/db64360/README
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@ -1,105 +0,0 @@
This file contains status information for the port of the U-Boot to the Marvell Development Board DB64360.
Author: Ronen Shitrit <rshitrit@il.marvell.com>
This U-Boot version is based on the work of Brian Waite and his team from Sky Computers, THANKS A LOT.
Supported CPU Types :
+++++++++++++++++++++
IBM750FX (ver 2.3)
MPC7455 (ver 2.1)
Supported CPU Cache Library:
++++++++++++++++++++++++++++
L1 and L2 only.
CPU Control:
++++++++++++
Marvell optimized CPU control settings:
Big Endian
Enable CPU pipeline
Data and address parity checking
AACK# assert after 2 cycles
U-Boot I/O Interface Support:
+++++++++++++++++++++++++++++
- Serial Interface (UART)
This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module.
- Network Interface
This LSP supports the following network devices:
o MV64360 Gigabit Ethernet Controller device
o Intel 82559 PCI NIC device
- PCI Interface
This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units:
o Local PCI configuration header control.
o External PCI configuration header control (for other agents on the bus).
o PCI configuration application. Scans and configures the PCI agents on the bus.
o PCI Internal Arbiter activation and configuration.
Memory Interface Support:
+++++++++++++++++++++++++
- DDR
o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs).
o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma.
- Devices
o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM.
o JFFS2
JFFS2 is a crash/power down safe file system for disk-less embedded devices.
This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it.
Unsupported Features:
+++++++++++++++++++++
Messaging unit - No support for MV64360 Messaging unit.
Watchdog Timer - No support for MV64360 Watchdog unit.
L3 cache - No support for L3 cache on MPC7455
Dual PCU - No support for Dual CPU
PCI-X was never tested
IDMA driver - No support for MV64360 IDMA unit.
BSP Special Considerations:
+++++++++++++++++++++++++++
- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots.
- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical.
Test Cases:
###########
UART:
+++++
Check that the UART baud rate is configured to 57600 and 115200, and check:
Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom.
Load S-Record file over the UART using Windows HyperTerminal.
Network:
++++++++
Use TFTP application to load a debugged executable and execute it.
Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC.
Memory:
+++++++
Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters:
o 128MB DIMM consist of 16 x 64Mbit devices
o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz.
o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz.
o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz.
o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz.
o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz.
o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered
For each chip select device perform data access to verify its accessibility.
Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage.
Load the U-Boot and:
use the ls command to check correct scan of the JFFS2 on the large flash.
Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage.
PCI:
++++
1)Insert different PCI cards:
Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10
on different slots (0-3) of the PCI and check:
o Correct detection of the PCI devices.
o Correct address mapping of the PCI devices.
2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot.
Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal)

922
board/Marvell/db64360/db64360.c
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@ -1,922 +0,0 @@
/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
*/
/*
* db64360.c - main board support/init for the Galileo Eval board.
*/
#include <common.h>
#include <74xx_7xx.h>
#include "../include/memory.h"
#include "../include/pci.h"
#include "../include/mv_gen_reg.h"
#include <net.h>
#include <netdev.h>
#include <linux/compiler.h>
#include "eth.h"
#include "mpsc.h"
#include "i2c.h"
#include "64360.h"
#include "mv_regs.h"
#undef DEBUG
/*#define DEBUG */
#define MAP_PCI
#ifdef DEBUG
#define DP(x) x
#else
#define DP(x)
#endif
/* ------------------------------------------------------------------------- */
/* this is the current GT register space location */
/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
/* Unfortunately, we cant change it while we are in flash, so we initialize it
* to the "final" value. This means that any debug_led calls before
* board_early_init_f wont work right (like in cpu_init_f).
* See also my_remap_gt_regs below. (NTL)
*/
void board_prebootm_init (void);
unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
int display_mem_map (void);
/* ------------------------------------------------------------------------- */
/*
* This is a version of the GT register space remapping function that
* doesn't touch globals (meaning, it's ok to run from flash.)
*
* Unfortunately, this has the side effect that a writable
* INTERNAL_REG_BASE_ADDR is impossible. Oh well.
*/
void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
{
u32 temp;
/* check and see if it's already moved */
/* original ppcboot 1.1.6 source
temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
if ((temp & 0xffff) == new_loc >> 20)
return;
temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
0xffff0000) | (new_loc >> 20);
out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
original ppcboot 1.1.6 source end */
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
if ((temp & 0xffff) == new_loc >> 16)
return;
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
0xffff0000) | (new_loc >> 16);
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
}
#ifdef CONFIG_PCI
static void gt_pci_config (void)
{
unsigned int stat;
unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
* config registers by writing ones to the bus and device.
* We then update the Virtual register with the correct value for the bus and device.
*/
if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
(stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
(stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
/* Enable master */
PCI_MASTER_ENABLE (0, SELF);
PCI_MASTER_ENABLE (1, SELF);
/* Enable PCI0/1 Mem0 and IO 0 disable all others */
GT_REG_READ (BASE_ADDR_ENABLE, &stat);
stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
<<
18);
stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
/* ronen- add write to pci remap registers for 64460.
in 64360 when writing to pci base go and overide remap automaticaly,
in 64460 it doesn't */
GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
/* PCI interface settings */
/* Timeout set to retry forever */
GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
/* ronen - enable only CS0 and Internal reg!! */
GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
/*ronen update the pci internal registers base address.*/
#ifdef MAP_PCI
for (stat = 0; stat <= PCI_HOST1; stat++)
pciWriteConfigReg (stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
SELF, CONFIG_SYS_GT_REGS);
#endif
}
#endif
/* Setup CPU interface paramaters */
static void gt_cpu_config (void)
{
cpu_t cpu = get_cpu_type ();
ulong tmp;
/* cpu configuration register */
tmp = GTREGREAD (CPU_CONFIGURATION);
/* set the SINGLE_CPU bit see MV64360 P.399 */
#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
tmp |= CPU_CONF_SINGLE_CPU;
#endif
tmp &= ~CPU_CONF_AACK_DELAY_2;
tmp |= CPU_CONF_DP_VALID;
tmp |= CPU_CONF_AP_VALID;
tmp |= CPU_CONF_PIPELINE;
GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
/* CPU master control register */
tmp = GTREGREAD (CPU_MASTER_CONTROL);
tmp |= CPU_MAST_CTL_ARB_EN;
if ((cpu == CPU_7400) ||
(cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
tmp |= CPU_MAST_CTL_CLEAN_BLK;
tmp |= CPU_MAST_CTL_FLUSH_BLK;
} else {
/* cleanblock must be cleared for CPUs
* that do not support this command (603e, 750)
* see Res#1 */
tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
}
GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
}
/*
* board_early_init_f.
*
* set up gal. device mappings, etc.
*/
int board_early_init_f (void)
{
uchar sram_boot = 0;
/*
* set up the GT the way the kernel wants it
* the call to move the GT register space will obviously
* fail if it has already been done, but we're going to assume
* that if it's not at the power-on location, it's where we put
* it last time. (huber)
*/
my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
/* No PCI in first release of Port To_do: enable it. */
#ifdef CONFIG_PCI
gt_pci_config ();
#endif
/* mask all external interrupt sources */
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
/* new in MV6436x */
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
/* --------------------- */
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
/* does not exist in MV6436x
GT_REG_WRITE(CPU_INT_0_MASK, 0);
GT_REG_WRITE(CPU_INT_1_MASK, 0);
GT_REG_WRITE(CPU_INT_2_MASK, 0);
GT_REG_WRITE(CPU_INT_3_MASK, 0);
--------------------- */
/* ----- DEVICE BUS SETTINGS ------ */
/*
* EVB
* 0 - SRAM ????
* 1 - RTC ????
* 2 - UART ????
* 3 - Flash checked 32Bit Intel Strata
* boot - BootCS checked 8Bit 29LV040B
*
* Zuma
* 0 - Flash
* boot - BootCS
*/
/*
* the dual 7450 module requires burst access to the boot
* device, so the serial rom copies the boot device to the
* on-board sram on the eval board, and updates the correct
* registers to boot from the sram. (device0)
*/
if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
sram_boot = 1;
if (!sram_boot)
memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
/* configure device timing */
#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */
if (!sram_boot)
GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
#endif
#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */
GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
#endif
#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */
GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
#endif
#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
/* detect if we are booting from the 32 bit flash */
if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
/* 32 bit boot flash */
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
CONFIG_SYS_32BIT_BOOT_PAR);
} else {
/* 8 bit boot flash */
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
}
#else
/* 8 bit boot flash only */
/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
#endif
gt_cpu_config ();
/* MPP setup */
GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
DEBUG_LED0_ON ();
DEBUG_LED1_ON ();
DEBUG_LED2_ON ();
return 0;
}
/* various things to do after relocation */
int misc_init_r ()
{
icache_enable ();
#ifdef CONFIG_SYS_L2
l2cache_enable ();
#endif
#ifdef CONFIG_MPSC
mpsc_sdma_init ();
mpsc_init2 ();
#endif
#if 0
/* disable the dcache and MMU */
dcache_lock ();
#endif
return 0;
}
void after_reloc (ulong dest_addr, gd_t * gd)
{
/* check to see if we booted from the sram. If so, move things
* back to the way they should be. (we're running from main
* memory at this point now */
if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
}
display_mem_map ();
/* now, jump to the main ppcboot board init code */
board_init_r (gd, dest_addr);
/* NOTREACHED */
}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
* right now, assume borad type. (there is just one...after all)
*/
int checkboard (void)
{
int l_type = 0;
printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
return (l_type);
}
/* utility functions */
void debug_led (int led, int mode)
{
volatile int *addr = 0;
__maybe_unused int dummy;
if (mode == 1) {
switch (led) {
case 0:
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x08000);
break;
case 1:
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x0c000);
break;
case 2:
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x10000);
break;
}
} else if (mode == 0) {
switch (led) {
case 0:
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x14000);
break;
case 1:
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x18000);
break;
case 2:
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x1c000);
break;
}
}
dummy = *addr;
}
int display_mem_map (void)
{
int i, j;
unsigned int base, size, width;
/* SDRAM */
printf ("SD (DDR) RAM\n");
for (i = 0; i <= BANK3; i++) {
base = memoryGetBankBaseAddress (i);
size = memoryGetBankSize (i);
if (size != 0) {
printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
i, base, size >> 20);
}
}
/* CPU's PCI windows */
for (i = 0; i <= PCI_HOST1; i++) {
printf ("\nCPU's PCI %d windows\n", i);
base = pciGetSpaceBase (i, PCI_IO);
size = pciGetSpaceSize (i, PCI_IO);
printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
size >> 20);
for (j = 0;
j <=
PCI_REGION0
/*ronen currently only first PCI MEM is used 3 */ ;
j++) {
base = pciGetSpaceBase (i, j);
size = pciGetSpaceSize (i, j);
printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
}
}
/* Devices */
printf ("\nDEVICES\n");
for (i = 0; i <= DEVICE3; i++) {
base = memoryGetDeviceBaseAddress (i);
size = memoryGetDeviceSize (i);
width = memoryGetDeviceWidth (i) * 8;
printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
if (i == 0)
printf ("\t- EXT SRAM (actual - 1M)\n");
else if (i == 1)
printf ("\t- RTC\n");
else if (i == 2)
printf ("\t- UART\n");
else
printf ("\t- LARGE FLASH\n");
}
/* Bootrom */
base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
size = memoryGetDeviceSize (BOOT_DEVICE);
width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n",
base, size >> 20, width);
return (0);
}
/* DRAM check routines copied from gw8260 */
#if defined (CONFIG_SYS_DRAM_TEST)
/*********************************************************************/
/* NAME: move64() - moves a double word (64-bit) */
/* */
/* DESCRIPTION: */
/* this function performs a double word move from the data at */
/* the source pointer to the location at the destination pointer. */
/* */
/* INPUTS: */
/* unsigned long long *src - pointer to data to move */
/* */
/* OUTPUTS: */
/* unsigned long long *dest - pointer to locate to move data */
/* */
/* RETURNS: */
/* None */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* May cloober fr0. */
/* */
/*********************************************************************/
static void move64 (unsigned long long *src, unsigned long long *dest)
{
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
"stfd 0, 0(4)" /* *dest = fpr0 */
: : : "fr0"); /* Clobbers fr0 */
return;
}
#if defined (CONFIG_SYS_DRAM_TEST_DATA)
unsigned long long pattern[] = {
0xaaaaaaaaaaaaaaaaULL,
0xccccccccccccccccULL,
0xf0f0f0f0f0f0f0f0ULL,
0xff00ff00ff00ff00ULL,
0xffff0000ffff0000ULL,
0xffffffff00000000ULL,
0x00000000ffffffffULL,
0x0000ffff0000ffffULL,
0x00ff00ff00ff00ffULL,
0x0f0f0f0f0f0f0f0fULL,
0x3333333333333333ULL,
0x5555555555555555ULL,
};
/*********************************************************************/
/* NAME: mem_test_data() - test data lines for shorts and opens */
/* */
/* DESCRIPTION: */
/* Tests data lines for shorts and opens by forcing adjacent data */
/* to opposite states. Because the data lines could be routed in */
/* an arbitrary manner the must ensure test patterns ensure that */
/* every case is tested. By using the following series of binary */
/* patterns every combination of adjacent bits is test regardless */
/* of routing. */
/* */
/* ...101010101010101010101010 */
/* ...110011001100110011001100 */
/* ...111100001111000011110000 */
/* ...111111110000000011111111 */
/* */
/* Carrying this out, gives us six hex patterns as follows: */
/* */
/* 0xaaaaaaaaaaaaaaaa */
/* 0xcccccccccccccccc */
/* 0xf0f0f0f0f0f0f0f0 */
/* 0xff00ff00ff00ff00 */
/* 0xffff0000ffff0000 */
/* 0xffffffff00000000 */
/* */
/* The number test patterns will always be given by: */
/* */
/* log(base 2)(number data bits) = log2 (64) = 6 */
/* */
/* To test for short and opens to other signals on our boards. we */
/* simply */
/* test with the 1's complemnt of the paterns as well. */
/* */
/* OUTPUTS: */
/* Displays failing test pattern */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* Assumes only one one SDRAM bank */
/* */
/*********************************************************************/
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
for (i = 0; i < num_patterns; i++) {
move64 (&(pattern[i]), pmem);
move64 (pmem, &temp64);
/* hi = (temp64>>32) & 0xffffffff; */
/* lo = temp64 & 0xffffffff; */
/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
hi = (pattern[i] >> 32) & 0xffffffff;
lo = pattern[i] & 0xffffffff;
/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
if (temp64 != pattern[i]) {
printf ("\n Data Test Failed, pattern 0x%08x%08x",
hi, lo);
return 1;
}
}
return 0;
}
#endif /* CONFIG_SYS_DRAM_TEST_DATA */
#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
/*********************************************************************/
/* NAME: mem_test_address() - test address lines */
/* */
/* DESCRIPTION: */
/* This function performs a test to verify that each word im */
/* memory is uniquly addressable. The test sequence is as follows: */
/* */
/* 1) write the address of each word to each word. */
/* 2) verify that each location equals its address */
/* */
/* OUTPUTS: */
/* Displays failing test pattern and address */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int mem_test_address (void)
{
volatile unsigned int *pmem =
(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
unsigned int i;
/* write address to each location */
for (i = 0; i < size; i++) {
pmem[i] = i;
}
/* verify each loaction */
for (i = 0; i < size; i++) {
if (pmem[i] != i) {
printf ("\n Address Test Failed at 0x%x", i);
return 1;
}
}
return 0;
}
#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
#if defined (CONFIG_SYS_DRAM_TEST_WALK)
/*********************************************************************/
/* NAME: mem_march() - memory march */
/* */
/* DESCRIPTION: */
/* Marches up through memory. At each location verifies rmask if */
/* read = 1. At each location write wmask if write = 1. Displays */
/* failing address and pattern. */
/* */
/* INPUTS: */
/* volatile unsigned long long * base - start address of test */
/* unsigned int size - number of dwords(64-bit) to test */
/* unsigned long long rmask - read verify mask */
/* unsigned long long wmask - wrtie verify mask */
/* short read - verifies rmask if read = 1 */
/* short write - writes wmask if write = 1 */
/* */
/* OUTPUTS: */
/* Displays failing test pattern and address */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int mem_march (volatile unsigned long long *base,
unsigned int size,
unsigned long long rmask,
unsigned long long wmask, short read, short write)
{
unsigned int i;
unsigned long long temp = 0;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
if (read != 0) {
/* temp = base[i]; */
move64 ((unsigned long long *) &(base[i]), &temp);
if (rmask != temp) {
hitemp = (temp >> 32) & 0xffffffff;
lotemp = temp & 0xffffffff;
himask = (rmask >> 32) & 0xffffffff;
lomask = rmask & 0xffffffff;
printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
return 1;
}
}
if (write != 0) {
/* base[i] = wmask; */
move64 (&wmask, (unsigned long long *) &(base[i]));
}
}
return 0;
}
#endif /* CONFIG_SYS_DRAM_TEST_WALK */
/*********************************************************************/
/* NAME: mem_test_walk() - a simple walking ones test */
/* */
/* DESCRIPTION: */
/* Performs a walking ones through entire physical memory. The */
/* test uses as series of memory marches, mem_march(), to verify */
/* and write the test patterns to memory. The test sequence is as */
/* follows: */
/* 1) march writing 0000...0001 */
/* 2) march verifying 0000...0001 , writing 0000...0010 */
/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
/* the write mask equals 1000...0000 */
/* 4) march verifying 1000...0000 */
/* The test fails if any of the memory marches return a failure. */
/* */
/* OUTPUTS: */
/* Displays which pass on the memory test is executing */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int mem_test_walk (void)
{
unsigned long long mask;
volatile unsigned long long *pmem =
(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
unsigned int i;
mask = 0x01;
printf ("Initial Pass");
mem_march (pmem, size, 0x0, 0x1, 0, 1);
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
printf (" ");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
for (i = 0; i < 63; i++) {
printf ("Pass %2d", i + 2);
if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
/*printf("mask: 0x%x, pass: %d, ", mask, i); */
return 1;
}
mask = mask << 1;
printf ("\b\b\b\b\b\b\b");
}
printf ("Last Pass");
if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
/* printf("mask: 0x%x", mask); */
return 1;
}
printf ("\b\b\b\b\b\b\b\b\b");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b");
return 0;
}
/*********************************************************************/
/* NAME: testdram() - calls any enabled memory tests */
/* */
/* DESCRIPTION: */
/* Runs memory tests if the environment test variables are set to */
/* 'y'. */
/* */
/* INPUTS: */
/* testdramdata - If set to 'y', data test is run. */
/* testdramaddress - If set to 'y', address test is run. */
/* testdramwalk - If set to 'y', walking ones test is run */
/* */
/* OUTPUTS: */
/* None */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int testdram (void)
{
int rundata, runaddress, runwalk;
rundata = getenv_yesno("testdramdata") == 1;
runaddress = getenv_yesno("testdramaddress") == 1;
runwalk = getenv_yesno("testdramwalk") == 1;
/* rundata = 1; */
/* runaddress = 0; */
/* runwalk = 0; */
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
}
#ifdef CONFIG_SYS_DRAM_TEST_DATA
if (rundata == 1) {
printf ("Test DATA ... ");
if (mem_test_data () == 1) {
printf ("failed \n");
return 1;
} else
printf ("ok \n");
}
#endif
#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
if (runaddress == 1) {
printf ("Test ADDRESS ... ");
if (mem_test_address () == 1) {
printf ("failed \n");
return 1;
} else
printf ("ok \n");
}
#endif
#ifdef CONFIG_SYS_DRAM_TEST_WALK
if (runwalk == 1) {
printf ("Test WALKING ONEs ... ");
if (mem_test_walk () == 1) {
printf ("failed \n");
return 1;
} else
printf ("ok \n");
}
#endif
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf ("passed\n");
}
return 0;
}
#endif /* CONFIG_SYS_DRAM_TEST */
/* ronen - the below functions are used by the bootm function */
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
/* - we turn off the RX gig dmas - to prevent the dma from overunning */
/* the kernel data areas. */
/* - we diable and invalidate the icache and dcache. */
void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
{
u32 temp;
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
if ((temp & 0xffff) == new_loc >> 16)
return;
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
0xffff0000) | (new_loc >> 16);
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
new_loc |
(INTERNAL_SPACE_DECODE)))))
!= temp);
}
void board_prebootm_init ()
{
/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
/* Stop GigE Rx DMA engines */
GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
/* Relocate MV64360 internal regs */
my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
icache_disable ();
dcache_disable ();
}
int board_eth_init(bd_t *bis)
{
int ret;
ret = pci_eth_init(bis);
if (!ret)
ret = mv6436x_eth_initialize(bis);
return ret;
}

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board/Marvell/db64360/eth.h
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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* eth.h - header file for the polled mode GT ethernet driver
*/
#ifndef __EVB64360_ETH_H__
#define __EVB64360_ETH_H__
#include <asm/types.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <common.h>
int db64360_eth0_poll(void);
int db64360_eth0_transmit(unsigned int s, volatile char *p);
void db64360_eth0_disable(void);
bool network_start(bd_t *bis);
int mv6436x_eth_initialize(bd_t *);
#endif /* __EVB64360_ETH_H__ */

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board/Marvell/db64360/mpsc.c
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board/Marvell/db64360/mpsc.h
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/*
* (C) Copyright 2001
* John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*************************************************************************
* changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
*
************************************************************************/
/*
* mpsc.h - header file for MPSC in uart mode (console driver)
*/
#ifndef __MPSC_H__
#define __MPSC_H__
/* include actual Galileo defines */
#include "../include/mv_gen_reg.h"
/* driver related defines */
int mpsc_init(int baud);
void mpsc_sdma_init(void);
void mpsc_init2(void);
int galbrg_set_baudrate(int channel, int rate);
int mpsc_putchar_early(char ch);
char mpsc_getchar_debug(void);
int mpsc_test_char_debug(void);
int mpsc_test_char_sdma(void);
extern int (*mpsc_putchar)(char ch);
extern char (*mpsc_getchar)(void);
extern int (*mpsc_test_char)(void);
#define CHANNEL CONFIG_MPSC_PORT
#define TX_DESC 5
#define RX_DESC 20
#define DESC_FIRST 0x00010000
#define DESC_LAST 0x00020000
#define DESC_OWNER_BIT 0x80000000
#define TX_DEMAND 0x00800000
#define TX_STOP 0x00010000
#define RX_ENABLE 0x00000080
#define SDMA_RX_ABORT (1 << 15)
#define SDMA_TX_ABORT (1 << 31)
#define MPSC_TX_ABORT (1 << 7)
#define MPSC_RX_ABORT (1 << 23)
#define MPSC_ENTER_HUNT (1 << 31)
/* MPSC defines */
#define GALMPSC_CONNECT 0x1
#define GALMPSC_DISCONNECT 0x0
#define GALMPSC_UART 0x1
#define GALMPSC_STOP_BITS_1 0x0
#define GALMPSC_STOP_BITS_2 0x1
#define GALMPSC_CHAR_LENGTH_8 0x3
#define GALMPSC_CHAR_LENGTH_7 0x2
#define GALMPSC_PARITY_ODD 0x0
#define GALMPSC_PARITY_EVEN 0x2
#define GALMPSC_PARITY_MARK 0x3
#define GALMPSC_PARITY_SPACE 0x1
#define GALMPSC_PARITY_NONE -1
#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
#define GALMPSC_REG_GAP 0x1000
#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
#define GALSDMA_COMMAND_FIRST (1 << 16)
#define GALSDMA_COMMAND_LAST (1 << 17)
#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
#define GALSDMA_COMMAND_AUTO (1 << 30)
#define GALSDMA_COMMAND_OWNER (1 << 31)
#define GALSDMA_RX 0
#define GALSDMA_TX 1
/* CHANNEL2 should be CHANNEL1, according to documentation,
* but to work with the current GTREGS file...
*/
#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
#define GALSDMA_REG_DIFF 0x2000
/* WRONG in gt64260R.h */
#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
#define GALMPSC_0_INT_CAUSE 0xb804
#define GALMPSC_0_INT_MASK 0xb884
#define GALSDMA_MODE_UART 0
#define GALSDMA_MODE_BISYNC 1
#define GALSDMA_MODE_HDLC 2
#define GALSDMA_MODE_TRANSPARENT 3
#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
#define GALBRG_REG_GAP 0x0008
#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
#endif /* __MPSC_H__ */

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board/Marvell/db64360/mv_eth.c
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board/Marvell/db64360/mv_eth.h
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/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
*
* based on - Driver for MV64360X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* mv_eth.h - header file for the polled mode GT ethernet driver
*/
#ifndef __DB64360_ETH_H__
#define __DB64360_ETH_H__
#include <asm/types.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <common.h>
#include <net.h>
#include "mv_regs.h"
#include <asm/errno.h>
/*************************************************************************
**************************************************************************
**************************************************************************
* The first part is the high level driver of the gigE ethernet ports. *
**************************************************************************
**************************************************************************
*************************************************************************/
/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
#ifndef MAX_SKB_FRAGS
#define MAX_SKB_FRAGS 0
#endif
/* Port attributes */
/*#define MAX_RX_QUEUE_NUM 8*/
/*#define MAX_TX_QUEUE_NUM 8*/
#define MAX_RX_QUEUE_NUM 1
#define MAX_TX_QUEUE_NUM 1
/* Use one TX queue and one RX queue */
#define MV64360_TX_QUEUE_NUM 1
#define MV64360_RX_QUEUE_NUM 1
/*
* Number of RX / TX descriptors on RX / TX rings.
* Note that allocating RX descriptors is done by allocating the RX
* ring AND a preallocated RX buffers (skb's) for each descriptor.
* The TX descriptors only allocates the TX descriptors ring,
* with no pre allocated TX buffers (skb's are allocated by higher layers.
*/
/* Default TX ring size is 10 descriptors */
#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
#else
#define MV64360_TX_QUEUE_SIZE 4
#endif
/* Default RX ring size is 4 descriptors */
#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE
#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
#else
#define MV64360_RX_QUEUE_SIZE 4
#endif
#ifdef CONFIG_RX_BUFFER_SIZE
#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
#else
#define MV64360_RX_BUFFER_SIZE 1600
#endif
#ifdef CONFIG_TX_BUFFER_SIZE
#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
#else
#define MV64360_TX_BUFFER_SIZE 1600
#endif
/*
* Network device statistics. Akin to the 2.0 ether stats but
* with byte counters.
*/
struct net_device_stats
{
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_errors; /* bad packets received */
unsigned long tx_errors; /* packet transmit problems */
unsigned long rx_dropped; /* no space in linux buffers */
unsigned long tx_dropped; /* no space available in linux */
unsigned long multicast; /* multicast packets received */
unsigned long collisions;
/* detailed rx_errors: */
unsigned long rx_length_errors;
unsigned long rx_over_errors; /* receiver ring buff overflow */
unsigned long rx_crc_errors; /* recved pkt with crc error */
unsigned long rx_frame_errors; /* recv'd frame alignment error */
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
unsigned long rx_missed_errors; /* receiver missed packet */
/* detailed tx_errors */
unsigned long tx_aborted_errors;
unsigned long tx_carrier_errors;
unsigned long tx_fifo_errors;
unsigned long tx_heartbeat_errors;
unsigned long tx_window_errors;
/* for cslip etc */
unsigned long rx_compressed;
unsigned long tx_compressed;
};
/* Private data structure used for ethernet device */
struct mv64360_eth_priv {
unsigned int port_num;
struct net_device_stats *stats;
/* to buffer area aligned */
char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
/* Size of Tx Ring per queue */
unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
/* Size of Rx Ring per queue */
unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
/* Magic Number for Ethernet running */
unsigned int eth_running;
};
int mv64360_eth_init (struct eth_device *dev);
int mv64360_eth_stop (struct eth_device *dev);
int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
int mv64360_eth_open (struct eth_device *dev);
/*************************************************************************
**************************************************************************
**************************************************************************
* The second part is the low level driver of the gigE ethernet ports. *
**************************************************************************
**************************************************************************
*************************************************************************/
/********************************************************************************
* Header File for : MV-643xx network interface header
*
* DESCRIPTION:
* This header file contains macros typedefs and function declaration for
* the Marvell Gig Bit Ethernet Controller.
*
* DEPENDENCIES:
* None.
*
*******************************************************************************/
#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
#ifdef CONFIG_MV64360_SRAM_CACHEABLE
/* In case SRAM is cacheable but not cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) \
{ \
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
}
#else
/* In case SRAM is cache coherent or non-cacheable */
#define D_CACHE_FLUSH_LINE(addr, offset) ;
#endif
#else
#ifdef CONFIG_NOT_COHERENT_CACHE
/* In case of descriptors on DDR but not cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) \
{ \
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
}
#else
/* In case of descriptors on DDR and cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) ;
#endif /* CONFIG_NOT_COHERENT_CACHE */
#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
#define CPU_PIPE_FLUSH \
{ \
__asm__ __volatile__ ("eieio"); \
}
/* defines */
/* Default port configuration value */
#define PORT_CONFIG_VALUE \
ETH_UNICAST_NORMAL_MODE | \
ETH_DEFAULT_RX_QUEUE_0 | \
ETH_DEFAULT_RX_ARP_QUEUE_0 | \
ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
ETH_RECEIVE_BC_IF_IP | \
ETH_RECEIVE_BC_IF_ARP | \
ETH_CAPTURE_TCP_FRAMES_DIS | \
ETH_CAPTURE_UDP_FRAMES_DIS | \
ETH_DEFAULT_RX_TCP_QUEUE_0 | \
ETH_DEFAULT_RX_UDP_QUEUE_0 | \
ETH_DEFAULT_RX_BPDU_QUEUE_0
/* Default port extend configuration value */
#define PORT_CONFIG_EXTEND_VALUE \
ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
ETH_PARTITION_DISABLE
/* Default sdma control value */
#ifdef CONFIG_NOT_COHERENT_CACHE
#define PORT_SDMA_CONFIG_VALUE \
ETH_RX_BURST_SIZE_16_64BIT | \
GT_ETH_IPG_INT_RX(0) | \
ETH_TX_BURST_SIZE_16_64BIT;
#else
#define PORT_SDMA_CONFIG_VALUE \
ETH_RX_BURST_SIZE_4_64BIT | \
GT_ETH_IPG_INT_RX(0) | \
ETH_TX_BURST_SIZE_4_64BIT;
#endif
#define GT_ETH_IPG_INT_RX(value) \
((value & 0x3fff) << 8)
/* Default port serial control value */
#define PORT_SERIAL_CONTROL_VALUE \
ETH_FORCE_LINK_PASS | \
ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
ETH_ADV_SYMMETRIC_FLOW_CTRL | \
ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
ETH_FORCE_BP_MODE_NO_JAM | \
BIT9 | \
ETH_DO_NOT_FORCE_LINK_FAIL | \
ETH_RETRANSMIT_16_ETTEMPTS | \
ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
ETH_DTE_ADV_0 | \
ETH_DISABLE_AUTO_NEG_BYPASS | \
ETH_AUTO_NEG_NO_CHANGE | \
ETH_MAX_RX_PACKET_1552BYTE | \
ETH_CLR_EXT_LOOPBACK | \
ETH_SET_FULL_DUPLEX_MODE | \
ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
#define RX_BUFFER_MAX_SIZE 0xFFFF
#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
#define RX_BUFFER_MIN_SIZE 0x8
#define TX_BUFFER_MIN_SIZE 0x8
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
/* MAC accepet/reject macros */
#define ACCEPT_MAC_ADDR 0
#define REJECT_MAC_ADDR 1
/* Size of a Tx/Rx descriptor used in chain list data structure */
#define RX_DESC_ALIGNED_SIZE 0x20
#define TX_DESC_ALIGNED_SIZE 0x20
/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
#define TX_BUF_OFFSET_IN_DESC 0x18
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Gap define */
#define ETH_BAR_GAP 0x8
#define ETH_SIZE_REG_GAP 0x8
#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
#define ETH_PORT_ACCESS_CTRL_GAP 0x4
/* Gigabit Ethernet Unit Global Registers */
/* MIB Counters register definitions */
#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
#define ETH_MIB_FRAMES_64_OCTETS 0x20
#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
#define ETH_MIB_GOOD_FRAMES_SENT 0x40
#define ETH_MIB_EXCESSIVE_COLLISION 0x44
#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
#define ETH_MIB_FC_SENT 0x54
#define ETH_MIB_GOOD_FC_RECEIVED 0x58
#define ETH_MIB_BAD_FC_RECEIVED 0x5c
#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
#define ETH_MIB_OVERSIZE_RECEIVED 0x68
#define ETH_MIB_JABBER_RECEIVED 0x6c
#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
#define ETH_MIB_BAD_CRC_EVENT 0x74
#define ETH_MIB_COLLISION 0x78
#define ETH_MIB_LATE_COLLISION 0x7c
/* Port serial status reg (PSR) */
#define ETH_INTERFACE_GMII_MII 0
#define ETH_INTERFACE_PCM BIT0
#define ETH_LINK_IS_DOWN 0
#define ETH_LINK_IS_UP BIT1
#define ETH_PORT_AT_HALF_DUPLEX 0
#define ETH_PORT_AT_FULL_DUPLEX BIT2
#define ETH_RX_FLOW_CTRL_DISABLED 0
#define ETH_RX_FLOW_CTRL_ENBALED BIT3
#define ETH_GMII_SPEED_100_10 0
#define ETH_GMII_SPEED_1000 BIT4
#define ETH_MII_SPEED_10 0
#define ETH_MII_SPEED_100 BIT5
#define ETH_NO_TX 0
#define ETH_TX_IN_PROGRESS BIT7
#define ETH_BYPASS_NO_ACTIVE 0
#define ETH_BYPASS_ACTIVE BIT8
#define ETH_PORT_NOT_AT_PARTITION_STATE 0
#define ETH_PORT_AT_PARTITION_STATE BIT9
#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
#define ETH_PORT_TX_FIFO_EMPTY BIT10
/* These macros describes the Port configuration reg (Px_cR) bits */
#define ETH_UNICAST_NORMAL_MODE 0
#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
#define ETH_DEFAULT_RX_QUEUE_0 0
#define ETH_DEFAULT_RX_QUEUE_1 BIT1
#define ETH_DEFAULT_RX_QUEUE_2 BIT2
#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
#define ETH_DEFAULT_RX_QUEUE_4 BIT3
#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
#define ETH_RECEIVE_BC_IF_IP 0
#define ETH_REJECT_BC_IF_IP BIT8
#define ETH_RECEIVE_BC_IF_ARP 0
#define ETH_REJECT_BC_IF_ARP BIT9
#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
#define ETH_CAPTURE_TCP_FRAMES_DIS 0
#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
#define ETH_CAPTURE_UDP_FRAMES_DIS 0
#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
#define ETH_CLASSIFY_EN BIT0
#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
#define ETH_PARTITION_DISABLE 0
#define ETH_PARTITION_ENABLE BIT2
/* Tx/Rx queue command reg (RQCR/TQCR)*/
#define ETH_QUEUE_0_ENABLE BIT0
#define ETH_QUEUE_1_ENABLE BIT1
#define ETH_QUEUE_2_ENABLE BIT2
#define ETH_QUEUE_3_ENABLE BIT3
#define ETH_QUEUE_4_ENABLE BIT4
#define ETH_QUEUE_5_ENABLE BIT5
#define ETH_QUEUE_6_ENABLE BIT6
#define ETH_QUEUE_7_ENABLE BIT7
#define ETH_QUEUE_0_DISABLE BIT8
#define ETH_QUEUE_1_DISABLE BIT9
#define ETH_QUEUE_2_DISABLE BIT10
#define ETH_QUEUE_3_DISABLE BIT11
#define ETH_QUEUE_4_DISABLE BIT12
#define ETH_QUEUE_5_DISABLE BIT13
#define ETH_QUEUE_6_DISABLE BIT14
#define ETH_QUEUE_7_DISABLE BIT15
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
#define ETH_RIFB BIT0
#define ETH_RX_BURST_SIZE_1_64BIT 0
#define ETH_RX_BURST_SIZE_2_64BIT BIT1
#define ETH_RX_BURST_SIZE_4_64BIT BIT2
#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
#define ETH_RX_BURST_SIZE_16_64BIT BIT3
#define ETH_BLM_RX_NO_SWAP BIT4
#define ETH_BLM_RX_BYTE_SWAP 0
#define ETH_BLM_TX_NO_SWAP BIT5
#define ETH_BLM_TX_BYTE_SWAP 0
#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
#define ETH_DESCRIPTORS_NO_SWAP 0
#define ETH_TX_BURST_SIZE_1_64BIT 0
#define ETH_TX_BURST_SIZE_2_64BIT BIT22
#define ETH_TX_BURST_SIZE_4_64BIT BIT23
#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
#define ETH_TX_BURST_SIZE_16_64BIT BIT24
/* These macros describes the Port serial control reg (PSCR) bits */
#define ETH_SERIAL_PORT_DISABLE 0
#define ETH_SERIAL_PORT_ENABLE BIT0
#define ETH_FORCE_LINK_PASS BIT1
#define ETH_DO_NOT_FORCE_LINK_PASS 0
#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
#define ETH_ADV_NO_FLOW_CTRL 0
#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
#define ETH_FORCE_BP_MODE_NO_JAM 0
#define ETH_FORCE_BP_MODE_JAM_TX BIT7
#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
#define ETH_FORCE_LINK_FAIL 0
#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
#define ETH_RETRANSMIT_16_ETTEMPTS 0
#define ETH_RETRANSMIT_FOREVER BIT11
#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
#define ETH_DTE_ADV_0 0
#define ETH_DTE_ADV_1 BIT14
#define ETH_DISABLE_AUTO_NEG_BYPASS 0
#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
#define ETH_AUTO_NEG_NO_CHANGE 0
#define ETH_RESTART_AUTO_NEG BIT16
#define ETH_MAX_RX_PACKET_1518BYTE 0
#define ETH_MAX_RX_PACKET_1522BYTE BIT17
#define ETH_MAX_RX_PACKET_1552BYTE BIT18
#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
#define ETH_MAX_RX_PACKET_9192BYTE BIT19
#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
#define ETH_SET_EXT_LOOPBACK BIT20
#define ETH_CLR_EXT_LOOPBACK 0
#define ETH_SET_FULL_DUPLEX_MODE BIT21
#define ETH_SET_HALF_DUPLEX_MODE 0
#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
#define ETH_SET_GMII_SPEED_TO_10_100 0
#define ETH_SET_GMII_SPEED_TO_1000 BIT23
#define ETH_SET_MII_SPEED_TO_10 0
#define ETH_SET_MII_SPEED_TO_100 BIT24
/* SMI reg */
#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
#define ETH_ERROR_SUMMARY (BIT0)
/* Tx & Rx descriptors command */
#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
/* Tx descriptors status */
#define ETH_LC_ERROR (0 )
#define ETH_UR_ERROR (BIT1 )
#define ETH_RL_ERROR (BIT2 )
#define ETH_LLC_SNAP_FORMAT (BIT9 )
/* Rx descriptors status */
#define ETH_CRC_ERROR (0 )
#define ETH_OVERRUN_ERROR (BIT1 )
#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
#define ETH_VLAN_TAGGED (BIT19)
#define ETH_BPDU_FRAME (BIT20)
#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
#define ETH_OTHER_FRAME_TYPE (BIT22)
#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
#define ETH_FRAME_HEADER_OK (BIT25)
#define ETH_RX_LAST_DESC (BIT26)
#define ETH_RX_FIRST_DESC (BIT27)
#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
#define ETH_RX_ENABLE_INTERRUPT (BIT29)
#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
/* Rx descriptors byte count */
#define ETH_FRAME_FRAGMENTED (BIT2)
/* Tx descriptors command */
#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
#define ETH_FRAME_SET_TO_VLAN (BIT15)
#define ETH_TCP_FRAME (0 )
#define ETH_UDP_FRAME (BIT16)
#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
#define ETH_ZERO_PADDING (BIT19)
#define ETH_TX_LAST_DESC (BIT20)
#define ETH_TX_FIRST_DESC (BIT21)
#define ETH_GEN_CRC (BIT22)
#define ETH_TX_ENABLE_INTERRUPT (BIT23)
#define ETH_AUTO_MODE (BIT30)
/* Address decode parameters */
/* Ethernet Base Address Register bits */
#define EBAR_TARGET_DRAM 0x00000000
#define EBAR_TARGET_DEVICE 0x00000001
#define EBAR_TARGET_CBS 0x00000002
#define EBAR_TARGET_PCI0 0x00000003
#define EBAR_TARGET_PCI1 0x00000004
#define EBAR_TARGET_CUNIT 0x00000005
#define EBAR_TARGET_AUNIT 0x00000006
#define EBAR_TARGET_GUNIT 0x00000007
/* Window attributes */
#define EBAR_ATTR_DRAM_CS0 0x00000E00
#define EBAR_ATTR_DRAM_CS1 0x00000D00
#define EBAR_ATTR_DRAM_CS2 0x00000B00
#define EBAR_ATTR_DRAM_CS3 0x00000700
/* DRAM Target interface */
#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
/* Device Bus Target interface */
#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
/* PCI Target interface */
#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
/* CPU 60x bus or internal SRAM interface */
#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
#define EBAR_ATTR_CBS_SRAM 0x00000000
#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
/* Window access control */
#define EWIN_ACCESS_NOT_ALLOWED 0
#define EWIN_ACCESS_READ_ONLY BIT0
#define EWIN_ACCESS_FULL (BIT1 | BIT0)
#define EWIN0_ACCESS_MASK 0x0003
#define EWIN1_ACCESS_MASK 0x000C
#define EWIN2_ACCESS_MASK 0x0030
#define EWIN3_ACCESS_MASK 0x00C0
/* typedefs */
typedef enum _eth_port
{
ETH_0 = 0,
ETH_1 = 1,
ETH_2 = 2
}ETH_PORT;
typedef enum _eth_func_ret_status
{
ETH_OK, /* Returned as expected. */
ETH_ERROR, /* Fundamental error. */
ETH_RETRY, /* Could not process request. Try later. */
ETH_END_OF_JOB, /* Ring has nothing to process. */
ETH_QUEUE_FULL, /* Ring resource error. */
ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
}ETH_FUNC_RET_STATUS;
typedef enum _eth_queue
{
ETH_Q0 = 0,
ETH_Q1 = 1,
ETH_Q2 = 2,
ETH_Q3 = 3,
ETH_Q4 = 4,
ETH_Q5 = 5,
ETH_Q6 = 6,
ETH_Q7 = 7
} ETH_QUEUE;
typedef enum _addr_win
{
ETH_WIN0,
ETH_WIN1,
ETH_WIN2,
ETH_WIN3,
ETH_WIN4,
ETH_WIN5
} ETH_ADDR_WIN;
typedef enum _eth_target
{
ETH_TARGET_DRAM ,
ETH_TARGET_DEVICE,
ETH_TARGET_CBS ,
ETH_TARGET_PCI0 ,
ETH_TARGET_PCI1
}ETH_TARGET;
typedef struct _eth_rx_desc
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short buf_size ; /* Buffer size */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int next_desc_ptr; /* Next descriptor pointer */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} ETH_RX_DESC;
typedef struct _eth_tx_desc
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short l4i_chk ; /* CPU provided TCP Checksum */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int next_desc_ptr; /* Next descriptor pointer */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} ETH_TX_DESC;
/* Unified struct for Rx and Tx operations. The user is not required to */
/* be familier with neither Tx nor Rx descriptors. */
typedef struct _pkt_info
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} PKT_INFO;
typedef struct _eth_win_param
{
ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
ETH_TARGET target; /* System targets. See ETH_TARGET enum */
unsigned short attributes; /* BAR attributes. See above macros. */
unsigned int base_addr; /* Window base address in unsigned int form */
unsigned int high_addr; /* Window high address in unsigned int form */
unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
bool enable; /* Enable/disable access to the window. */
unsigned short access_ctrl; /* Access ctrl register. see above macros */
} ETH_WIN_PARAM;
/* Ethernet port specific infomation */
typedef struct _eth_port_ctrl
{
ETH_PORT port_num; /* User Ethernet port number */
int port_phy_addr; /* User phy address of Ethrnet port */
unsigned char port_mac_addr[6]; /* User defined port MAC address. */
unsigned int port_config; /* User port configuration value */
unsigned int port_config_extend; /* User port config extend value */
unsigned int port_sdma_config; /* User port SDMA config value */
unsigned int port_serial_control; /* User port serial control value */
unsigned int port_tx_queue_command; /* Port active Tx queues summary */
unsigned int port_rx_queue_command; /* Port active Rx queues summary */
/* User function to cast virtual address to CPU bus address */
unsigned int (*port_virt_to_phys)(unsigned int addr);
/* User scratch pad for user specific data structures */
void *port_private;
bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
/* Tx/Rx rings managment indexes fields. For driver use */
/* Next available Rx resource */
volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
/* Returning Rx resource */
volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
/* Next available Tx resource */
volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
/* Returning Tx resource */
volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
/* An extra Tx index to support transmit of multiple buffers per packet */
volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
/* Tx/Rx rings size and base variables fields. For driver use */
volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
} ETH_PORT_INFO;
/* ethernet.h API list */
/* Port operation control routines */
static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
static void eth_port_reset(ETH_PORT eth_port_num);
static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
/* Port MAC address routines */
static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
unsigned char *p_addr,
ETH_QUEUE queue);
#if 0 /* FIXME */
static void eth_port_mc_addr (ETH_PORT eth_port_num,
unsigned char *p_addr,
ETH_QUEUE queue,
int option);
#endif
/* PHY and MIB routines */
static bool ethernet_phy_reset(ETH_PORT eth_port_num);
static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
unsigned int phy_reg,
unsigned int value);
static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
unsigned int phy_reg,
unsigned int* value);
static void eth_clear_mib_counters(ETH_PORT eth_port_num);
/* Port data flow control routines */
static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
PKT_INFO *p_pkt_info);
static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
int tx_desc_num,
int tx_buff_size,
unsigned int tx_desc_base_addr,
unsigned int tx_buff_base_addr);
static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
int rx_desc_num,
int rx_buff_size,
unsigned int rx_desc_base_addr,
unsigned int rx_buff_base_addr);
#endif /* MV64360_ETH_ */

1108
board/Marvell/db64360/mv_regs.h
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board/Marvell/db64360/pci.c
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* PCI.c - PCI functions */
#include <common.h>
#include <pci.h>
#include "../include/pci.h"
#undef DEBUG
#undef IDE_SET_NATIVE_MODE
static unsigned int local_buses[] = { 0, 0 };
static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
};
#ifdef DEBUG
static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
static void gt_pci_bus_mode_display (PCI_HOST host)
{
unsigned int mode;
mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
switch (mode) {
case 0:
printf ("PCI %d bus mode: Conventional PCI\n", host);
break;
case 1:
printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
break;
case 2:
printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
break;
case 3:
printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
break;
default:
printf ("Unknown BUS %d\n", mode);
}
}
#endif
static const unsigned int pci_p2p_configuration_reg[] = {
PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
};
static const unsigned int pci_configuration_address[] = {
PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
};
static const unsigned int pci_configuration_data[] = {
PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
};
static const unsigned int pci_error_cause_reg[] = {
PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
};
static const unsigned int pci_arbiter_control[] = {
PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
};
static const unsigned int pci_address_space_en[] = {
PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
};
static const unsigned int pci_snoop_control_base_0_low[] = {
PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
};
static const unsigned int pci_snoop_control_top_0[] = {
PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
};
static const unsigned int pci_access_control_base_0_low[] = {
PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
};
static const unsigned int pci_access_control_top_0[] = {
PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
};
static const unsigned int pci_scs_bank_size[2][4] = {
{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
};
static const unsigned int pci_p2p_configuration[] = {
PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
};
/********************************************************************
* pciWriteConfigReg - Write to a PCI configuration register
* - Make sure the GT is configured as a master before writing
* to another device on the PCI.
* - The function takes care of Big/Little endian conversion.
*
*
* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
* (or any other PCI device spec)
* pciDevNum: The device number needs to be addressed.
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|00|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
unsigned int pciDevNum, unsigned int data)
{
volatile unsigned int DataForAddrReg;
unsigned int functionNum;
unsigned int busNum = 0;
unsigned int addr;
if (pciDevNum > 32) /* illegal device Number */
return;
if (pciDevNum == SELF) { /* configure our configuration space. */
pciDevNum =
(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
0x1f;
busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
0xff0000;
}
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xfc;
DataForAddrReg =
(regOffset | pciDevNum | functionNum | busNum) | BIT31;
GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
GT_REG_READ (pci_configuration_address[host], &addr);
if (addr != DataForAddrReg)
return;
GT_REG_WRITE (pci_configuration_data[host], data);
}
/********************************************************************
* pciReadConfigReg - Read from a PCI0 configuration register
* - Make sure the GT is configured as a master before reading
* from another device on the PCI.
* - The function takes care of Big/Little endian conversion.
* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
* spec)
* pciDevNum: The device number needs to be addressed.
* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
* cause register to make sure the data is valid
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|00|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
unsigned int pciDevNum)
{
volatile unsigned int DataForAddrReg;
unsigned int data;
unsigned int functionNum;
unsigned int busNum = 0;
if (pciDevNum > 32) /* illegal device Number */
return 0xffffffff;
if (pciDevNum == SELF) { /* configure our configuration space. */
pciDevNum =
(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
0x1f;
busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
0xff0000;
}
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xfc;
DataForAddrReg =
(regOffset | pciDevNum | functionNum | busNum) | BIT31;
GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
GT_REG_READ (pci_configuration_address[host], &data);
if (data != DataForAddrReg)
return 0xffffffff;
GT_REG_READ (pci_configuration_data[host], &data);
return data;
}
/********************************************************************
* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
* the agent is placed on another Bus. For more
* information read P2P in the PCI spec.
*
* Inputs: unsigned int regOffset - The register offset as it apears in the
* GT spec (or any other PCI device spec).
* unsigned int pciDevNum - The device number needs to be addressed.
* unsigned int busNum - On which bus does the Target agent connect
* to.
* unsigned int data - data to be written.
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|01|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
* The configuration Address is configure as type-I (bits[1:0] = '01') due to
* PCI spec referring to P2P.
*
*********************************************************************/
void pciOverBridgeWriteConfigReg (PCI_HOST host,
unsigned int regOffset,
unsigned int pciDevNum,
unsigned int busNum, unsigned int data)
{
unsigned int DataForReg;
unsigned int functionNum;
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xff;
busNum = busNum << 16;
if (pciDevNum == SELF) { /* This board */
DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
} else {
DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
BIT31 | BIT0;
}
GT_REG_WRITE (pci_configuration_address[host], DataForReg);
GT_REG_WRITE (pci_configuration_data[host], data);
}
/********************************************************************
* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
* the agent target locate on another PCI bus.
* - Make sure the GT is configured as a master
* before reading from another device on the PCI.
* - The function takes care of Big/Little endian
* conversion.
* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
* spec). (configuration register offset.)
* pciDevNum: The device number needs to be addressed.
* busNum: the Bus number where the agent is place.
* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
* cause register to make sure the data is valid
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|01|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
unsigned int regOffset,
unsigned int pciDevNum,
unsigned int busNum)
{
unsigned int DataForReg;
unsigned int data;
unsigned int functionNum;
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xff;
busNum = busNum << 16;
if (pciDevNum == SELF) { /* This board */
DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
} else { /* agent on another bus */
DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
BIT0 | BIT31;
}
GT_REG_WRITE (pci_configuration_address[host], DataForReg);
GT_REG_READ (pci_configuration_data[host], &data);
return data;
}
/********************************************************************
* pciGetRegOffset - Gets the register offset for this region config.
*
* INPUT: Bus, Region - The bus and region we ask for its base address.
* OUTPUT: N/A
* RETURNS: PCI register base address
*********************************************************************/
static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
{
switch (host) {
case PCI_HOST0:
switch (region) {
case PCI_IO:
return PCI_0I_O_LOW_DECODE_ADDRESS;
case PCI_REGION0:
return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
case PCI_REGION1:
return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
case PCI_REGION2:
return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
case PCI_REGION3:
return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
}
case PCI_HOST1:
switch (region) {
case PCI_IO:
return PCI_1I_O_LOW_DECODE_ADDRESS;
case PCI_REGION0:
return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
case PCI_REGION1:
return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
case PCI_REGION2:
return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
case PCI_REGION3:
return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
}
}
return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
}
static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
{
switch (host) {
case PCI_HOST0:
switch (region) {
case PCI_IO:
return PCI_0I_O_ADDRESS_REMAP;
case PCI_REGION0:
return PCI_0MEMORY0_ADDRESS_REMAP;
case PCI_REGION1:
return PCI_0MEMORY1_ADDRESS_REMAP;
case PCI_REGION2:
return PCI_0MEMORY2_ADDRESS_REMAP;
case PCI_REGION3:
return PCI_0MEMORY3_ADDRESS_REMAP;
}
case PCI_HOST1:
switch (region) {
case PCI_IO:
return PCI_1I_O_ADDRESS_REMAP;
case PCI_REGION0:
return PCI_1MEMORY0_ADDRESS_REMAP;
case PCI_REGION1:
return PCI_1MEMORY1_ADDRESS_REMAP;
case PCI_REGION2:
return PCI_1MEMORY2_ADDRESS_REMAP;
case PCI_REGION3:
return PCI_1MEMORY3_ADDRESS_REMAP;
}
}
return PCI_0MEMORY0_ADDRESS_REMAP;
}
/********************************************************************
* pciGetBaseAddress - Gets the base address of a PCI.
* - If the PCI size is 0 then this base address has no meaning!!!
*
*
* INPUT: Bus, Region - The bus and region we ask for its base address.
* OUTPUT: N/A
* RETURNS: PCI base address.
*********************************************************************/
unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
{
unsigned int regBase;
unsigned int regEnd;
unsigned int regOffset = pciGetRegOffset (host, region);
GT_REG_READ (regOffset, &regBase);
GT_REG_READ (regOffset + 8, &regEnd);
if (regEnd <= regBase)
return 0xffffffff; /* ERROR !!! */
regBase = regBase << 16;
return regBase;
}
bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
unsigned int bankBase, unsigned int bankLength)
{
unsigned int low = 0xfff;
unsigned int high = 0x0;
unsigned int regOffset = pciGetRegOffset (host, region);
unsigned int remapOffset = pciGetRemapOffset (host, region);
if (bankLength != 0) {
low = (bankBase >> 16) & 0xffff;
high = ((bankBase + bankLength) >> 16) - 1;
}
GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
GT_REG_WRITE (regOffset + 8, high);
if (bankLength != 0) { /* must do AFTER writing maps */
GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
dont support upper 32
in this driver */
}
return true;
}
unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
{
unsigned int low;
unsigned int regOffset = pciGetRegOffset (host, region);
GT_REG_READ (regOffset, &low);
return (low & 0xffff) << 16;
}
unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
{
unsigned int low, high;
unsigned int regOffset = pciGetRegOffset (host, region);
GT_REG_READ (regOffset, &low);
GT_REG_READ (regOffset + 8, &high);
return ((high & 0xffff) + 1) << 16;
}
/* ronen - 7/Dec/03*/
/********************************************************************
* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
* Inputs: one of the PCI BAR
*********************************************************************/
void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
{
RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
}
void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
{
SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
}
/********************************************************************
* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
*
* Inputs: base and size of PCI SCS
*********************************************************************/
void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
unsigned int pciDramBase, unsigned int pciDramSize)
{
/*ronen different function for 3rd bank. */
unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
pciDramBase = pciDramBase & 0xfffff000;
pciDramBase = pciDramBase | (pciReadConfigReg (host,
PCI_SCS_0_BASE_ADDRESS
+ offset,
SELF) & 0x00000fff);
pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
pciDramBase);
if (pciDramSize == 0)
pciDramSize++;
GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
gtPciEnableInternalBAR (host, bank);
}
/********************************************************************
* pciSetRegionFeatures - This function modifys one of the 8 regions with
* feature bits given as an input.
* - Be advised to check the spec before modifying them.
* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
* unsigned int features - See file: pci.h there are defintion for those
* region features.
* unsigned int baseAddress - The region base Address.
* unsigned int topAddress - The region top Address.
* Returns: false if one of the parameters is erroneous true otherwise.
*********************************************************************/
bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
unsigned int features, unsigned int baseAddress,
unsigned int regionLength)
{
unsigned int accessLow;
unsigned int accessHigh;
unsigned int accessTop = baseAddress + regionLength;
if (regionLength == 0) { /* close the region. */
pciDisableAccessRegion (host, region);
return true;
}
/* base Address is store is bits [11:0] */
accessLow = (baseAddress & 0xfff00000) >> 20;
/* All the features are update according to the defines in pci.h (to be on
the safe side we disable bits: [11:0] */
accessLow = accessLow | (features & 0xfffff000);
/* write to the Low Access Region register */
GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
accessLow);
accessHigh = (accessTop & 0xfff00000) >> 20;
/* write to the High Access Region register */
GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
accessHigh - 1);
return true;
}
/********************************************************************
* pciDisableAccessRegion - Disable The given Region by writing MAX size
* to its low Address and MIN size to its high Address.
*
* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
* Returns: N/A.
*********************************************************************/
void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
{
/* writing back the registers default values. */
GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
0x01001fff);
GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
}
/********************************************************************
* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
*
* Inputs: N/A
* Returns: true.
*********************************************************************/
bool pciArbiterEnable (PCI_HOST host)
{
unsigned int regData;
GT_REG_READ (pci_arbiter_control[host], &regData);
GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
return true;
}
/********************************************************************
* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
*
* Inputs: N/A
* Returns: true
*********************************************************************/
bool pciArbiterDisable (PCI_HOST host)
{
unsigned int regData;
GT_REG_READ (pci_arbiter_control[host], &regData);
GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
return true;
}
/********************************************************************
* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
*
* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
* Returns: true
*********************************************************************/
bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
PCI_AGENT_PRIO externalAgent0,
PCI_AGENT_PRIO externalAgent1,
PCI_AGENT_PRIO externalAgent2,
PCI_AGENT_PRIO externalAgent3,
PCI_AGENT_PRIO externalAgent4,
PCI_AGENT_PRIO externalAgent5)
{
unsigned int regData;
unsigned int writeData;
GT_REG_READ (pci_arbiter_control[host], &regData);
writeData = (internalAgent << 7) + (externalAgent0 << 8) +
(externalAgent1 << 9) + (externalAgent2 << 10) +
(externalAgent3 << 11) + (externalAgent4 << 12) +
(externalAgent5 << 13);
regData = (regData & 0xffffc07f) | writeData;
GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
return true;
}
/********************************************************************
* pciParkingDisable - Park on last option disable, with this function you can
* disable the park on last mechanism for each agent.
* disabling this option for all agents results parking
* on the internal master.
*
* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
* Returns: true
*********************************************************************/
bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
PCI_AGENT_PARK externalAgent0,
PCI_AGENT_PARK externalAgent1,
PCI_AGENT_PARK externalAgent2,
PCI_AGENT_PARK externalAgent3,
PCI_AGENT_PARK externalAgent4,
PCI_AGENT_PARK externalAgent5)
{
unsigned int regData;
unsigned int writeData;
GT_REG_READ (pci_arbiter_control[host], &regData);
writeData = (internalAgent << 14) + (externalAgent0 << 15) +
(externalAgent1 << 16) + (externalAgent2 << 17) +
(externalAgent3 << 18) + (externalAgent4 << 19) +
(externalAgent5 << 20);
regData = (regData & ~(0x7f << 14)) | writeData;
GT_REG_WRITE (pci_arbiter_control[host], regData);
return true;
}
/********************************************************************
* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
* respond to grant assertion within a window specified in
* the input value: 'brokenValue'.
*
* Inputs: unsigned char brokenValue - A value which limits the Master to hold the
* grant without asserting frame.
* Returns: Error for illegal broken value otherwise true.
*********************************************************************/
bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
{
unsigned int data;
unsigned int regData;
if (brokenValue > 0xf)
return false; /* brokenValue must be 4 bit */
data = brokenValue << 3;
GT_REG_READ (pci_arbiter_control[host], &regData);
regData = (regData & 0xffffff87) | data;
GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
return true;
}
/********************************************************************
* pciDisableBrokenAgentDetection - This function disable the Broken agent
* Detection mechanism.
* NOTE: This operation may cause a dead lock on the
* pci0 arbitration.
*
* Inputs: N/A
* Returns: true.
*********************************************************************/
bool pciDisableBrokenAgentDetection (PCI_HOST host)
{
unsigned int regData;
GT_REG_READ (pci_arbiter_control[host], &regData);
regData = regData & 0xfffffffd;
GT_REG_WRITE (pci_arbiter_control[host], regData);
return true;
}
/********************************************************************
* pciP2PConfig - This function set the PCI_n P2P configurate.
* For more information on the P2P read PCI spec.
*
* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
* Boundry.
* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
* Boundry.
* unsigned int busNum - The CPI bus number to which the PCI interface
* is connected.
* unsigned int devNum - The PCI interface's device number.
*
* Returns: true.
*********************************************************************/
bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
unsigned int SecondBusHigh,
unsigned int busNum, unsigned int devNum)
{
unsigned int regData;
regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
GT_REG_WRITE (pci_p2p_configuration[host], regData);
return true;
}
/********************************************************************
* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
* supports Cache Coherency in the PCI_n interface.
* Inputs: region - One of the four regions.
* snoopType - There is four optional Types:
* 1. No Snoop.
* 2. Snoop to WT region.
* 3. Snoop to WB region.
* 4. Snoop & Invalidate to WB region.
* baseAddress - Base Address of this region.
* regionLength - Region length.
* Returns: false if one of the parameters is wrong otherwise return true.
*********************************************************************/
bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
PCI_SNOOP_TYPE snoopType,
unsigned int baseAddress,
unsigned int regionLength)
{
unsigned int snoopXbaseAddress;
unsigned int snoopXtopAddress;
unsigned int data;
unsigned int snoopHigh = baseAddress + regionLength;
if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
return false;
snoopXbaseAddress =
pci_snoop_control_base_0_low[host] + 0x10 * region;
snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
if (regionLength == 0) { /* closing the region */
GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
GT_REG_WRITE (snoopXtopAddress, 0);
return true;
}
baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
data = (baseAddress >> 20) | snoopType << 12;
GT_REG_WRITE (snoopXbaseAddress, data);
snoopHigh = (snoopHigh & 0xfff00000) >> 20;
GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
return true;
}
static int gt_read_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 * value)
{
int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
PCI_DEV (dev));
} else {
*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
cfg_addr, offset,
PCI_DEV (dev), bus);
}
return 0;
}
static int gt_write_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
PCI_DEV (dev), value);
} else {
pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
offset, PCI_DEV (dev), bus,
value);
}
return 0;
}
static void gt_setup_ide (struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *entry)
{
static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
u32 bar_response, bar_value;
int bar;
for (bar = 0; bar < 6; bar++) {
/*ronen different function for 3rd bank. */
unsigned int offset =
(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
0x0);
pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
&bar_response);
pciauto_region_allocate (bar_response &
PCI_BASE_ADDRESS_SPACE_IO ? hose->
pci_io : hose->pci_mem, ide_bar[bar],
&bar_value);
pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
bar_value);
}
}
/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
/* and is curently not called *. */
#if 0
static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
{
unsigned char pin, irq;
pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
if (pin == 1) { /* only allow INT A */
irq = pci_irq_swizzle[(PCI_HOST) hose->
cfg_addr][PCI_DEV (dev)];
if (irq)
pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
}
}
#endif
struct pci_config_table gt_config_table[] = {
{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
{}
};
struct pci_controller pci0_hose = {
/* fixup_irq: gt_fixup_irq, */
config_table:gt_config_table,
};
struct pci_controller pci1_hose = {
/* fixup_irq: gt_fixup_irq, */
config_table:gt_config_table,
};
void pci_init_board (void)
{
unsigned int command;
#ifdef DEBUG
gt_pci_bus_mode_display (PCI_HOST0);
#endif
pci0_hose.first_busno = 0;
pci0_hose.last_busno = 0xff;
local_buses[0] = pci0_hose.first_busno;
/* PCI memory space */
pci_set_region (pci0_hose.regions + 0,
CONFIG_SYS_PCI0_0_MEM_SPACE,
CONFIG_SYS_PCI0_0_MEM_SPACE,
CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci0_hose.regions + 1,
CONFIG_SYS_PCI0_IO_SPACE_PCI,
CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci0_hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
gt_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
gt_write_config_dword);
pci0_hose.region_count = 2;
pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
pci_register_hose (&pci0_hose);
pciArbiterEnable (PCI_HOST0);
pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MASTER;
pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MEMORY;
pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
#ifdef DEBUG
gt_pci_bus_mode_display (PCI_HOST1);
#endif
pci1_hose.first_busno = pci0_hose.last_busno + 1;
pci1_hose.last_busno = 0xff;
pci1_hose.current_busno = pci1_hose.first_busno;
local_buses[1] = pci1_hose.first_busno;
/* PCI memory space */
pci_set_region (pci1_hose.regions + 0,
CONFIG_SYS_PCI1_0_MEM_SPACE,
CONFIG_SYS_PCI1_0_MEM_SPACE,
CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci1_hose.regions + 1,
CONFIG_SYS_PCI1_IO_SPACE_PCI,
CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci1_hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
gt_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
gt_write_config_dword);
pci1_hose.region_count = 2;
pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
pci_register_hose (&pci1_hose);
pciArbiterEnable (PCI_HOST1);
pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MASTER;
pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MEMORY;
pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
}

1945
board/Marvell/db64360/sdram_init.c
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36
board/Marvell/db64460/64460.h
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@ -1,36 +0,0 @@
/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* main board support/init for the Galileo Eval board DB64460.
*/
#ifndef __64460_H__
#define __64460_H__
/* CPU Configuration bits */
#define CPU_CONF_ADDR_MISS_EN (1 << 8)
#define CPU_CONF_SINGLE_CPU (1 << 11)
#define CPU_CONF_ENDIANESS (1 << 12)
#define CPU_CONF_PIPELINE (1 << 13)
#define CPU_CONF_STOP_RETRY (1 << 17)
#define CPU_CONF_MULTI_DECODE (1 << 18)
#define CPU_CONF_DP_VALID (1 << 19)
#define CPU_CONF_PERR_PROP (1 << 22)
#define CPU_CONF_AACK_DELAY_2 (1 << 25)
#define CPU_CONF_AP_VALID (1 << 26)
#define CPU_CONF_REMAP_WR_DIS (1 << 27)
/* CPU Master Control bits */
#define CPU_MAST_CTL_ARB_EN (1 << 8)
#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
#endif /* __64460_H__ */

12
board/Marvell/db64460/Kconfig
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@ -1,12 +0,0 @@
if TARGET_DB64460
config SYS_BOARD
default "db64460"
config SYS_VENDOR
default "Marvell"
config SYS_CONFIG_NAME
default "DB64460"
endif

6
board/Marvell/db64460/MAINTAINERS
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@ -1,6 +0,0 @@
DB64460 BOARD
#M: -
S: Maintained
F: board/Marvell/db64460/
F: include/configs/DB64460.h
F: configs/DB64460_defconfig

13
board/Marvell/db64460/Makefile
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@ -1,13 +0,0 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += db64460.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
sdram_init.o ../common/intel_flash.o ../common/misc.o

105
board/Marvell/db64460/README
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@ -1,105 +0,0 @@
This file contains status information for the port of the U-Boot to the Marvell Development Board DB64460.
Author: Ronen Shitrit <rshitrit@il.marvell.com>
Supported CPU Types :
+++++++++++++++++++++
IBM750Gx Rev 1.0
MPC7457 Rev 1.1
Supported CPU Cache Library:
++++++++++++++++++++++++++++
L1 and L2 only.
CPU Control:
++++++++++++
Marvell optimized CPU control settings:
Big Endian
Enable CPU pipeline
Data and address parity checking
AACK# assert after 2 cycles
U-Boot I/O Interface Support:
+++++++++++++++++++++++++++++
- Serial Interface (UART)
This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module.
- Network Interface
This LSP supports the following network devices:
o MV64360 Gigabit Ethernet Controller device
o Intel 82559 PCI NIC device
- PCI Interface
This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units:
o Local PCI configuration header control.
o External PCI configuration header control (for other agents on the bus).
o PCI configuration application. Scans and configures the PCI agents on the bus.
o PCI Internal Arbiter activation and configuration.
Memory Interface Support:
+++++++++++++++++++++++++
- DDR
o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs).
o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma.
- Devices
o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM.
o JFFS2
JFFS2 is a crash/power down safe file system for disk-less embedded devices.
This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it.
Unsupported Features:
+++++++++++++++++++++
Messaging unit - No support for MV64360 Messaging unit.
Watchdog Timer - No support for MV64360 Watchdog unit.
L3 cache - No support for L3 cache on MPC7455
Dual PCU - No support for Dual CPU
PCI-X was never tested
IDMA driver - No support for MV64360 IDMA unit.
XOR Engine - No support for MV64460 XOR Engine
BSP Special Considerations:
+++++++++++++++++++++++++++
- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots.
- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical.
Test Cases:
###########
UART:
+++++
Check that the UART baud rate is configured to 57600 and 115200, and check:
Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom.
Load S-Record file over the UART using Windows HyperTerminal.
Network:
++++++++
Use TFTP application to load a debugged executable and execute it.
Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC.
Memory:
+++++++
Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters:
o 128MB DIMM consist of 16 x 64Mbit devices
o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz.
o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz.
o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz.
o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz.
o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz.
o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered
For each chip select device perform data access to verify its accessibility.
Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage.
Load the U-Boot and:
use the ls command to check correct scan of the JFFS2 on the large flash.
Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage.
PCI:
++++
1)Insert different PCI cards:
Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10
on different slots (0-3) of the PCI and check:
o Correct detection of the PCI devices.
o Correct address mapping of the PCI devices.
2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot.
Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal)

922
board/Marvell/db64460/db64460.c
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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com
*/
/*
* db64460.c - main board support/init for the Galileo Eval board.
*/
#include <common.h>
#include <74xx_7xx.h>
#include "../include/memory.h"
#include "../include/pci.h"
#include "../include/mv_gen_reg.h"
#include <net.h>
#include <netdev.h>
#include <linux/compiler.h>
#include "eth.h"
#include "mpsc.h"
#include "i2c.h"
#include "64460.h"
#include "mv_regs.h"
#undef DEBUG
/*#define DEBUG */
#define MAP_PCI
#ifdef DEBUG
#define DP(x) x
#else
#define DP(x)
#endif
/* ------------------------------------------------------------------------- */
/* this is the current GT register space location */
/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
/* Unfortunately, we cant change it while we are in flash, so we initialize it
* to the "final" value. This means that any debug_led calls before
* board_early_init_f wont work right (like in cpu_init_f).
* See also my_remap_gt_regs below. (NTL)
*/
void board_prebootm_init (void);
unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
int display_mem_map (void);
/* ------------------------------------------------------------------------- */
/*
* This is a version of the GT register space remapping function that
* doesn't touch globals (meaning, it's ok to run from flash.)
*
* Unfortunately, this has the side effect that a writable
* INTERNAL_REG_BASE_ADDR is impossible. Oh well.
*/
void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
{
u32 temp;
/* check and see if it's already moved */
/* original ppcboot 1.1.6 source
temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
if ((temp & 0xffff) == new_loc >> 20)
return;
temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
0xffff0000) | (new_loc >> 20);
out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
original ppcboot 1.1.6 source end */
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
if ((temp & 0xffff) == new_loc >> 16)
return;
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
0xffff0000) | (new_loc >> 16);
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
}
#ifdef CONFIG_PCI
static void gt_pci_config (void)
{
unsigned int stat;
unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
* config registers by writing ones to the bus and device.
* We then update the Virtual register with the correct value for the bus and device.
*/
if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
(stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
(stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
/* Enable master */
PCI_MASTER_ENABLE (0, SELF);
PCI_MASTER_ENABLE (1, SELF);
/* Enable PCI0/1 Mem0 and IO 0 disable all others */
GT_REG_READ (BASE_ADDR_ENABLE, &stat);
stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
<<
18);
stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
/* ronen- add write to pci remap registers for 64460.
in 64360 when writing to pci base go and overide remap automaticaly,
in 64460 it doesn't */
GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
/* PCI interface settings */
/* Timeout set to retry forever */
GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
/* ronen - enable only CS0 and Internal reg!! */
GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
/*ronen update the pci internal registers base address.*/
#ifdef MAP_PCI
for (stat = 0; stat <= PCI_HOST1; stat++)
pciWriteConfigReg (stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
SELF, CONFIG_SYS_GT_REGS);
#endif
}
#endif
/* Setup CPU interface paramaters */
static void gt_cpu_config (void)
{
cpu_t cpu = get_cpu_type ();
ulong tmp;
/* cpu configuration register */
tmp = GTREGREAD (CPU_CONFIGURATION);
/* set the SINGLE_CPU bit see MV64460 P.399 */
#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
tmp |= CPU_CONF_SINGLE_CPU;
#endif
tmp &= ~CPU_CONF_AACK_DELAY_2;
tmp |= CPU_CONF_DP_VALID;
tmp |= CPU_CONF_AP_VALID;
tmp |= CPU_CONF_PIPELINE;
GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
/* CPU master control register */
tmp = GTREGREAD (CPU_MASTER_CONTROL);
tmp |= CPU_MAST_CTL_ARB_EN;
if ((cpu == CPU_7400) ||
(cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
tmp |= CPU_MAST_CTL_CLEAN_BLK;
tmp |= CPU_MAST_CTL_FLUSH_BLK;
} else {
/* cleanblock must be cleared for CPUs
* that do not support this command (603e, 750)
* see Res#1 */
tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
}
GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
}
/*
* board_early_init_f.
*
* set up gal. device mappings, etc.
*/
int board_early_init_f (void)
{
uchar sram_boot = 0;
/*
* set up the GT the way the kernel wants it
* the call to move the GT register space will obviously
* fail if it has already been done, but we're going to assume
* that if it's not at the power-on location, it's where we put
* it last time. (huber)
*/
my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
/* No PCI in first release of Port To_do: enable it. */
#ifdef CONFIG_PCI
gt_pci_config ();
#endif
/* mask all external interrupt sources */
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
/* new in MV6446x */
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
/* --------------------- */
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
/* does not exist in MV6446x
GT_REG_WRITE(CPU_INT_0_MASK, 0);
GT_REG_WRITE(CPU_INT_1_MASK, 0);
GT_REG_WRITE(CPU_INT_2_MASK, 0);
GT_REG_WRITE(CPU_INT_3_MASK, 0);
--------------------- */
/* ----- DEVICE BUS SETTINGS ------ */
/*
* EVB
* 0 - SRAM ????
* 1 - RTC ????
* 2 - UART ????
* 3 - Flash checked 32Bit Intel Strata
* boot - BootCS checked 8Bit 29LV040B
*
* Zuma
* 0 - Flash
* boot - BootCS
*/
/*
* the dual 7450 module requires burst access to the boot
* device, so the serial rom copies the boot device to the
* on-board sram on the eval board, and updates the correct
* registers to boot from the sram. (device0)
*/
if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
sram_boot = 1;
if (!sram_boot)
memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
/* configure device timing */
#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */
if (!sram_boot)
GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
#endif
#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */
GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
#endif
#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */
GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
#endif
#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
/* detect if we are booting from the 32 bit flash */
if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
/* 32 bit boot flash */
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
CONFIG_SYS_32BIT_BOOT_PAR);
} else {
/* 8 bit boot flash */
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
}
#else
/* 8 bit boot flash only */
/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
#endif
gt_cpu_config ();
/* MPP setup */
GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
DEBUG_LED0_ON ();
DEBUG_LED1_ON ();
DEBUG_LED2_ON ();
return 0;
}
/* various things to do after relocation */
int misc_init_r ()
{
icache_enable ();
#ifdef CONFIG_SYS_L2
l2cache_enable ();
#endif
#ifdef CONFIG_MPSC
mpsc_sdma_init ();
mpsc_init2 ();
#endif
#if 0
/* disable the dcache and MMU */
dcache_lock ();
#endif
return 0;
}
void after_reloc (ulong dest_addr, gd_t * gd)
{
/* check to see if we booted from the sram. If so, move things
* back to the way they should be. (we're running from main
* memory at this point now */
if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
}
display_mem_map ();
/* now, jump to the main ppcboot board init code */
board_init_r (gd, dest_addr);
/* NOTREACHED */
}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
* right now, assume borad type. (there is just one...after all)
*/
int checkboard (void)
{
int l_type = 0;
printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
return (l_type);
}
/* utility functions */
void debug_led (int led, int mode)
{
volatile int *addr = 0;
__maybe_unused int dummy;
if (mode == 1) {
switch (led) {
case 0:
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x08000);
break;
case 1:
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x0c000);
break;
case 2:
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x10000);
break;
}
} else if (mode == 0) {
switch (led) {
case 0:
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x14000);
break;
case 1:
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x18000);
break;
case 2:
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x1c000);
break;
}
}
dummy = *addr;
}
int display_mem_map (void)
{
int i, j;
unsigned int base, size, width;
/* SDRAM */
printf ("SD (DDR) RAM\n");
for (i = 0; i <= BANK3; i++) {
base = memoryGetBankBaseAddress (i);
size = memoryGetBankSize (i);
if (size != 0) {
printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
i, base, size >> 20);
}
}
/* CPU's PCI windows */
for (i = 0; i <= PCI_HOST1; i++) {
printf ("\nCPU's PCI %d windows\n", i);
base = pciGetSpaceBase (i, PCI_IO);
size = pciGetSpaceSize (i, PCI_IO);
printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
size >> 20);
for (j = 0;
j <=
PCI_REGION0
/*ronen currently only first PCI MEM is used 3 */ ;
j++) {
base = pciGetSpaceBase (i, j);
size = pciGetSpaceSize (i, j);
printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
}
}
/* Devices */
printf ("\nDEVICES\n");
for (i = 0; i <= DEVICE3; i++) {
base = memoryGetDeviceBaseAddress (i);
size = memoryGetDeviceSize (i);
width = memoryGetDeviceWidth (i) * 8;
printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
if (i == 0)
printf ("\t- EXT SRAM (actual - 1M)\n");
else if (i == 1)
printf ("\t- RTC\n");
else if (i == 2)
printf ("\t- UART\n");
else
printf ("\t- LARGE FLASH\n");
}
/* Bootrom */
base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
size = memoryGetDeviceSize (BOOT_DEVICE);
width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n",
base, size >> 20, width);
return (0);
}
/* DRAM check routines copied from gw8260 */
#if defined (CONFIG_SYS_DRAM_TEST)
/*********************************************************************/
/* NAME: move64() - moves a double word (64-bit) */
/* */
/* DESCRIPTION: */
/* this function performs a double word move from the data at */
/* the source pointer to the location at the destination pointer. */
/* */
/* INPUTS: */
/* unsigned long long *src - pointer to data to move */
/* */
/* OUTPUTS: */
/* unsigned long long *dest - pointer to locate to move data */
/* */
/* RETURNS: */
/* None */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* May cloober fr0. */
/* */
/*********************************************************************/
static void move64 (unsigned long long *src, unsigned long long *dest)
{
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
"stfd 0, 0(4)" /* *dest = fpr0 */
: : : "fr0"); /* Clobbers fr0 */
return;
}
#if defined (CONFIG_SYS_DRAM_TEST_DATA)
unsigned long long pattern[] = {
0xaaaaaaaaaaaaaaaaULL,
0xccccccccccccccccULL,
0xf0f0f0f0f0f0f0f0ULL,
0xff00ff00ff00ff00ULL,
0xffff0000ffff0000ULL,
0xffffffff00000000ULL,
0x00000000ffffffffULL,
0x0000ffff0000ffffULL,
0x00ff00ff00ff00ffULL,
0x0f0f0f0f0f0f0f0fULL,
0x3333333333333333ULL,
0x5555555555555555ULL,
};
/*********************************************************************/
/* NAME: mem_test_data() - test data lines for shorts and opens */
/* */
/* DESCRIPTION: */
/* Tests data lines for shorts and opens by forcing adjacent data */
/* to opposite states. Because the data lines could be routed in */
/* an arbitrary manner the must ensure test patterns ensure that */
/* every case is tested. By using the following series of binary */
/* patterns every combination of adjacent bits is test regardless */
/* of routing. */
/* */
/* ...101010101010101010101010 */
/* ...110011001100110011001100 */
/* ...111100001111000011110000 */
/* ...111111110000000011111111 */
/* */
/* Carrying this out, gives us six hex patterns as follows: */
/* */
/* 0xaaaaaaaaaaaaaaaa */
/* 0xcccccccccccccccc */
/* 0xf0f0f0f0f0f0f0f0 */
/* 0xff00ff00ff00ff00 */
/* 0xffff0000ffff0000 */
/* 0xffffffff00000000 */
/* */
/* The number test patterns will always be given by: */
/* */
/* log(base 2)(number data bits) = log2 (64) = 6 */
/* */
/* To test for short and opens to other signals on our boards. we */
/* simply */
/* test with the 1's complemnt of the paterns as well. */
/* */
/* OUTPUTS: */
/* Displays failing test pattern */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* Assumes only one one SDRAM bank */
/* */
/*********************************************************************/
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
for (i = 0; i < num_patterns; i++) {
move64 (&(pattern[i]), pmem);
move64 (pmem, &temp64);
/* hi = (temp64>>32) & 0xffffffff; */
/* lo = temp64 & 0xffffffff; */
/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
hi = (pattern[i] >> 32) & 0xffffffff;
lo = pattern[i] & 0xffffffff;
/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
if (temp64 != pattern[i]) {
printf ("\n Data Test Failed, pattern 0x%08x%08x",
hi, lo);
return 1;
}
}
return 0;
}
#endif /* CONFIG_SYS_DRAM_TEST_DATA */
#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
/*********************************************************************/
/* NAME: mem_test_address() - test address lines */
/* */
/* DESCRIPTION: */
/* This function performs a test to verify that each word im */
/* memory is uniquly addressable. The test sequence is as follows: */
/* */
/* 1) write the address of each word to each word. */
/* 2) verify that each location equals its address */
/* */
/* OUTPUTS: */
/* Displays failing test pattern and address */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int mem_test_address (void)
{
volatile unsigned int *pmem =
(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
unsigned int i;
/* write address to each location */
for (i = 0; i < size; i++) {
pmem[i] = i;
}
/* verify each loaction */
for (i = 0; i < size; i++) {
if (pmem[i] != i) {
printf ("\n Address Test Failed at 0x%x", i);
return 1;
}
}
return 0;
}
#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
#if defined (CONFIG_SYS_DRAM_TEST_WALK)
/*********************************************************************/
/* NAME: mem_march() - memory march */
/* */
/* DESCRIPTION: */
/* Marches up through memory. At each location verifies rmask if */
/* read = 1. At each location write wmask if write = 1. Displays */
/* failing address and pattern. */
/* */
/* INPUTS: */
/* volatile unsigned long long * base - start address of test */
/* unsigned int size - number of dwords(64-bit) to test */
/* unsigned long long rmask - read verify mask */
/* unsigned long long wmask - wrtie verify mask */
/* short read - verifies rmask if read = 1 */
/* short write - writes wmask if write = 1 */
/* */
/* OUTPUTS: */
/* Displays failing test pattern and address */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int mem_march (volatile unsigned long long *base,
unsigned int size,
unsigned long long rmask,
unsigned long long wmask, short read, short write)
{
unsigned int i;
unsigned long long temp = 0;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
if (read != 0) {
/* temp = base[i]; */
move64 ((unsigned long long *) &(base[i]), &temp);
if (rmask != temp) {
hitemp = (temp >> 32) & 0xffffffff;
lotemp = temp & 0xffffffff;
himask = (rmask >> 32) & 0xffffffff;
lomask = rmask & 0xffffffff;
printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
return 1;
}
}
if (write != 0) {
/* base[i] = wmask; */
move64 (&wmask, (unsigned long long *) &(base[i]));
}
}
return 0;
}
#endif /* CONFIG_SYS_DRAM_TEST_WALK */
/*********************************************************************/
/* NAME: mem_test_walk() - a simple walking ones test */
/* */
/* DESCRIPTION: */
/* Performs a walking ones through entire physical memory. The */
/* test uses as series of memory marches, mem_march(), to verify */
/* and write the test patterns to memory. The test sequence is as */
/* follows: */
/* 1) march writing 0000...0001 */
/* 2) march verifying 0000...0001 , writing 0000...0010 */
/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
/* the write mask equals 1000...0000 */
/* 4) march verifying 1000...0000 */
/* The test fails if any of the memory marches return a failure. */
/* */
/* OUTPUTS: */
/* Displays which pass on the memory test is executing */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int mem_test_walk (void)
{
unsigned long long mask;
volatile unsigned long long *pmem =
(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
unsigned int i;
mask = 0x01;
printf ("Initial Pass");
mem_march (pmem, size, 0x0, 0x1, 0, 1);
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
printf (" ");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
for (i = 0; i < 63; i++) {
printf ("Pass %2d", i + 2);
if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
/*printf("mask: 0x%x, pass: %d, ", mask, i); */
return 1;
}
mask = mask << 1;
printf ("\b\b\b\b\b\b\b");
}
printf ("Last Pass");
if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
/* printf("mask: 0x%x", mask); */
return 1;
}
printf ("\b\b\b\b\b\b\b\b\b");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b");
return 0;
}
/*********************************************************************/
/* NAME: testdram() - calls any enabled memory tests */
/* */
/* DESCRIPTION: */
/* Runs memory tests if the environment test variables are set to */
/* 'y'. */
/* */
/* INPUTS: */
/* testdramdata - If set to 'y', data test is run. */
/* testdramaddress - If set to 'y', address test is run. */
/* testdramwalk - If set to 'y', walking ones test is run */
/* */
/* OUTPUTS: */
/* None */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int testdram (void)
{
int rundata, runaddress, runwalk;
rundata = getenv_yesno("testdramdata") == 1;
runaddress = getenv_yesno("testdramaddress") == 1;
runwalk = getenv_yesno("testdramwalk") == 1;
/* rundata = 1; */
/* runaddress = 0; */
/* runwalk = 0; */
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
}
#ifdef CONFIG_SYS_DRAM_TEST_DATA
if (rundata == 1) {
printf ("Test DATA ... ");
if (mem_test_data () == 1) {
printf ("failed \n");
return 1;
} else
printf ("ok \n");
}
#endif
#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
if (runaddress == 1) {
printf ("Test ADDRESS ... ");
if (mem_test_address () == 1) {
printf ("failed \n");
return 1;
} else
printf ("ok \n");
}
#endif
#ifdef CONFIG_SYS_DRAM_TEST_WALK
if (runwalk == 1) {
printf ("Test WALKING ONEs ... ");
if (mem_test_walk () == 1) {
printf ("failed \n");
return 1;
} else
printf ("ok \n");
}
#endif
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf ("passed\n");
}
return 0;
}
#endif /* CONFIG_SYS_DRAM_TEST */
/* ronen - the below functions are used by the bootm function */
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
/* - we turn off the RX gig dmas - to prevent the dma from overunning */
/* the kernel data areas. */
/* - we diable and invalidate the icache and dcache. */
void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
{
u32 temp;
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
if ((temp & 0xffff) == new_loc >> 16)
return;
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
0xffff0000) | (new_loc >> 16);
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
new_loc |
(INTERNAL_SPACE_DECODE)))))
!= temp);
}
void board_prebootm_init ()
{
/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
/* Stop GigE Rx DMA engines */
GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
/* Relocate MV64460 internal regs */
my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
icache_disable ();
dcache_disable ();
}
int board_eth_init(bd_t *bis)
{
int ret;
ret = pci_eth_init(bis);
if (!ret)
ret = mv6446x_eth_initialize(bis);
return ret;
}

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board/Marvell/db64460/eth.h
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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* eth.h - header file for the polled mode GT ethernet driver
*/
#ifndef __EVB64460_ETH_H__
#define __EVB64460_ETH_H__
#include <asm/types.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <common.h>
int db64460_eth0_poll(void);
int db64460_eth0_transmit(unsigned int s, volatile char *p);
void db64460_eth0_disable(void);
bool network_start(bd_t *bis);
int mv6446x_eth_initialize(bd_t *);
#endif /* __EVB64460_ETH_H__ */

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board/Marvell/db64460/mpsc.c
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board/Marvell/db64460/mpsc.h
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/*
* (C) Copyright 2001
* John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*************************************************************************
* changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
*
************************************************************************/
/*
* mpsc.h - header file for MPSC in uart mode (console driver)
*/
#ifndef __MPSC_H__
#define __MPSC_H__
/* include actual Galileo defines */
#include "../include/mv_gen_reg.h"
/* driver related defines */
int mpsc_init(int baud);
void mpsc_sdma_init(void);
void mpsc_init2(void);
int galbrg_set_baudrate(int channel, int rate);
int mpsc_putchar_early(char ch);
char mpsc_getchar_debug(void);
int mpsc_test_char_debug(void);
int mpsc_test_char_sdma(void);
extern int (*mpsc_putchar)(char ch);
extern char (*mpsc_getchar)(void);
extern int (*mpsc_test_char)(void);
#define CHANNEL CONFIG_MPSC_PORT
#define TX_DESC 5
#define RX_DESC 20
#define DESC_FIRST 0x00010000
#define DESC_LAST 0x00020000
#define DESC_OWNER_BIT 0x80000000
#define TX_DEMAND 0x00800000
#define TX_STOP 0x00010000
#define RX_ENABLE 0x00000080
#define SDMA_RX_ABORT (1 << 15)
#define SDMA_TX_ABORT (1 << 31)
#define MPSC_TX_ABORT (1 << 7)
#define MPSC_RX_ABORT (1 << 23)
#define MPSC_ENTER_HUNT (1 << 31)
/* MPSC defines */
#define GALMPSC_CONNECT 0x1
#define GALMPSC_DISCONNECT 0x0
#define GALMPSC_UART 0x1
#define GALMPSC_STOP_BITS_1 0x0
#define GALMPSC_STOP_BITS_2 0x1
#define GALMPSC_CHAR_LENGTH_8 0x3
#define GALMPSC_CHAR_LENGTH_7 0x2
#define GALMPSC_PARITY_ODD 0x0
#define GALMPSC_PARITY_EVEN 0x2
#define GALMPSC_PARITY_MARK 0x3
#define GALMPSC_PARITY_SPACE 0x1
#define GALMPSC_PARITY_NONE -1
#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
#define GALMPSC_REG_GAP 0x1000
#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
#define GALSDMA_COMMAND_FIRST (1 << 16)
#define GALSDMA_COMMAND_LAST (1 << 17)
#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
#define GALSDMA_COMMAND_AUTO (1 << 30)
#define GALSDMA_COMMAND_OWNER (1 << 31)
#define GALSDMA_RX 0
#define GALSDMA_TX 1
/* CHANNEL2 should be CHANNEL1, according to documentation,
* but to work with the current GTREGS file...
*/
#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
#define GALSDMA_REG_DIFF 0x2000
/* WRONG in gt64260R.h */
#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
#define GALMPSC_0_INT_CAUSE 0xb804
#define GALMPSC_0_INT_MASK 0xb884
#define GALSDMA_MODE_UART 0
#define GALSDMA_MODE_BISYNC 1
#define GALSDMA_MODE_HDLC 2
#define GALSDMA_MODE_TRANSPARENT 3
#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
#define GALBRG_REG_GAP 0x0008
#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
#endif /* __MPSC_H__ */

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board/Marvell/db64460/mv_eth.c
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board/Marvell/db64460/mv_eth.h
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/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
*
* based on - Driver for MV64460X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* mv_eth.h - header file for the polled mode GT ethernet driver
*/
#ifndef __DB64460_ETH_H__
#define __DB64460_ETH_H__
#include <asm/types.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <common.h>
#include <net.h>
#include "mv_regs.h"
#include <asm/errno.h>
/*************************************************************************
**************************************************************************
**************************************************************************
* The first part is the high level driver of the gigE ethernet ports. *
**************************************************************************
**************************************************************************
*************************************************************************/
/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
#ifndef MAX_SKB_FRAGS
#define MAX_SKB_FRAGS 0
#endif
/* Port attributes */
/*#define MAX_RX_QUEUE_NUM 8*/
/*#define MAX_TX_QUEUE_NUM 8*/
#define MAX_RX_QUEUE_NUM 1
#define MAX_TX_QUEUE_NUM 1
/* Use one TX queue and one RX queue */
#define MV64460_TX_QUEUE_NUM 1
#define MV64460_RX_QUEUE_NUM 1
/*
* Number of RX / TX descriptors on RX / TX rings.
* Note that allocating RX descriptors is done by allocating the RX
* ring AND a preallocated RX buffers (skb's) for each descriptor.
* The TX descriptors only allocates the TX descriptors ring,
* with no pre allocated TX buffers (skb's are allocated by higher layers.
*/
/* Default TX ring size is 10 descriptors */
#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
#else
#define MV64460_TX_QUEUE_SIZE 4
#endif
/* Default RX ring size is 4 descriptors */
#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE
#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
#else
#define MV64460_RX_QUEUE_SIZE 4
#endif
#ifdef CONFIG_RX_BUFFER_SIZE
#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
#else
#define MV64460_RX_BUFFER_SIZE 1600
#endif
#ifdef CONFIG_TX_BUFFER_SIZE
#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
#else
#define MV64460_TX_BUFFER_SIZE 1600
#endif
/*
* Network device statistics. Akin to the 2.0 ether stats but
* with byte counters.
*/
struct net_device_stats
{
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_errors; /* bad packets received */
unsigned long tx_errors; /* packet transmit problems */
unsigned long rx_dropped; /* no space in linux buffers */
unsigned long tx_dropped; /* no space available in linux */
unsigned long multicast; /* multicast packets received */
unsigned long collisions;
/* detailed rx_errors: */
unsigned long rx_length_errors;
unsigned long rx_over_errors; /* receiver ring buff overflow */
unsigned long rx_crc_errors; /* recved pkt with crc error */
unsigned long rx_frame_errors; /* recv'd frame alignment error */
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
unsigned long rx_missed_errors; /* receiver missed packet */
/* detailed tx_errors */
unsigned long tx_aborted_errors;
unsigned long tx_carrier_errors;
unsigned long tx_fifo_errors;
unsigned long tx_heartbeat_errors;
unsigned long tx_window_errors;
/* for cslip etc */
unsigned long rx_compressed;
unsigned long tx_compressed;
};
/* Private data structure used for ethernet device */
struct mv64460_eth_priv {
unsigned int port_num;
struct net_device_stats *stats;
/* to buffer area aligned */
char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
/* Size of Tx Ring per queue */
unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
/* Size of Rx Ring per queue */
unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
/* Magic Number for Ethernet running */
unsigned int eth_running;
};
int mv64460_eth_init (struct eth_device *dev);
int mv64460_eth_stop (struct eth_device *dev);
int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length);
int mv64460_eth_open (struct eth_device *dev);
/*************************************************************************
**************************************************************************
**************************************************************************
* The second part is the low level driver of the gigE ethernet ports. *
**************************************************************************
**************************************************************************
*************************************************************************/
/********************************************************************************
* Header File for : MV-643xx network interface header
*
* DESCRIPTION:
* This header file contains macros typedefs and function declaration for
* the Marvell Gig Bit Ethernet Controller.
*
* DEPENDENCIES:
* None.
*
*******************************************************************************/
#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
#ifdef CONFIG_MV64460_SRAM_CACHEABLE
/* In case SRAM is cacheable but not cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) \
{ \
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
}
#else
/* In case SRAM is cache coherent or non-cacheable */
#define D_CACHE_FLUSH_LINE(addr, offset) ;
#endif
#else
#ifdef CONFIG_NOT_COHERENT_CACHE
/* In case of descriptors on DDR but not cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) \
{ \
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
}
#else
/* In case of descriptors on DDR and cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) ;
#endif /* CONFIG_NOT_COHERENT_CACHE */
#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
#define CPU_PIPE_FLUSH \
{ \
__asm__ __volatile__ ("eieio"); \
}
/* defines */
/* Default port configuration value */
#define PORT_CONFIG_VALUE \
ETH_UNICAST_NORMAL_MODE | \
ETH_DEFAULT_RX_QUEUE_0 | \
ETH_DEFAULT_RX_ARP_QUEUE_0 | \
ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
ETH_RECEIVE_BC_IF_IP | \
ETH_RECEIVE_BC_IF_ARP | \
ETH_CAPTURE_TCP_FRAMES_DIS | \
ETH_CAPTURE_UDP_FRAMES_DIS | \
ETH_DEFAULT_RX_TCP_QUEUE_0 | \
ETH_DEFAULT_RX_UDP_QUEUE_0 | \
ETH_DEFAULT_RX_BPDU_QUEUE_0
/* Default port extend configuration value */
#define PORT_CONFIG_EXTEND_VALUE \
ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
ETH_PARTITION_DISABLE
/* Default sdma control value */
#ifdef CONFIG_NOT_COHERENT_CACHE
#define PORT_SDMA_CONFIG_VALUE \
ETH_RX_BURST_SIZE_16_64BIT | \
GT_ETH_IPG_INT_RX(0) | \
ETH_TX_BURST_SIZE_16_64BIT;
#else
#define PORT_SDMA_CONFIG_VALUE \
ETH_RX_BURST_SIZE_4_64BIT | \
GT_ETH_IPG_INT_RX(0) | \
ETH_TX_BURST_SIZE_4_64BIT;
#endif
#define GT_ETH_IPG_INT_RX(value) \
((value & 0x3fff) << 8)
/* Default port serial control value */
#define PORT_SERIAL_CONTROL_VALUE \
ETH_FORCE_LINK_PASS | \
ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
ETH_ADV_SYMMETRIC_FLOW_CTRL | \
ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
ETH_FORCE_BP_MODE_NO_JAM | \
BIT9 | \
ETH_DO_NOT_FORCE_LINK_FAIL | \
ETH_RETRANSMIT_16_ETTEMPTS | \
ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
ETH_DTE_ADV_0 | \
ETH_DISABLE_AUTO_NEG_BYPASS | \
ETH_AUTO_NEG_NO_CHANGE | \
ETH_MAX_RX_PACKET_1552BYTE | \
ETH_CLR_EXT_LOOPBACK | \
ETH_SET_FULL_DUPLEX_MODE | \
ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
#define RX_BUFFER_MAX_SIZE 0xFFFF
#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
#define RX_BUFFER_MIN_SIZE 0x8
#define TX_BUFFER_MIN_SIZE 0x8
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
/* MAC accepet/reject macros */
#define ACCEPT_MAC_ADDR 0
#define REJECT_MAC_ADDR 1
/* Size of a Tx/Rx descriptor used in chain list data structure */
#define RX_DESC_ALIGNED_SIZE 0x20
#define TX_DESC_ALIGNED_SIZE 0x20
/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
#define TX_BUF_OFFSET_IN_DESC 0x18
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Gap define */
#define ETH_BAR_GAP 0x8
#define ETH_SIZE_REG_GAP 0x8
#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
#define ETH_PORT_ACCESS_CTRL_GAP 0x4
/* Gigabit Ethernet Unit Global Registers */
/* MIB Counters register definitions */
#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
#define ETH_MIB_FRAMES_64_OCTETS 0x20
#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
#define ETH_MIB_GOOD_FRAMES_SENT 0x40
#define ETH_MIB_EXCESSIVE_COLLISION 0x44
#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
#define ETH_MIB_FC_SENT 0x54
#define ETH_MIB_GOOD_FC_RECEIVED 0x58
#define ETH_MIB_BAD_FC_RECEIVED 0x5c
#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
#define ETH_MIB_OVERSIZE_RECEIVED 0x68
#define ETH_MIB_JABBER_RECEIVED 0x6c
#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
#define ETH_MIB_BAD_CRC_EVENT 0x74
#define ETH_MIB_COLLISION 0x78
#define ETH_MIB_LATE_COLLISION 0x7c
/* Port serial status reg (PSR) */
#define ETH_INTERFACE_GMII_MII 0
#define ETH_INTERFACE_PCM BIT0
#define ETH_LINK_IS_DOWN 0
#define ETH_LINK_IS_UP BIT1
#define ETH_PORT_AT_HALF_DUPLEX 0
#define ETH_PORT_AT_FULL_DUPLEX BIT2
#define ETH_RX_FLOW_CTRL_DISABLED 0
#define ETH_RX_FLOW_CTRL_ENBALED BIT3
#define ETH_GMII_SPEED_100_10 0
#define ETH_GMII_SPEED_1000 BIT4
#define ETH_MII_SPEED_10 0
#define ETH_MII_SPEED_100 BIT5
#define ETH_NO_TX 0
#define ETH_TX_IN_PROGRESS BIT7
#define ETH_BYPASS_NO_ACTIVE 0
#define ETH_BYPASS_ACTIVE BIT8
#define ETH_PORT_NOT_AT_PARTITION_STATE 0
#define ETH_PORT_AT_PARTITION_STATE BIT9
#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
#define ETH_PORT_TX_FIFO_EMPTY BIT10
/* These macros describes the Port configuration reg (Px_cR) bits */
#define ETH_UNICAST_NORMAL_MODE 0
#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
#define ETH_DEFAULT_RX_QUEUE_0 0
#define ETH_DEFAULT_RX_QUEUE_1 BIT1
#define ETH_DEFAULT_RX_QUEUE_2 BIT2
#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
#define ETH_DEFAULT_RX_QUEUE_4 BIT3
#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
#define ETH_RECEIVE_BC_IF_IP 0
#define ETH_REJECT_BC_IF_IP BIT8
#define ETH_RECEIVE_BC_IF_ARP 0
#define ETH_REJECT_BC_IF_ARP BIT9
#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
#define ETH_CAPTURE_TCP_FRAMES_DIS 0
#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
#define ETH_CAPTURE_UDP_FRAMES_DIS 0
#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
#define ETH_CLASSIFY_EN BIT0
#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
#define ETH_PARTITION_DISABLE 0
#define ETH_PARTITION_ENABLE BIT2
/* Tx/Rx queue command reg (RQCR/TQCR)*/
#define ETH_QUEUE_0_ENABLE BIT0
#define ETH_QUEUE_1_ENABLE BIT1
#define ETH_QUEUE_2_ENABLE BIT2
#define ETH_QUEUE_3_ENABLE BIT3
#define ETH_QUEUE_4_ENABLE BIT4
#define ETH_QUEUE_5_ENABLE BIT5
#define ETH_QUEUE_6_ENABLE BIT6
#define ETH_QUEUE_7_ENABLE BIT7
#define ETH_QUEUE_0_DISABLE BIT8
#define ETH_QUEUE_1_DISABLE BIT9
#define ETH_QUEUE_2_DISABLE BIT10
#define ETH_QUEUE_3_DISABLE BIT11
#define ETH_QUEUE_4_DISABLE BIT12
#define ETH_QUEUE_5_DISABLE BIT13
#define ETH_QUEUE_6_DISABLE BIT14
#define ETH_QUEUE_7_DISABLE BIT15
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
#define ETH_RIFB BIT0
#define ETH_RX_BURST_SIZE_1_64BIT 0
#define ETH_RX_BURST_SIZE_2_64BIT BIT1
#define ETH_RX_BURST_SIZE_4_64BIT BIT2
#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
#define ETH_RX_BURST_SIZE_16_64BIT BIT3
#define ETH_BLM_RX_NO_SWAP BIT4
#define ETH_BLM_RX_BYTE_SWAP 0
#define ETH_BLM_TX_NO_SWAP BIT5
#define ETH_BLM_TX_BYTE_SWAP 0
#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
#define ETH_DESCRIPTORS_NO_SWAP 0
#define ETH_TX_BURST_SIZE_1_64BIT 0
#define ETH_TX_BURST_SIZE_2_64BIT BIT22
#define ETH_TX_BURST_SIZE_4_64BIT BIT23
#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
#define ETH_TX_BURST_SIZE_16_64BIT BIT24
/* These macros describes the Port serial control reg (PSCR) bits */
#define ETH_SERIAL_PORT_DISABLE 0
#define ETH_SERIAL_PORT_ENABLE BIT0
#define ETH_FORCE_LINK_PASS BIT1
#define ETH_DO_NOT_FORCE_LINK_PASS 0
#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
#define ETH_ADV_NO_FLOW_CTRL 0
#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
#define ETH_FORCE_BP_MODE_NO_JAM 0
#define ETH_FORCE_BP_MODE_JAM_TX BIT7
#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
#define ETH_FORCE_LINK_FAIL 0
#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
#define ETH_RETRANSMIT_16_ETTEMPTS 0
#define ETH_RETRANSMIT_FOREVER BIT11
#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
#define ETH_DTE_ADV_0 0
#define ETH_DTE_ADV_1 BIT14
#define ETH_DISABLE_AUTO_NEG_BYPASS 0
#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
#define ETH_AUTO_NEG_NO_CHANGE 0
#define ETH_RESTART_AUTO_NEG BIT16
#define ETH_MAX_RX_PACKET_1518BYTE 0
#define ETH_MAX_RX_PACKET_1522BYTE BIT17
#define ETH_MAX_RX_PACKET_1552BYTE BIT18
#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
#define ETH_MAX_RX_PACKET_9192BYTE BIT19
#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
#define ETH_SET_EXT_LOOPBACK BIT20
#define ETH_CLR_EXT_LOOPBACK 0
#define ETH_SET_FULL_DUPLEX_MODE BIT21
#define ETH_SET_HALF_DUPLEX_MODE 0
#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
#define ETH_SET_GMII_SPEED_TO_10_100 0
#define ETH_SET_GMII_SPEED_TO_1000 BIT23
#define ETH_SET_MII_SPEED_TO_10 0
#define ETH_SET_MII_SPEED_TO_100 BIT24
/* SMI reg */
#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
#define ETH_ERROR_SUMMARY (BIT0)
/* Tx & Rx descriptors command */
#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
/* Tx descriptors status */
#define ETH_LC_ERROR (0 )
#define ETH_UR_ERROR (BIT1 )
#define ETH_RL_ERROR (BIT2 )
#define ETH_LLC_SNAP_FORMAT (BIT9 )
/* Rx descriptors status */
#define ETH_CRC_ERROR (0 )
#define ETH_OVERRUN_ERROR (BIT1 )
#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
#define ETH_VLAN_TAGGED (BIT19)
#define ETH_BPDU_FRAME (BIT20)
#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
#define ETH_OTHER_FRAME_TYPE (BIT22)
#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
#define ETH_FRAME_HEADER_OK (BIT25)
#define ETH_RX_LAST_DESC (BIT26)
#define ETH_RX_FIRST_DESC (BIT27)
#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
#define ETH_RX_ENABLE_INTERRUPT (BIT29)
#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
/* Rx descriptors byte count */
#define ETH_FRAME_FRAGMENTED (BIT2)
/* Tx descriptors command */
#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
#define ETH_FRAME_SET_TO_VLAN (BIT15)
#define ETH_TCP_FRAME (0 )
#define ETH_UDP_FRAME (BIT16)
#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
#define ETH_ZERO_PADDING (BIT19)
#define ETH_TX_LAST_DESC (BIT20)
#define ETH_TX_FIRST_DESC (BIT21)
#define ETH_GEN_CRC (BIT22)
#define ETH_TX_ENABLE_INTERRUPT (BIT23)
#define ETH_AUTO_MODE (BIT30)
/* Address decode parameters */
/* Ethernet Base Address Register bits */
#define EBAR_TARGET_DRAM 0x00000000
#define EBAR_TARGET_DEVICE 0x00000001
#define EBAR_TARGET_CBS 0x00000002
#define EBAR_TARGET_PCI0 0x00000003
#define EBAR_TARGET_PCI1 0x00000004
#define EBAR_TARGET_CUNIT 0x00000005
#define EBAR_TARGET_AUNIT 0x00000006
#define EBAR_TARGET_GUNIT 0x00000007
/* Window attributes */
#define EBAR_ATTR_DRAM_CS0 0x00000E00
#define EBAR_ATTR_DRAM_CS1 0x00000D00
#define EBAR_ATTR_DRAM_CS2 0x00000B00
#define EBAR_ATTR_DRAM_CS3 0x00000700
/* DRAM Target interface */
#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
/* Device Bus Target interface */
#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
/* PCI Target interface */
#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
/* CPU 60x bus or internal SRAM interface */
#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
#define EBAR_ATTR_CBS_SRAM 0x00000000
#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
/* Window access control */
#define EWIN_ACCESS_NOT_ALLOWED 0
#define EWIN_ACCESS_READ_ONLY BIT0
#define EWIN_ACCESS_FULL (BIT1 | BIT0)
#define EWIN0_ACCESS_MASK 0x0003
#define EWIN1_ACCESS_MASK 0x000C
#define EWIN2_ACCESS_MASK 0x0030
#define EWIN3_ACCESS_MASK 0x00C0
/* typedefs */
typedef enum _eth_port
{
ETH_0 = 0,
ETH_1 = 1,
ETH_2 = 2
}ETH_PORT;
typedef enum _eth_func_ret_status
{
ETH_OK, /* Returned as expected. */
ETH_ERROR, /* Fundamental error. */
ETH_RETRY, /* Could not process request. Try later. */
ETH_END_OF_JOB, /* Ring has nothing to process. */
ETH_QUEUE_FULL, /* Ring resource error. */
ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
}ETH_FUNC_RET_STATUS;
typedef enum _eth_queue
{
ETH_Q0 = 0,
ETH_Q1 = 1,
ETH_Q2 = 2,
ETH_Q3 = 3,
ETH_Q4 = 4,
ETH_Q5 = 5,
ETH_Q6 = 6,
ETH_Q7 = 7
} ETH_QUEUE;
typedef enum _addr_win
{
ETH_WIN0,
ETH_WIN1,
ETH_WIN2,
ETH_WIN3,
ETH_WIN4,
ETH_WIN5
} ETH_ADDR_WIN;
typedef enum _eth_target
{
ETH_TARGET_DRAM ,
ETH_TARGET_DEVICE,
ETH_TARGET_CBS ,
ETH_TARGET_PCI0 ,
ETH_TARGET_PCI1
}ETH_TARGET;
typedef struct _eth_rx_desc
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short buf_size ; /* Buffer size */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int next_desc_ptr; /* Next descriptor pointer */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} ETH_RX_DESC;
typedef struct _eth_tx_desc
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short l4i_chk ; /* CPU provided TCP Checksum */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int next_desc_ptr; /* Next descriptor pointer */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} ETH_TX_DESC;
/* Unified struct for Rx and Tx operations. The user is not required to */
/* be familier with neither Tx nor Rx descriptors. */
typedef struct _pkt_info
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} PKT_INFO;
typedef struct _eth_win_param
{
ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
ETH_TARGET target; /* System targets. See ETH_TARGET enum */
unsigned short attributes; /* BAR attributes. See above macros. */
unsigned int base_addr; /* Window base address in unsigned int form */
unsigned int high_addr; /* Window high address in unsigned int form */
unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
bool enable; /* Enable/disable access to the window. */
unsigned short access_ctrl; /* Access ctrl register. see above macros */
} ETH_WIN_PARAM;
/* Ethernet port specific infomation */
typedef struct _eth_port_ctrl
{
ETH_PORT port_num; /* User Ethernet port number */
int port_phy_addr; /* User phy address of Ethrnet port */
unsigned char port_mac_addr[6]; /* User defined port MAC address. */
unsigned int port_config; /* User port configuration value */
unsigned int port_config_extend; /* User port config extend value */
unsigned int port_sdma_config; /* User port SDMA config value */
unsigned int port_serial_control; /* User port serial control value */
unsigned int port_tx_queue_command; /* Port active Tx queues summary */
unsigned int port_rx_queue_command; /* Port active Rx queues summary */
/* User function to cast virtual address to CPU bus address */
unsigned int (*port_virt_to_phys)(unsigned int addr);
/* User scratch pad for user specific data structures */
void *port_private;
bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
/* Tx/Rx rings managment indexes fields. For driver use */
/* Next available Rx resource */
volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
/* Returning Rx resource */
volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
/* Next available Tx resource */
volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
/* Returning Tx resource */
volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
/* An extra Tx index to support transmit of multiple buffers per packet */
volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
/* Tx/Rx rings size and base variables fields. For driver use */
volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
} ETH_PORT_INFO;
/* ethernet.h API list */
/* Port operation control routines */
static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
static void eth_port_reset(ETH_PORT eth_port_num);
static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
/* Port MAC address routines */
static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
unsigned char *p_addr,
ETH_QUEUE queue);
#if 0 /* FIXME */
static void eth_port_mc_addr (ETH_PORT eth_port_num,
unsigned char *p_addr,
ETH_QUEUE queue,
int option);
#endif
/* PHY and MIB routines */
static bool ethernet_phy_reset(ETH_PORT eth_port_num);
static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
unsigned int phy_reg,
unsigned int value);
static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
unsigned int phy_reg,
unsigned int* value);
static void eth_clear_mib_counters(ETH_PORT eth_port_num);
/* Port data flow control routines */
static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
PKT_INFO *p_pkt_info);
static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
int tx_desc_num,
int tx_buff_size,
unsigned int tx_desc_base_addr,
unsigned int tx_buff_base_addr);
static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
int rx_desc_num,
int rx_buff_size,
unsigned int rx_desc_base_addr,
unsigned int rx_buff_base_addr);
#endif /* MV64460_ETH_ */

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board/Marvell/db64460/mv_regs.h
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board/Marvell/db64460/pci.c
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* PCI.c - PCI functions */
#include <common.h>
#include <pci.h>
#include "../include/pci.h"
#undef DEBUG
#undef IDE_SET_NATIVE_MODE
static unsigned int local_buses[] = { 0, 0 };
static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
};
#ifdef DEBUG
static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
static void gt_pci_bus_mode_display (PCI_HOST host)
{
unsigned int mode;
mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
switch (mode) {
case 0:
printf ("PCI %d bus mode: Conventional PCI\n", host);
break;
case 1:
printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
break;
case 2:
printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
break;
case 3:
printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
break;
default:
printf ("Unknown BUS %d\n", mode);
}
}
#endif
static const unsigned int pci_p2p_configuration_reg[] = {
PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
};
static const unsigned int pci_configuration_address[] = {
PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
};
static const unsigned int pci_configuration_data[] = {
PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
};
static const unsigned int pci_error_cause_reg[] = {
PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
};
static const unsigned int pci_arbiter_control[] = {
PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
};
static const unsigned int pci_address_space_en[] = {
PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
};
static const unsigned int pci_snoop_control_base_0_low[] = {
PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
};
static const unsigned int pci_snoop_control_top_0[] = {
PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
};
static const unsigned int pci_access_control_base_0_low[] = {
PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
};
static const unsigned int pci_access_control_top_0[] = {
PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
};
static const unsigned int pci_scs_bank_size[2][4] = {
{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
};
static const unsigned int pci_p2p_configuration[] = {
PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
};
/********************************************************************
* pciWriteConfigReg - Write to a PCI configuration register
* - Make sure the GT is configured as a master before writing
* to another device on the PCI.
* - The function takes care of Big/Little endian conversion.
*
*
* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
* (or any other PCI device spec)
* pciDevNum: The device number needs to be addressed.
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|00|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
unsigned int pciDevNum, unsigned int data)
{
volatile unsigned int DataForAddrReg;
unsigned int functionNum;
unsigned int busNum = 0;
unsigned int addr;
if (pciDevNum > 32) /* illegal device Number */
return;
if (pciDevNum == SELF) { /* configure our configuration space. */
pciDevNum =
(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
0x1f;
busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
0xff0000;
}
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xfc;
DataForAddrReg =
(regOffset | pciDevNum | functionNum | busNum) | BIT31;
GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
GT_REG_READ (pci_configuration_address[host], &addr);
if (addr != DataForAddrReg)
return;
GT_REG_WRITE (pci_configuration_data[host], data);
}
/********************************************************************
* pciReadConfigReg - Read from a PCI0 configuration register
* - Make sure the GT is configured as a master before reading
* from another device on the PCI.
* - The function takes care of Big/Little endian conversion.
* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
* spec)
* pciDevNum: The device number needs to be addressed.
* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
* cause register to make sure the data is valid
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|00|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
unsigned int pciDevNum)
{
volatile unsigned int DataForAddrReg;
unsigned int data;
unsigned int functionNum;
unsigned int busNum = 0;
if (pciDevNum > 32) /* illegal device Number */
return 0xffffffff;
if (pciDevNum == SELF) { /* configure our configuration space. */
pciDevNum =
(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
0x1f;
busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
0xff0000;
}
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xfc;
DataForAddrReg =
(regOffset | pciDevNum | functionNum | busNum) | BIT31;
GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
GT_REG_READ (pci_configuration_address[host], &data);
if (data != DataForAddrReg)
return 0xffffffff;
GT_REG_READ (pci_configuration_data[host], &data);
return data;
}
/********************************************************************
* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
* the agent is placed on another Bus. For more
* information read P2P in the PCI spec.
*
* Inputs: unsigned int regOffset - The register offset as it apears in the
* GT spec (or any other PCI device spec).
* unsigned int pciDevNum - The device number needs to be addressed.
* unsigned int busNum - On which bus does the Target agent connect
* to.
* unsigned int data - data to be written.
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|01|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
* The configuration Address is configure as type-I (bits[1:0] = '01') due to
* PCI spec referring to P2P.
*
*********************************************************************/
void pciOverBridgeWriteConfigReg (PCI_HOST host,
unsigned int regOffset,
unsigned int pciDevNum,
unsigned int busNum, unsigned int data)
{
unsigned int DataForReg;
unsigned int functionNum;
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xff;
busNum = busNum << 16;
if (pciDevNum == SELF) { /* This board */
DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
} else {
DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
BIT31 | BIT0;
}
GT_REG_WRITE (pci_configuration_address[host], DataForReg);
GT_REG_WRITE (pci_configuration_data[host], data);
}
/********************************************************************
* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
* the agent target locate on another PCI bus.
* - Make sure the GT is configured as a master
* before reading from another device on the PCI.
* - The function takes care of Big/Little endian
* conversion.
* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
* spec). (configuration register offset.)
* pciDevNum: The device number needs to be addressed.
* busNum: the Bus number where the agent is place.
* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
* cause register to make sure the data is valid
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|01|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
unsigned int regOffset,
unsigned int pciDevNum,
unsigned int busNum)
{
unsigned int DataForReg;
unsigned int data;
unsigned int functionNum;
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xff;
busNum = busNum << 16;
if (pciDevNum == SELF) { /* This board */
DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
} else { /* agent on another bus */
DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
BIT0 | BIT31;
}
GT_REG_WRITE (pci_configuration_address[host], DataForReg);
GT_REG_READ (pci_configuration_data[host], &data);
return data;
}
/********************************************************************
* pciGetRegOffset - Gets the register offset for this region config.
*
* INPUT: Bus, Region - The bus and region we ask for its base address.
* OUTPUT: N/A
* RETURNS: PCI register base address
*********************************************************************/
static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
{
switch (host) {
case PCI_HOST0:
switch (region) {
case PCI_IO:
return PCI_0I_O_LOW_DECODE_ADDRESS;
case PCI_REGION0:
return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
case PCI_REGION1:
return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
case PCI_REGION2:
return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
case PCI_REGION3:
return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
}
case PCI_HOST1:
switch (region) {
case PCI_IO:
return PCI_1I_O_LOW_DECODE_ADDRESS;
case PCI_REGION0:
return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
case PCI_REGION1:
return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
case PCI_REGION2:
return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
case PCI_REGION3:
return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
}
}
return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
}
static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
{
switch (host) {
case PCI_HOST0:
switch (region) {
case PCI_IO:
return PCI_0I_O_ADDRESS_REMAP;
case PCI_REGION0:
return PCI_0MEMORY0_ADDRESS_REMAP;
case PCI_REGION1:
return PCI_0MEMORY1_ADDRESS_REMAP;
case PCI_REGION2:
return PCI_0MEMORY2_ADDRESS_REMAP;
case PCI_REGION3:
return PCI_0MEMORY3_ADDRESS_REMAP;
}
case PCI_HOST1:
switch (region) {
case PCI_IO:
return PCI_1I_O_ADDRESS_REMAP;
case PCI_REGION0:
return PCI_1MEMORY0_ADDRESS_REMAP;
case PCI_REGION1:
return PCI_1MEMORY1_ADDRESS_REMAP;
case PCI_REGION2:
return PCI_1MEMORY2_ADDRESS_REMAP;
case PCI_REGION3:
return PCI_1MEMORY3_ADDRESS_REMAP;
}
}
return PCI_0MEMORY0_ADDRESS_REMAP;
}
/********************************************************************
* pciGetBaseAddress - Gets the base address of a PCI.
* - If the PCI size is 0 then this base address has no meaning!!!
*
*
* INPUT: Bus, Region - The bus and region we ask for its base address.
* OUTPUT: N/A
* RETURNS: PCI base address.
*********************************************************************/
unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
{
unsigned int regBase;
unsigned int regEnd;
unsigned int regOffset = pciGetRegOffset (host, region);
GT_REG_READ (regOffset, &regBase);
GT_REG_READ (regOffset + 8, &regEnd);
if (regEnd <= regBase)
return 0xffffffff; /* ERROR !!! */
regBase = regBase << 16;
return regBase;
}
bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
unsigned int bankBase, unsigned int bankLength)
{
unsigned int low = 0xfff;
unsigned int high = 0x0;
unsigned int regOffset = pciGetRegOffset (host, region);
unsigned int remapOffset = pciGetRemapOffset (host, region);
if (bankLength != 0) {
low = (bankBase >> 16) & 0xffff;
high = ((bankBase + bankLength) >> 16) - 1;
}
GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
GT_REG_WRITE (regOffset + 8, high);
if (bankLength != 0) { /* must do AFTER writing maps */
GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
dont support upper 32
in this driver */
}
return true;
}
unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
{
unsigned int low;
unsigned int regOffset = pciGetRegOffset (host, region);
GT_REG_READ (regOffset, &low);
return (low & 0xffff) << 16;
}
unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
{
unsigned int low, high;
unsigned int regOffset = pciGetRegOffset (host, region);
GT_REG_READ (regOffset, &low);
GT_REG_READ (regOffset + 8, &high);
return ((high & 0xffff) + 1) << 16;
}
/* ronen - 7/Dec/03*/
/********************************************************************
* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
* Inputs: one of the PCI BAR
*********************************************************************/
void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
{
RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
}
void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
{
SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
}
/********************************************************************
* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
*
* Inputs: base and size of PCI SCS
*********************************************************************/
void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
unsigned int pciDramBase, unsigned int pciDramSize)
{
/*ronen different function for 3rd bank. */
unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
pciDramBase = pciDramBase & 0xfffff000;
pciDramBase = pciDramBase | (pciReadConfigReg (host,
PCI_SCS_0_BASE_ADDRESS
+ offset,
SELF) & 0x00000fff);
pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
pciDramBase);
if (pciDramSize == 0)
pciDramSize++;
GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
gtPciEnableInternalBAR (host, bank);
}
/********************************************************************
* pciSetRegionFeatures - This function modifys one of the 8 regions with
* feature bits given as an input.
* - Be advised to check the spec before modifying them.
* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
* unsigned int features - See file: pci.h there are defintion for those
* region features.
* unsigned int baseAddress - The region base Address.
* unsigned int topAddress - The region top Address.
* Returns: false if one of the parameters is erroneous true otherwise.
*********************************************************************/
bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
unsigned int features, unsigned int baseAddress,
unsigned int regionLength)
{
unsigned int accessLow;
unsigned int accessHigh;
unsigned int accessTop = baseAddress + regionLength;
if (regionLength == 0) { /* close the region. */
pciDisableAccessRegion (host, region);
return true;
}
/* base Address is store is bits [11:0] */
accessLow = (baseAddress & 0xfff00000) >> 20;
/* All the features are update according to the defines in pci.h (to be on
the safe side we disable bits: [11:0] */
accessLow = accessLow | (features & 0xfffff000);
/* write to the Low Access Region register */
GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
accessLow);
accessHigh = (accessTop & 0xfff00000) >> 20;
/* write to the High Access Region register */
GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
accessHigh - 1);
return true;
}
/********************************************************************
* pciDisableAccessRegion - Disable The given Region by writing MAX size
* to its low Address and MIN size to its high Address.
*
* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
* Returns: N/A.
*********************************************************************/
void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
{
/* writing back the registers default values. */
GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
0x01001fff);
GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
}
/********************************************************************
* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
*
* Inputs: N/A
* Returns: true.
*********************************************************************/
bool pciArbiterEnable (PCI_HOST host)
{
unsigned int regData;
GT_REG_READ (pci_arbiter_control[host], &regData);
GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
return true;
}
/********************************************************************
* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
*
* Inputs: N/A
* Returns: true
*********************************************************************/
bool pciArbiterDisable (PCI_HOST host)
{
unsigned int regData;
GT_REG_READ (pci_arbiter_control[host], &regData);
GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
return true;
}
/********************************************************************
* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
*
* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
* Returns: true
*********************************************************************/
bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
PCI_AGENT_PRIO externalAgent0,
PCI_AGENT_PRIO externalAgent1,
PCI_AGENT_PRIO externalAgent2,
PCI_AGENT_PRIO externalAgent3,
PCI_AGENT_PRIO externalAgent4,
PCI_AGENT_PRIO externalAgent5)
{
unsigned int regData;
unsigned int writeData;
GT_REG_READ (pci_arbiter_control[host], &regData);
writeData = (internalAgent << 7) + (externalAgent0 << 8) +
(externalAgent1 << 9) + (externalAgent2 << 10) +
(externalAgent3 << 11) + (externalAgent4 << 12) +
(externalAgent5 << 13);
regData = (regData & 0xffffc07f) | writeData;
GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
return true;
}
/********************************************************************
* pciParkingDisable - Park on last option disable, with this function you can
* disable the park on last mechanism for each agent.
* disabling this option for all agents results parking
* on the internal master.
*
* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
* Returns: true
*********************************************************************/
bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
PCI_AGENT_PARK externalAgent0,
PCI_AGENT_PARK externalAgent1,
PCI_AGENT_PARK externalAgent2,
PCI_AGENT_PARK externalAgent3,
PCI_AGENT_PARK externalAgent4,
PCI_AGENT_PARK externalAgent5)
{
unsigned int regData;
unsigned int writeData;
GT_REG_READ (pci_arbiter_control[host], &regData);
writeData = (internalAgent << 14) + (externalAgent0 << 15) +
(externalAgent1 << 16) + (externalAgent2 << 17) +
(externalAgent3 << 18) + (externalAgent4 << 19) +
(externalAgent5 << 20);
regData = (regData & ~(0x7f << 14)) | writeData;
GT_REG_WRITE (pci_arbiter_control[host], regData);
return true;
}
/********************************************************************
* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
* respond to grant assertion within a window specified in
* the input value: 'brokenValue'.
*
* Inputs: unsigned char brokenValue - A value which limits the Master to hold the
* grant without asserting frame.
* Returns: Error for illegal broken value otherwise true.
*********************************************************************/
bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
{
unsigned int data;
unsigned int regData;
if (brokenValue > 0xf)
return false; /* brokenValue must be 4 bit */
data = brokenValue << 3;
GT_REG_READ (pci_arbiter_control[host], &regData);
regData = (regData & 0xffffff87) | data;
GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
return true;
}
/********************************************************************
* pciDisableBrokenAgentDetection - This function disable the Broken agent
* Detection mechanism.
* NOTE: This operation may cause a dead lock on the
* pci0 arbitration.
*
* Inputs: N/A
* Returns: true.
*********************************************************************/
bool pciDisableBrokenAgentDetection (PCI_HOST host)
{
unsigned int regData;
GT_REG_READ (pci_arbiter_control[host], &regData);
regData = regData & 0xfffffffd;
GT_REG_WRITE (pci_arbiter_control[host], regData);
return true;
}
/********************************************************************
* pciP2PConfig - This function set the PCI_n P2P configurate.
* For more information on the P2P read PCI spec.
*
* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
* Boundry.
* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
* Boundry.
* unsigned int busNum - The CPI bus number to which the PCI interface
* is connected.
* unsigned int devNum - The PCI interface's device number.
*
* Returns: true.
*********************************************************************/
bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
unsigned int SecondBusHigh,
unsigned int busNum, unsigned int devNum)
{
unsigned int regData;
regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
GT_REG_WRITE (pci_p2p_configuration[host], regData);
return true;
}
/********************************************************************
* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
* supports Cache Coherency in the PCI_n interface.
* Inputs: region - One of the four regions.
* snoopType - There is four optional Types:
* 1. No Snoop.
* 2. Snoop to WT region.
* 3. Snoop to WB region.
* 4. Snoop & Invalidate to WB region.
* baseAddress - Base Address of this region.
* regionLength - Region length.
* Returns: false if one of the parameters is wrong otherwise return true.
*********************************************************************/
bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
PCI_SNOOP_TYPE snoopType,
unsigned int baseAddress,
unsigned int regionLength)
{
unsigned int snoopXbaseAddress;
unsigned int snoopXtopAddress;
unsigned int data;
unsigned int snoopHigh = baseAddress + regionLength;
if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
return false;
snoopXbaseAddress =
pci_snoop_control_base_0_low[host] + 0x10 * region;
snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
if (regionLength == 0) { /* closing the region */
GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
GT_REG_WRITE (snoopXtopAddress, 0);
return true;
}
baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
data = (baseAddress >> 20) | snoopType << 12;
GT_REG_WRITE (snoopXbaseAddress, data);
snoopHigh = (snoopHigh & 0xfff00000) >> 20;
GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
return true;
}
static int gt_read_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 * value)
{
int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
PCI_DEV (dev));
} else {
*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
cfg_addr, offset,
PCI_DEV (dev), bus);
}
return 0;
}
static int gt_write_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
PCI_DEV (dev), value);
} else {
pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
offset, PCI_DEV (dev), bus,
value);
}
return 0;
}
static void gt_setup_ide (struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *entry)
{
static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
u32 bar_response, bar_value;
int bar;
for (bar = 0; bar < 6; bar++) {
/*ronen different function for 3rd bank. */
unsigned int offset =
(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
0x0);
pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
&bar_response);
pciauto_region_allocate (bar_response &
PCI_BASE_ADDRESS_SPACE_IO ? hose->
pci_io : hose->pci_mem, ide_bar[bar],
&bar_value);
pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
bar_value);
}
}
/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
/* and is curently not called *. */
#if 0
static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
{
unsigned char pin, irq;
pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
if (pin == 1) { /* only allow INT A */
irq = pci_irq_swizzle[(PCI_HOST) hose->
cfg_addr][PCI_DEV (dev)];
if (irq)
pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
}
}
#endif
struct pci_config_table gt_config_table[] = {
{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
{}
};
struct pci_controller pci0_hose = {
/* fixup_irq: gt_fixup_irq, */
config_table:gt_config_table,
};
struct pci_controller pci1_hose = {
/* fixup_irq: gt_fixup_irq, */
config_table:gt_config_table,
};
void pci_init_board (void)
{
unsigned int command;
#ifdef DEBUG
gt_pci_bus_mode_display (PCI_HOST0);
#endif
pci0_hose.first_busno = 0;
pci0_hose.last_busno = 0xff;
local_buses[0] = pci0_hose.first_busno;
/* PCI memory space */
pci_set_region (pci0_hose.regions + 0,
CONFIG_SYS_PCI0_0_MEM_SPACE,
CONFIG_SYS_PCI0_0_MEM_SPACE,
CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci0_hose.regions + 1,
CONFIG_SYS_PCI0_IO_SPACE_PCI,
CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci0_hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
gt_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
gt_write_config_dword);
pci0_hose.region_count = 2;
pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
pci_register_hose (&pci0_hose);
pciArbiterEnable (PCI_HOST0);
pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MASTER;
pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MEMORY;
pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
#ifdef DEBUG
gt_pci_bus_mode_display (PCI_HOST1);
#endif
pci1_hose.first_busno = pci0_hose.last_busno + 1;
pci1_hose.last_busno = 0xff;
pci1_hose.current_busno = pci1_hose.first_busno;
local_buses[1] = pci1_hose.first_busno;
/* PCI memory space */
pci_set_region (pci1_hose.regions + 0,
CONFIG_SYS_PCI1_0_MEM_SPACE,
CONFIG_SYS_PCI1_0_MEM_SPACE,
CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci1_hose.regions + 1,
CONFIG_SYS_PCI1_IO_SPACE_PCI,
CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci1_hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
gt_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
gt_write_config_dword);
pci1_hose.region_count = 2;
pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
pci_register_hose (&pci1_hose);
pciArbiterEnable (PCI_HOST1);
pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MASTER;
pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MEMORY;
pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
}

1950
board/Marvell/db64460/sdram_init.c
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236
board/Marvell/include/core.h
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@ -1,236 +0,0 @@
/* Core.h - Basic core logic functions and definitions */
/* Copyright Galileo Technology. */
/*
DESCRIPTION
This header file contains simple read/write macros for addressing
the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
space). The macros take care of Big/Little endian conversions.
*/
#ifndef __INCcoreh
#define __INCcoreh
#include "mv_gen_reg.h"
extern unsigned int INTERNAL_REG_BASE_ADDR;
/****************************************/
/* GENERAL Definitions */
/****************************************/
#define NO_BIT 0x00000000
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define _1K 0x00000400
#define _2K 0x00000800
#define _4K 0x00001000
#define _8K 0x00002000
#define _16K 0x00004000
#define _32K 0x00008000
#define _64K 0x00010000
#define _128K 0x00020000
#define _256K 0x00040000
#define _512K 0x00080000
#define _1M 0x00100000
#define _2M 0x00200000
#define _3M 0x00300000
#define _4M 0x00400000
#define _5M 0x00500000
#define _6M 0x00600000
#define _7M 0x00700000
#define _8M 0x00800000
#define _9M 0x00900000
#define _10M 0x00a00000
#define _11M 0x00b00000
#define _12M 0x00c00000
#define _13M 0x00d00000
#define _14M 0x00e00000
#define _15M 0x00f00000
#define _16M 0x01000000
#define _32M 0x02000000
#define _64M 0x04000000
#define _128M 0x08000000
#define _256M 0x10000000
#define _512M 0x20000000
#define _1G 0x40000000
#define _2G 0x80000000
/* Little to Big endian conversion macros */
#ifdef LE /* Little Endian */
#define SHORT_SWAP(X) (X)
#define WORD_SWAP(X) (X)
#define LONG_SWAP(X) ((l64)(X))
#else /* Big Endian */
#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
#define WORD_SWAP(X) (((X)&0xff)<<24)+ \
(((X)&0xff00)<<8)+ \
(((X)&0xff0000)>>8)+ \
(((X)&0xff000000)>>24)
#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \
(((X)&0xff00ULL)<<40)+ \
(((X)&0xff0000ULL)<<24)+ \
(((X)&0xff000000ULL)<<8)+ \
(((X)&0xff00000000ULL)>>8)+ \
(((X)&0xff0000000000ULL)>>24)+ \
(((X)&0xff000000000000ULL)>>40)+ \
(((X)&0xff00000000000000ULL)>>56))
#endif
#ifndef NULL
#define NULL 0
#endif
/* Those two definitions were defined to be compatible with MIPS */
#define NONE_CACHEABLE 0x00000000
#define CACHEABLE 0x00000000
/* 750 cache line */
#define CACHE_LINE_SIZE 32
#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
/* Read/Write to/from GT`s internal registers */
#define GT_REG_READ(offset, pData) \
*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \
INTERNAL_REG_BASE_ADDR | (offset))) ) ; \
*pData = WORD_SWAP(*pData)
#define GTREGREAD(offset) \
(WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \
INTERNAL_REG_BASE_ADDR | (offset))) ))
#define GT_REG_WRITE(offset, data) \
*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \
WORD_SWAP(data)
/* Write 32/16/8 bit */
#define WRITE_CHAR(address, data) \
*((unsigned char *)(address)) = data
#define WRITE_SHORT(address, data) \
*((unsigned short *)(address)) = data
#define WRITE_WORD(address, data) \
*((unsigned int *)(address)) = data
#define GT_WRITE_CHAR(address, data) WRITE_CHAR(address, data)
/* Write 32/16/8 bit NonCacheable */
/*
#define GT_WRITE_CHAR(address, data) \
(*((unsigned char *)NONE_CACHEABLE(address))) = data
#define GT_WRITE_SHORT(address, data) \
(*((unsigned short *)NONE_CACHEABLE(address))) = data
#define GT_WRITE_WORD(address, data) \
(*((unsigned int *)NONE_CACHEABLE(address))) = data
*/
/*#define GT_WRITE_CHAR(address, data) ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */
/*#define GT_WRITE_SHORT(address, data) ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */
/*#define GT_WRITE_WORD(address, data) ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */
/* Read 32/16/8 bits - returns data in variable. */
#define READ_CHAR(address, pData) \
*pData = *((volatile unsigned char *)(address))
#define READ_SHORT(address, pData) \
*pData = *((volatile unsigned short *)(address))
#define READ_WORD(address, pData) \
*pData = *((volatile unsigned int *)(address))
/* Read 32/16/8 bit - returns data direct. */
#define READCHAR(address) \
*((volatile unsigned char *)((address) | NONE_CACHEABLE))
#define READSHORT(address) \
*((volatile unsigned short *)((address) | NONE_CACHEABLE))
#define READWORD(address) \
*((volatile unsigned int *)((address) | NONE_CACHEABLE))
/* Those two Macros were defined to be compatible with MIPS */
#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff)
#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE)
/* SET_REG_BITS(regOffset,bits) -
gets register offset and bits: a 32bit value. It set to logic '1' in the
internal register the bits which given as an input example:
SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
'1' in register 0x840 while the other bits stays as is. */
#define SET_REG_BITS(regOffset,bits) \
*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \
regOffset) |= (unsigned int)WORD_SWAP(bits)
/* RESET_REG_BITS(regOffset,bits) -
gets register offset and bits: a 32bit value. It set to logic '0' in the
internal register the bits which given as an input example:
RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
'0' in register 0x840 while the other bits stays as is. */
#define RESET_REG_BITS(regOffset,bits) \
*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \
| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
/* gets register offset and bits: a 32bit value. It set to logic '1' in the
internal register the bits which given as an input example:
GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
'1' in register 0x840 while the other bits stays as is. */
/*#define GT_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */
/*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */
#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits)
/* gets register offset and bits: a 32bit value. It set to logic '0' in the
internal register the bits which given as an input example:
GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to
logic '0' in register 0x840 while the other bits stays as is. */
/*#define GT_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */
#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)
#define DEBUG_LED0_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0)
#define DEBUG_LED1_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0)
#define DEBUG_LED2_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0)
#define DEBUG_LED0_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0)
#define DEBUG_LED1_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0)
#define DEBUG_LED2_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0)
#endif /* __INCcoreh */

2296
board/Marvell/include/mv_gen_reg.h
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12
board/eltec/mhpc/Kconfig
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if TARGET_MHPC
config SYS_BOARD
default "mhpc"
config SYS_VENDOR
default "eltec"
config SYS_CONFIG_NAME
default "MHPC"
endif

6
board/eltec/mhpc/MAINTAINERS
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@ -1,6 +0,0 @@
MHPC BOARD
M: Frank Gottschling <fgottschling@eltec.de>
S: Maintained
F: board/eltec/mhpc/
F: include/configs/MHPC.h
F: configs/MHPC_defconfig

8
board/eltec/mhpc/Makefile
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@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = mhpc.o flash.o

414
board/eltec/mhpc/flash.c
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/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc8xx.h>
#include <linux/byteorder/swab.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Protection Flags:
*/
#define FLAG_PROTECT_SET 0x01
#define FLAG_PROTECT_CLEAR 0x02
/* Board support for 1 or 2 flash devices */
#undef FLASH_PORT_WIDTH32
#define FLASH_PORT_WIDTH16
#ifdef FLASH_PORT_WIDTH16
#define FLASH_PORT_WIDTH ushort
#define FLASH_PORT_WIDTHV vu_short
#define SWAP(x) __swab16(x)
#else
#define FLASH_PORT_WIDTH ulong
#define FLASH_PORT_WIDTHV vu_long
#define SWAP(x) __swab32(x)
#endif
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (FPW *addr, flash_info_t *info);
static int write_data (flash_info_t *info, ulong dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size_b0;
int i;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Remap FLASH according to real size */
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
/* Re-do sizing to get full correct info */
size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
&flash_info[0]);
flash_info[0].size = size_b0;
return (size_b0);
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
return;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000);
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL: printf ("INTEL "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F640J5 :
printf ("28F640J5 \n"); break;
default: printf ("Unknown Chip Type=0x%lXh\n",
info->flash_id & FLASH_TYPEMASK); break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (FPW *addr, flash_info_t *info)
{
FPW value;
/* Write auto select command: read Manufacturer ID */
addr[0x5555] = (FPW)0xAA00AA00;
addr[0x2AAA] = (FPW)0x55005500;
addr[0x5555] = (FPW)0x90009000;
value = SWAP(addr[0]);
switch (value) {
case (FPW)INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = (FPW)0xFF00FF00; /* restore read mode */
return (0); /* no or unknown flash */
}
value = SWAP(addr[1]); /* device ID no swap !*/
switch (value) {
case (FPW)INTEL_ID_28F640J5 :
info->flash_id += FLASH_28F640J5 ;
info->sector_count = 64;
info->size = 0x00800000;
break; /* => 8 MB */
default:
info->flash_id = FLASH_UNKNOWN;
break;
}
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
addr[0] = (FPW)0xFF00FF00; /* restore read mode */
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type, start, now, last;
int rc = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
type = (info->flash_id & FLASH_VENDMASK);
if ((type != FLASH_MAN_INTEL)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
start = get_timer (0);
last = start;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
FPWV *addr = (FPWV *)(info->start[sect]);
FPW status;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
*addr = (FPW)0x50005000; /* clear status register */
*addr = (FPW)0x20002000; /* erase setup */
*addr = (FPW)0xD000D000; /* erase confirm */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW)0xB000B000; /* suspend erase */
*addr = (FPW)0xFF00FF00; /* reset to read mode */
rc = 1;
break;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
*addr = (FPW)0xFF00FF00; /* reset to read mode */
printf (" done\n");
}
}
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 4 - Flash not identified
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp;
FPW data;
int i, l, rc, port_width;
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
/* get lower word aligned address */
#ifdef FLASH_PORT_WIDTH16
wp = (addr & ~1);
port_width = 2;
#else
wp = (addr & ~3);
port_width = 4;
#endif
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
for (; i<port_width && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_data(info, wp, data)) != 0) {
return (rc);
}
wp += port_width;
}
/*
* handle word aligned part
*/
while (cnt >= port_width) {
data = 0;
for (i=0; i<port_width; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_data(info, wp, data)) != 0) {
return (rc);
}
wp += port_width;
cnt -= port_width;
if ((wp & 0xfff) == 0)
{
printf("%08lX",wp);
printf("\x1b[8D");
}
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_data(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t *info, ulong dest, FPW data)
{
FPWV *addr = (FPWV *)dest;
ulong status;
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
*addr = (FPW)0x40004000; /* write setup */
*addr = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
start = get_timer (0);
while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW)0xFF00FF00; /* restore read mode */
return (1);
}
}
*addr = (FPW)0xFF00FF00; /* restore read mode */
return (0);
}

465
board/eltec/mhpc/mhpc.c
View File

@ -1,465 +0,0 @@
/*
* (C) Copyright 2001
* ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* Board specific routines for the miniHiPerCam
*
* - initialisation (eeprom)
* - memory controller
* - serial io initialisation
* - ethernet io initialisation
*
* -----------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <cli.h>
#include <linux/ctype.h>
#include <commproc.h>
#include "mpc8xx.h"
#include <video_fb.h>
extern void eeprom_init (void);
extern int eeprom_read (unsigned dev_addr, unsigned offset,
unsigned char *buffer, unsigned cnt);
extern int eeprom_write (unsigned dev_addr, unsigned offset,
unsigned char *buffer, unsigned cnt);
/* globals */
void *video_hw_init (void);
void video_set_lut (unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
);
GraphicDevice gdev;
/* locals */
static void video_circle (char *center, int radius, int color, int pitch);
static void video_test_image (void);
static void video_default_lut (unsigned int clut_type);
/* revision info foer MHPC EEPROM offset 480 */
typedef struct {
char board[12]; /* 000 - Board Revision information */
char sensor; /* 012 - Sensor Type information */
char serial[8]; /* 013 - Board serial number */
char etheraddr[6]; /* 021 - Ethernet node addresse */
char revision[2]; /* 027 - Revision code */
char option[3]; /* 029 - resevered for options */
} revinfo;
/* ------------------------------------------------------------------------- */
static const unsigned int sdram_table[] = {
/* read single beat cycle */
0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
/* read burst cycle */
0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* write single beat cycle */
0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* write burst cycle */
0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* periodic timer expired */
0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* exception */
0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
};
/* ------------------------------------------------------------------------- */
int board_early_init_f (void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport);
/* reset the port A s.a. cpm-routines */
ip->iop_padat = 0x0000;
ip->iop_papar = 0x0000;
ip->iop_padir = 0x0800;
ip->iop_paodr = 0x0000;
/* reset the port B for digital and LCD output */
cp->cp_pbdat = 0x0300;
cp->cp_pbpar = 0x5001;
cp->cp_pbdir = 0x5301;
cp->cp_pbodr = 0x0000;
/* reset the port C configured for SMC1 serial port and aqc. control */
ip->iop_pcdat = 0x0800;
ip->iop_pcpar = 0x0000;
ip->iop_pcdir = 0x0e30;
ip->iop_pcso = 0x0000;
/* Config port D for LCD output */
ip->iop_pdpar = 0x1fff;
ip->iop_pddir = 0x1fff;
return (0);
}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity
*/
int checkboard (void)
{
puts ("Board: ELTEC miniHiperCam\n");
return (0);
}
/* ------------------------------------------------------------------------- */
int misc_init_r (void)
{
revinfo mhpcRevInfo;
char nid[32];
char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
"OMNIVISON OV7110 b&w", NULL
};
char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
0, 0, 0, 0, 10, 11, 12, 13, 14, 15
};
int i;
/* check revision data */
eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32);
if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
printf ("Enter revision number (0-9): %c ",
mhpcRevInfo.revision[0]);
if (0 != cli_readline(NULL)) {
mhpcRevInfo.revision[0] =
(char) toupper (console_buffer[0]);
}
printf ("Enter revision character (A-Z): %c ",
mhpcRevInfo.revision[1]);
if (1 == cli_readline(NULL)) {
mhpcRevInfo.revision[1] =
(char) toupper (console_buffer[0]);
}
printf ("Enter board name (V-XXXX-XXXX): %s ",
(char *) &mhpcRevInfo.board);
if (11 == cli_readline(NULL)) {
for (i = 0; i < 11; i++) {
mhpcRevInfo.board[i] =
(char) toupper (console_buffer[i]);
mhpcRevInfo.board[11] = '\0';
}
}
printf ("Supported sensor types:\n");
i = 0;
do {
printf ("\n \'%d\' : %s\n", i, mhpcSensorTypes[i]);
} while (mhpcSensorTypes[++i] != NULL);
do {
printf ("\nEnter sensor number (0-255): %d ",
(int) mhpcRevInfo.sensor);
if (0 != cli_readline(NULL)) {
mhpcRevInfo.sensor =
(unsigned char)
simple_strtoul (console_buffer, NULL,
10);
}
} while (mhpcRevInfo.sensor >= i);
printf ("Enter serial number: %s ",
(char *) &mhpcRevInfo.serial);
if (6 == cli_readline(NULL)) {
for (i = 0; i < 6; i++) {
mhpcRevInfo.serial[i] = console_buffer[i];
}
mhpcRevInfo.serial[6] = '\0';
}
printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
if (12 == cli_readline(NULL)) {
for (i = 0; i < 12; i += 2) {
mhpcRevInfo.etheraddr[i >> 1] =
(char) (16 *
hex[toupper
(console_buffer[i]) -
'0'] +
hex[toupper
(console_buffer[i + 1]) -
'0']);
}
}
/* setup new revision data */
eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo,
32);
}
/* set environment */
sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x",
mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
setenv ("ethaddr", nid);
/* print actual board identification */
printf ("Ident: %s %s Ser %s Rev %c%c\n",
mhpcRevInfo.board,
(mhpcRevInfo.sensor == 0 ? "color" : "b&w"),
(char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0],
mhpcRevInfo.revision[1]);
return (0);
}
/* ------------------------------------------------------------------------- */
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */
memctl->memc_mptpr = MPTPR_PTP_DIV64;
memctl->memc_mar = 0x00008800;
/*
* Map controller SDRAM bank 0
*/
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
udelay (200);
/*
* Map controller SDRAM bank 1
*/
memctl->memc_or2 = CONFIG_SYS_OR2;
memctl->memc_br2 = CONFIG_SYS_BR2;
/*
* Perform SDRAM initializsation sequence
*/
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
udelay (1);
memctl->memc_mcr = 0x80002730; /* SDRAM bank 0 - execute twice */
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (10000);
/* leave place for framebuffers */
return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE);
}
/* ------------------------------------------------------------------------- */
static void video_circle (char *center, int radius, int color, int pitch)
{
int x, y, d, dE, dSE;
x = 0;
y = radius;
d = 1 - radius;
dE = 3;
dSE = -2 * radius + 5;
*(center + x + y * pitch) = color;
*(center + y + x * pitch) = color;
*(center + y - x * pitch) = color;
*(center + x - y * pitch) = color;
*(center - x - y * pitch) = color;
*(center - y - x * pitch) = color;
*(center - y + x * pitch) = color;
*(center - x + y * pitch) = color;
while (y > x) {
if (d < 0) {
d += dE;
dE += 2;
dSE += 2;
x++;
} else {
d += dSE;
dE += 2;
dSE += 4;
x++;
y--;
}
*(center + x + y * pitch) = color;
*(center + y + x * pitch) = color;
*(center + y - x * pitch) = color;
*(center + x - y * pitch) = color;
*(center - x - y * pitch) = color;
*(center - y - x * pitch) = color;
*(center - y + x * pitch) = color;
*(center - x + y * pitch) = color;
}
}
/* ------------------------------------------------------------------------- */
static void video_test_image (void)
{
char *di;
int i, n;
/* draw raster */
for (i = 0; i < LCD_VIDEO_ROWS; i += 32) {
memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS),
LCD_VIDEO_FG, LCD_VIDEO_COLS);
for (n = i + 1; n < i + 32; n++)
memset ((char *) (LCD_VIDEO_ADDR +
n * LCD_VIDEO_COLS), LCD_VIDEO_BG,
LCD_VIDEO_COLS);
}
for (i = 0; i < LCD_VIDEO_COLS; i += 32) {
for (n = 0; n < LCD_VIDEO_ROWS; n++)
*(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) =
LCD_VIDEO_FG;
}
/* draw gray bar */
di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 +
97 * LCD_VIDEO_COLS);
for (n = 0; n < 63; n++) {
for (i = 0; i < 256; i++) {
*di++ = (char) i;
*(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255;
}
di += LCD_VIDEO_COLS - 256;
}
video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 +
LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2,
LCD_VIDEO_FG, LCD_VIDEO_COLS);
}
/* ------------------------------------------------------------------------- */
static void video_default_lut (unsigned int clut_type)
{
unsigned int i;
unsigned char RGB[] = {
0x00, 0x00, 0x00, /* black */
0x80, 0x80, 0x80, /* gray */
0xff, 0x00, 0x00, /* red */
0x00, 0xff, 0x00, /* green */
0x00, 0x00, 0xff, /* blue */
0x00, 0xff, 0xff, /* cyan */
0xff, 0x00, 0xff, /* magenta */
0xff, 0xff, 0x00, /* yellow */
0x80, 0x00, 0x00, /* dark red */
0x00, 0x80, 0x00, /* dark green */
0x00, 0x00, 0x80, /* dark blue */
0x00, 0x80, 0x80, /* dark cyan */
0x80, 0x00, 0x80, /* dark magenta */
0x80, 0x80, 0x00, /* dark yellow */
0xc0, 0xc0, 0xc0, /* light gray */
0xff, 0xff, 0xff, /* white */
};
switch (clut_type) {
case 1:
for (i = 0; i < 240; i++)
video_set_lut (i, i, i, i);
for (i = 0; i < 16; i++)
video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1],
RGB[i * 3 + 2]);
break;
default:
for (i = 0; i < 256; i++)
video_set_lut (i, i, i, i);
}
}
/* ------------------------------------------------------------------------- */
void *video_hw_init (void)
{
unsigned int clut = 0;
unsigned char *penv;
immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
/* enable video only on CLUT value */
if ((penv = (uchar *)getenv ("clut")) != NULL)
clut = (u_int) simple_strtoul ((char *)penv, NULL, 10);
else
return NULL;
/* disable graphic before write LCD regs. */
immr->im_lcd.lcd_lccr = 0x96000866;
/* config LCD regs. */
immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
immr->im_lcd.lcd_lchcr = 0x010a0093;
immr->im_lcd.lcd_lcvcr = 0x900f0024;
printf ("Video: 640x480 8Bit Index Lut %s\n",
(clut == 1 ? "240/16 (gray/vga)" : "256(gray)"));
video_default_lut (clut);
/* clear framebuffer */
memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG,
LCD_VIDEO_ROWS * LCD_VIDEO_COLS);
/* enable graphic */
immr->im_lcd.lcd_lccr = 0x96000867;
/* fill in Graphic Device */
gdev.frameAdrs = LCD_VIDEO_ADDR;
gdev.winSizeX = LCD_VIDEO_COLS;
gdev.winSizeY = LCD_VIDEO_ROWS;
gdev.gdfBytesPP = 1;
gdev.gdfIndex = GDF__8BIT_INDEX;
if (clut > 1)
/* return Graphic Device for console */
return (void *) &gdev;
else
/* just graphic enabled - draw something beautiful */
video_test_image ();
return NULL; /* this disabels cfb - console */
}
/* ------------------------------------------------------------------------- */
void video_set_lut (unsigned int index,
unsigned char r, unsigned char g, unsigned char b)
{
unsigned int lum;
unsigned short *pLut = (unsigned short *) (CONFIG_SYS_IMMR + 0x0e00);
/* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
/* y = 0.299*R + 0.587*G + 0.114*B */
lum = (2990 * r + 5870 * g + 1140 * b) / 10000;
pLut[index] =
((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum &
0x3f);
}
/* ------------------------------------------------------------------------- */

121
board/eltec/mhpc/u-boot.lds.debug
View File

@ -1,121 +0,0 @@
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
__bss_end = . ;
PROVIDE (end = .);
}

37
board/esd/cpci750/64360.h
View File

@ -1,37 +0,0 @@
/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
* for cpci750 Reinhard Arlt
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* main board support/init for the cpci750.
*/
#ifndef __64360_H__
#define __64360_H__
/* CPU Configuration bits */
#define CPU_CONF_ADDR_MISS_EN (1 << 8)
#define CPU_CONF_SINGLE_CPU (1 << 11)
#define CPU_CONF_ENDIANESS (1 << 12)
#define CPU_CONF_PIPELINE (1 << 13)
#define CPU_CONF_STOP_RETRY (1 << 17)
#define CPU_CONF_MULTI_DECODE (1 << 18)
#define CPU_CONF_DP_VALID (1 << 19)
#define CPU_CONF_PERR_PROP (1 << 22)
#define CPU_CONF_AACK_DELAY_2 (1 << 25)
#define CPU_CONF_AP_VALID (1 << 26)
#define CPU_CONF_REMAP_WR_DIS (1 << 27)
/* CPU Master Control bits */
#define CPU_MAST_CTL_ARB_EN (1 << 8)
#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
#endif /* __64360_H__ */

12
board/esd/cpci750/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_CPCI750
config SYS_BOARD
default "cpci750"
config SYS_VENDOR
default "esd"
config SYS_CONFIG_NAME
default "CPCI750"
endif

6
board/esd/cpci750/MAINTAINERS
View File

@ -1,6 +0,0 @@
CPCI750 BOARD
M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
S: Maintained
F: board/esd/cpci750/
F: include/configs/CPCI750.h
F: configs/CPCI750_defconfig

14
board/esd/cpci750/Makefile
View File

@ -1,14 +0,0 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = misc.o
obj-y += cpci750.o serial.o ../../Marvell/common/memory.o pci.o \
mv_eth.o mpsc.o i2c.o \
sdram_init.o ide.o

1088
board/esd/cpci750/cpci750.c
View File

File diff suppressed because it is too large Load Diff

28
board/esd/cpci750/eth.h
View File

@ -1,28 +0,0 @@
/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* eth.h - header file for the polled mode GT ethernet driver
*/
#ifndef __EVB64360_ETH_H__
#define __EVB64360_ETH_H__
#include <asm/types.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <common.h>
int db64360_eth0_poll(void);
int db64360_eth0_transmit(unsigned int s, volatile char *p);
void db64360_eth0_disable(void);
bool network_start(bd_t *bis);
int mv6436x_eth_initialize(bd_t *);
#endif /* __EVB64360_ETH_H__ */

475
board/esd/cpci750/i2c.c
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@ -1,475 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Hacked for the DB64360 board by Ingo.Assmus@keymile.com
* extra improvments by Brain Waite
* for cpci750 by reinhard.arlt@esd-electronics.com
*/
#include <common.h>
#include <mpc8xx.h>
#include <malloc.h>
#include <i2c.h>
#include "../../Marvell/include/mv_gen_reg.h"
#include "../../Marvell/include/core.h"
#define I2C_DELAY 100
#undef DEBUG_I2C
#ifdef DEBUG_I2C
#define DP(x) x
#else
#define DP(x)
#endif
/* Assuming that there is only one master on the bus (us) */
void i2c_init (int speed, int slaveaddr)
{
unsigned int n, m, freq, margin, power;
unsigned int actualN = 0, actualM = 0;
unsigned int minMargin = 0xffffffff;
unsigned int tclk = CONFIG_SYS_TCLK;
unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */
DP (puts ("i2c_init\n"));
/* gtI2cMasterInit */
for (n = 0; n < 8; n++) {
for (m = 0; m < 16; m++) {
power = 2 << n; /* power = 2^(n+1) */
freq = tclk / (10 * (m + 1) * power);
if (i2cFreq > freq)
margin = i2cFreq - freq;
else
margin = freq - i2cFreq;
if (margin < minMargin) {
minMargin = margin;
actualN = n;
actualM = m;
}
}
}
DP (puts ("setup i2c bus\n"));
/* Setup bus */
/* gtI2cReset */
GT_REG_WRITE (I2C_SOFT_RESET, 0);
asm(" sync");
GT_REG_WRITE (I2C_CONTROL, 0);
asm(" sync");
DP (puts ("set baudrate\n"));
GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
asm(" sync");
DP (puts ("udelay...\n"));
udelay (I2C_DELAY);
GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
asm(" sync");
}
static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
{
unsigned int status, data, bits = 7;
unsigned int control;
int count = 0;
DP (puts ("i2c_select_device\n"));
/* Output slave address */
if (ten_bit) {
bits = 10;
}
GT_REG_READ (I2C_CONTROL, &control);
control |= (0x1 << 2);
GT_REG_WRITE (I2C_CONTROL, control);
asm(" sync");
GT_REG_READ (I2C_CONTROL, &control);
control |= (0x1 << 5); /* generate the I2C_START_BIT */
GT_REG_WRITE (I2C_CONTROL, control);
asm(" sync");
RESET_REG_BITS (I2C_CONTROL, (0x01 << 3));
asm(" sync");
GT_REG_READ (I2C_CONTROL, &status);
while ((status & 0x08) != 0x08) {
GT_REG_READ (I2C_CONTROL, &status);
}
count = 0;
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){
if (count > 200) {
#ifdef DEBUG_I2C
printf ("Failed to set startbit: 0x%02x\n", status);
#endif
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
asm(" sync");
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
DP (puts ("i2c_select_device:write addr byte\n"));
/* assert the address */
data = (dev_addr << 1);
/* set the read bit */
data |= read;
GT_REG_WRITE (I2C_DATA, data);
asm(" sync");
RESET_REG_BITS (I2C_CONTROL, BIT3);
asm(" sync");
GT_REG_READ (I2C_CONTROL, &status);
while ((status & 0x08) != 0x08) {
GT_REG_READ (I2C_CONTROL, &status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count = 0;
while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
if (count > 200) {
#ifdef DEBUG_I2C
printf ("Failed to write address: 0x%02x\n", status);
#endif
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
asm(" sync");
count++;
}
if (bits == 10) {
printf ("10 bit I2C addressing not yet implemented\n");
return (0xff);
}
return (0);
}
static uchar i2c_get_data (uchar * return_data, int len)
{
unsigned int data, status;
int count = 0;
DP (puts ("i2c_get_data\n"));
while (len) {
RESET_REG_BITS (I2C_CONTROL, BIT3);
asm(" sync");
/* Get and return the data */
GT_REG_READ (I2C_CONTROL, &status);
while ((status & 0x08) != 0x08) {
GT_REG_READ (I2C_CONTROL, &status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
while ((status & 0xff) != 0x50) {
if (count > 20) {
#ifdef DEBUG_I2C
printf ("Failed to get data len status: 0x%02x\n", status);
#endif
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
asm(" sync");
return 0;
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
GT_REG_READ (I2C_DATA, &data);
len--;
*return_data = (uchar) data;
return_data++;
}
RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
asm(" sync");
count = 0;
GT_REG_READ (I2C_CONTROL, &status);
while ((status & 0x08) != 0x08) {
GT_REG_READ (I2C_CONTROL, &status);
}
while ((status & 0xff) != 0x58) {
if (count > 2000) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */
asm(" sync");
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
asm(" sync");
return (0);
}
static uchar i2c_write_data (unsigned int *data, int len)
{
unsigned int status;
int count;
unsigned int temp;
unsigned int *temp_ptr = data;
DP (puts ("i2c_write_data\n"));
while (len) {
count = 0;
temp = (unsigned int) (*temp_ptr);
GT_REG_WRITE (I2C_DATA, temp);
asm(" sync");
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
asm(" sync");
GT_REG_READ (I2C_CONTROL, &status);
while ((status & 0x08) != 0x08) {
GT_REG_READ (I2C_CONTROL, &status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
while ((status & 0xff) != 0x28) {
if (count > 200) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
asm(" sync");
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
len--;
temp_ptr++;
}
return (0);
}
static uchar i2c_write_byte (unsigned char *data, int len)
{
unsigned int status;
int count;
unsigned int temp;
unsigned char *temp_ptr = data;
DP (puts ("i2c_write_byte\n"));
while (len) {
count = 0;
/* Set and assert the data */
temp = *temp_ptr;
GT_REG_WRITE (I2C_DATA, temp);
asm(" sync");
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
asm(" sync");
GT_REG_READ (I2C_CONTROL, &status);
while ((status & 0x08) != 0x08) {
GT_REG_READ (I2C_CONTROL, &status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
while ((status & 0xff) != 0x28) {
if (count > 200) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
asm(" sync");
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
len--;
temp_ptr++;
}
return (0);
}
static uchar
i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
int alen)
{
uchar status;
unsigned int table[2];
table[1] = (offset ) & 0x0ff; /* low byte */
table[0] = (offset >> 8) & 0x0ff; /* high byte */
DP (puts ("i2c_set_dev_offset\n"));
status = i2c_select_device (dev_addr, 0, ten_bit);
if (status) {
#ifdef DEBUG_I2C
22 printf ("Failed to select device setting offset: 0x%02x\n",
status);
#endif
return status;
}
/* check the address offset length */
if (alen == 0)
/* no address offset */
return (0);
else if (alen == 1) {
/* 1 byte address offset */
status = i2c_write_data (&offset, 1);
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to write data: 0x%02x\n", status);
#endif
return status;
}
} else if (alen == 2) {
/* 2 bytes address offset */
status = i2c_write_data (table, 2);
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to write data: 0x%02x\n", status);
#endif
return status;
}
} else {
/* address offset unknown or not supported */
printf ("Address length offset %d is not supported\n", alen);
return 1;
}
return 0; /* sucessful completion */
}
int
i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
int len)
{
uchar status = 0;
unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_read\n"));
/* set the i2c frequency */
i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to set slave address & offset: 0x%02x\n",
status);
#endif
return status;
}
status = i2c_select_device (dev_addr, 1, 0);
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to select device for data read: 0x%02x\n",
status);
#endif
return status;
}
status = i2c_get_data (data, len);
if (status) {
#ifdef DEBUG_I2C
printf ("Data not read: 0x%02x\n", status);
#endif
return status;
}
return 0;
}
void i2c_stop (void)
{
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
asm(" sync");
}
int
i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
int len)
{
uchar status = 0;
unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_write\n"));
/* set the i2c frequency */
i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to set slave address & offset: 0x%02x\n",
status);
#endif
return status;
}
status = i2c_write_byte (data, len); /* write the data */
if (status) {
#ifdef DEBUG_I2C
printf ("Data not written: 0x%02x\n", status);
#endif
return status;
}
/* issue a stop bit */
i2c_stop ();
return 0;
}
int i2c_probe (uchar chip)
{
#ifdef DEBUG_I2C
unsigned int i2c_status;
#endif
uchar status = 0;
unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_probe\n"));
/* set the i2c frequency */
i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to set slave address: 0x%02x\n", status);
#endif
return (int) status;
}
#ifdef DEBUG_I2C
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
printf ("address %#x returned %#x\n", chip, i2c_status);
#endif
/* issue a stop bit */
i2c_stop ();
return 0; /* successful completion */
}

16
board/esd/cpci750/i2c.h
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@ -1,16 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Hacked for the DB64360 board by Ingo.Assmus@keymile.com
*/
#ifndef __I2C_H__
#define __I2C_H__
/* function declarations */
uchar i2c_read(uchar, unsigned int, int, uchar*, int);
#endif

74
board/esd/cpci750/ide.c
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@ -1,74 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* ide.c - ide support functions */
#include <common.h>
#if defined(CONFIG_CMD_IDE)
#include <ata.h>
#include <ide.h>
#include <pci.h>
int cpci_hd_type;
int ata_device(int dev)
{
int retval;
retval = (dev & 1) << 4;
if (cpci_hd_type == 2)
retval ^= 1 << 4;
return retval;
}
int ide_preinit (void)
{
int status;
pci_dev_t devbusfn;
int l;
status = 1;
cpci_hd_type = 0;
if (CPCI750_SLAVE_TEST != 0)
return status;
for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
ide_bus_offset[l] = -ATA_STATUS;
}
devbusfn = pci_find_device (0x1103, 0x0004, 0);
if (devbusfn != -1) {
cpci_hd_type = 1;
} else {
devbusfn = pci_find_device (0x1095, 0x3114, 0);
if (devbusfn != -1) {
cpci_hd_type = 2;
}
}
if (devbusfn != -1) {
ulong *ide_bus_offset_ptr;
status = 0;
ide_bus_offset_ptr = &ide_bus_offset[0];
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
(u32 *)ide_bus_offset_ptr);
ide_bus_offset[0] &= 0xfffffffe;
ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
ide_bus_offset_ptr = &ide_bus_offset[1];
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
(u32 *)ide_bus_offset_ptr);
ide_bus_offset[1] &= 0xfffffffe;
ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
}
return status;
}
void ide_set_reset (int flag) {
return;
}
#endif /* of CONFIG_CMDS_IDE */

69
board/esd/cpci750/local.h
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@ -1,69 +0,0 @@
/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* include/local.h - local configuration options, board specific
*/
#ifndef __LOCAL_H
#define __LOCAL_H
/*
* High Level Configuration Options
* (easy to change)
*/
/* This tells PPCBoot that the config options are compiled in */
/* #undef ENV_IS_EMBEDDED */
/* Don't touch this! PPCBOOT figures this out based on other
* magic. */
/* Uncomment and define any of the below options */
/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */
#define CONFIG_750FX /* The 750FX doesn't support as many things in L2CR like 750CX*/
/* These want string arguments */
/* #define CONFIG_BOOTARGS */
/* #define CONFIG_BOOTCOMMAND */
/* #define CONFIG_RAMBOOTCOMMAND */
/* #define CONFIG_NFSBOOTCOMMAND */
/* #define CONFIG_SYS_AUTOLOAD */
/* #define CONFIG_PREBOOT */
/* These don't */
/* #define CONFIG_BOOTDELAY */
/* #define CONFIG_BAUDRATE */
/* #define CONFIG_LOADS_ECHO */
/* #define CONFIG_ETHADDR */
/* #define CONFIG_ETH2ADDR */
/* #define CONFIG_ETH3ADDR */
/* #define CONFIG_IPADDR */
/* #define CONFIG_SERVERIP */
/* #define CONFIG_ROOTPATH */
/* #define CONFIG_GATEWAYIP */
/* #define CONFIG_NETMASK */
/* #define CONFIG_HOSTNAME */
/* #define CONFIG_BOOTFILE */
/* #define CONFIG_LOADADDR */
/* these hardware addresses are pretty bogus, please change them to
suit your needs */
/* first ethernet */
/* #define CONFIG_ETHADDR 86:06:2d:7e:c6:53 */
#define CONFIG_ETHADDR 64:36:00:00:00:01
/* next two ethernet hwaddrs */
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 86:06:2d:7e:c6:54
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 86:06:2d:7e:c6:55
#define CONFIG_ENV_OVERWRITE
#endif /* __CONFIG_H */

245
board/esd/cpci750/misc.S
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@ -1,245 +0,0 @@
#include <config.h>
#include <74xx_7xx.h>
#include "version.h"
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include "../../Marvell/include/mv_gen_reg.h"
#ifdef CONFIG_ECC
/* Galileo specific asm code for initializing ECC */
.globl board_relocate_rom
board_relocate_rom:
mflr r7
/* update the location of the GT registers */
lis r11, CONFIG_SYS_GT_REGS@h
/* if we're using ECC, we must use the DMA engine to copy ourselves */
bl start_idma_transfer_0
bl wait_for_idma_0
bl stop_idma_engine_0
mtlr r7
blr
.globl board_init_ecc
board_init_ecc:
mflr r7
/* NOTE: r10 still contains the location we've been relocated to
* which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
/* now that we're running from ram, init the rest of main memory
* for ECC use */
lis r8, CONFIG_SYS_MONITOR_LEN@h
ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
divw r3, r10, r8
/* set up the counter, and init the starting address */
mtctr r3
li r12, 0
/* bytes per transfer */
mr r5, r8
about_to_init_ecc:
1: mr r3, r12
mr r4, r12
bl start_idma_transfer_0
bl wait_for_idma_0
bl stop_idma_engine_0
add r12, r12, r8
bdnz 1b
mtlr r7
blr
/* r3: dest addr
* r4: source addr
* r5: byte count
* r11: gt regbase
* trashes: r6, r5
*/
start_idma_transfer_0:
/* set the byte count, including the OWN bit */
mr r6, r11
ori r6, r6, CHANNEL0_DMA_BYTE_COUNT
stwbrx r5, 0, (r6)
/* set the source address */
mr r6, r11
ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
stwbrx r4, 0, (r6)
/* set the dest address */
mr r6, r11
ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
stwbrx r3, 0, (r6)
/* set the next record pointer */
li r5, 0
mr r6, r11
ori r6, r6, CHANNEL0NEXT_RECORD_POINTER
stwbrx r5, 0, (r6)
/* set the low control register */
/* bit 9 is NON chained mode, bit 31 is new style descriptors.
bit 12 is channel enable */
ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
/* 15 shifted by 16 (oris) == bit 31 */
oris r5, r5, (1 << 15)
mr r6, r11
ori r6, r6, CHANNEL0CONTROL
stwbrx r5, 0, (r6)
blr
/* this waits for the bytecount to return to zero, indicating
* that the trasfer is complete */
wait_for_idma_0:
mr r5, r11
lis r6, 0xff
ori r6, r6, 0xffff
ori r5, r5, CHANNEL0_DMA_BYTE_COUNT
1: lwbrx r4, 0, (r5)
and. r4, r4, r6
bne 1b
blr
/* this turns off channel 0 of the idma engine */
stop_idma_engine_0:
/* shut off the DMA engine */
li r5, 0
mr r6, r11
ori r6, r6, CHANNEL0CONTROL
stwbrx r5, 0, (r6)
blr
#endif
#ifdef CONFIG_SYS_BOARD_ASM_INIT
/* NOTE: trashes r3-r7 */
.globl board_asm_init
board_asm_init:
/* just move the GT registers to where they belong */
lis r3, CONFIG_SYS_DFL_GT_REGS@h
ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
lis r4, CONFIG_SYS_GT_REGS@h
ori r4, r4, CONFIG_SYS_GT_REGS@l
li r5, INTERNAL_SPACE_DECODE
/* test to see if we've already moved */
lwbrx r6, r5, r4
andi. r6, r6, 0xffff
/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
/* rlwinm r7, r4, 8, 16, 31
rlwinm r7, r4, 12, 16, 31 */ /* original */
rlwinm r7, r4, 16, 16, 31
/* -----------------------------------------------------*/
cmp cr0, r7, r6
beqlr
/* nope, have to move the registers */
lwbrx r6, r5, r3
andis. r6, r6, 0xffff
or r6, r6, r7
stwbrx r6, r5, r3
/* now, poll for the change */
1: lwbrx r7, r5, r4
cmp cr0, r7, r6
bne 1b
lis r3, CONFIG_SYS_INT_SRAM_BASE@h
ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
rlwinm r3, r3, 16, 16, 31
lis r4, CONFIG_SYS_GT_REGS@h
ori r4, r4, CONFIG_SYS_GT_REGS@l
li r5, INTEGRATED_SRAM_BASE_ADDR
stwbrx r3, r5, r4
2: lwbrx r6, r5, r4
cmp cr0, r3, r6
bne 2b
/* done! */
blr
#endif
/* For use of the debug LEDs */
.global led_on0_relocated
led_on0_relocated:
xor r21, r21, r21
xor r18, r18, r18
lis r18, 0xFC80
ori r18, r18, 0x8000
/* stw r21, 0x0(r18) */
sync
blr
.global led_off0_relocated
led_off0_relocated:
xor r21, r21, r21
xor r18, r18, r18
lis r18, 0xFC81
ori r18, r18, 0x4000
/* stw r21, 0x0(r18) */
sync
blr
.global led_on0
led_on0:
xor r18, r18, r18
lis r18, 0x1c80
ori r18, r18, 0x8000
/* stw r18, 0x0(r18) */
sync
blr
.global led_off0
led_off0:
xor r18, r18, r18
lis r18, 0x1c81
ori r18, r18, 0x4000
/* stw r18, 0x0(r18) */
sync
blr
.global led_on1
led_on1:
xor r18, r18, r18
lis r18, 0x1c80
ori r18, r18, 0xc000
/* stw r18, 0x0(r18) */
sync
blr
.global led_off1
led_off1:
xor r18, r18, r18
lis r18, 0x1c81
ori r18, r18, 0x8000
/* stw r18, 0x0(r18) */
sync
blr
.global led_on2
led_on2:
xor r18, r18, r18
lis r18, 0x1c81
ori r18, r18, 0x0000
/* stw r18, 0x0(r18) */
sync
blr
.global led_off2
led_off2:
xor r18, r18, r18
lis r18, 0x1c81
ori r18, r18, 0xc000
/* stw r18, 0x0(r18) */
sync
blr

1002
board/esd/cpci750/mpsc.c
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board/esd/cpci750/mpsc.h
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/*
* (C) Copyright 2001
* John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*************************************************************************
* changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
*
************************************************************************/
/*
* mpsc.h - header file for MPSC in uart mode (console driver)
*/
#ifndef __MPSC_H__
#define __MPSC_H__
/* include actual Galileo defines */
#include "../../Marvell/include/mv_gen_reg.h"
/* driver related defines */
int mpsc_init(int baud);
void mpsc_sdma_init(void);
void mpsc_init2(void);
int galbrg_set_baudrate(int channel, int rate);
int mpsc_putchar_early(char ch);
char mpsc_getchar_debug(void);
int mpsc_test_char_debug(void);
int mpsc_test_char_sdma(void);
extern int (*mpsc_putchar)(char ch);
extern char (*mpsc_getchar)(void);
extern int (*mpsc_test_char)(void);
#define CHANNEL CONFIG_MPSC_PORT
#define TX_DESC 5
#define RX_DESC 20
#define DESC_FIRST 0x00010000
#define DESC_LAST 0x00020000
#define DESC_OWNER_BIT 0x80000000
#define TX_DEMAND 0x00800000
#define TX_STOP 0x00010000
#define RX_ENABLE 0x00000080
#define SDMA_RX_ABORT (1 << 15)
#define SDMA_TX_ABORT (1 << 31)
#define MPSC_TX_ABORT (1 << 7)
#define MPSC_RX_ABORT (1 << 23)
#define MPSC_ENTER_HUNT (1 << 31)
/* MPSC defines */
#define GALMPSC_CONNECT 0x1
#define GALMPSC_DISCONNECT 0x0
#define GALMPSC_UART 0x1
#define GALMPSC_STOP_BITS_1 0x0
#define GALMPSC_STOP_BITS_2 0x1
#define GALMPSC_CHAR_LENGTH_8 0x3
#define GALMPSC_CHAR_LENGTH_7 0x2
#define GALMPSC_PARITY_ODD 0x0
#define GALMPSC_PARITY_EVEN 0x2
#define GALMPSC_PARITY_MARK 0x3
#define GALMPSC_PARITY_SPACE 0x1
#define GALMPSC_PARITY_NONE -1
#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
#define GALMPSC_REG_GAP 0x1000
#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
#define GALSDMA_COMMAND_FIRST (1 << 16)
#define GALSDMA_COMMAND_LAST (1 << 17)
#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
#define GALSDMA_COMMAND_AUTO (1 << 30)
#define GALSDMA_COMMAND_OWNER (1 << 31)
#define GALSDMA_RX 0
#define GALSDMA_TX 1
/* CHANNEL2 should be CHANNEL1, according to documentation,
* but to work with the current GTREGS file...
*/
#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
#define GALSDMA_REG_DIFF 0x2000
/* WRONG in gt64260R.h */
#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
#define GALMPSC_0_INT_CAUSE 0xb804
#define GALMPSC_0_INT_MASK 0xb884
#define GALSDMA_MODE_UART 0
#define GALSDMA_MODE_BISYNC 1
#define GALSDMA_MODE_HDLC 2
#define GALSDMA_MODE_TRANSPARENT 3
#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
#define GALBRG_REG_GAP 0x0008
#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
#endif /* __MPSC_H__ */

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board/esd/cpci750/mv_eth.c
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board/esd/cpci750/mv_eth.h
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/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
*
* based on - Driver for MV64360X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* mv_eth.h - header file for the polled mode GT ethernet driver
*/
#ifndef __DB64360_ETH_H__
#define __DB64360_ETH_H__
#include <asm/types.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <common.h>
#include <net.h>
#include "mv_regs.h"
#include <asm/errno.h>
/*************************************************************************
**************************************************************************
**************************************************************************
* The first part is the high level driver of the gigE ethernet ports. *
**************************************************************************
**************************************************************************
*************************************************************************/
/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
#ifndef MAX_SKB_FRAGS
#define MAX_SKB_FRAGS 0
#endif
/* Port attributes */
/*#define MAX_RX_QUEUE_NUM 8*/
/*#define MAX_TX_QUEUE_NUM 8*/
#define MAX_RX_QUEUE_NUM 1
#define MAX_TX_QUEUE_NUM 1
/* Use one TX queue and one RX queue */
#define MV64360_TX_QUEUE_NUM 1
#define MV64360_RX_QUEUE_NUM 1
/*
* Number of RX / TX descriptors on RX / TX rings.
* Note that allocating RX descriptors is done by allocating the RX
* ring AND a preallocated RX buffers (skb's) for each descriptor.
* The TX descriptors only allocates the TX descriptors ring,
* with no pre allocated TX buffers (skb's are allocated by higher layers.
*/
/* Default TX ring size is 10 descriptors */
#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
#else
#define MV64360_TX_QUEUE_SIZE 4
#endif
/* Default RX ring size is 4 descriptors */
#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE
#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
#else
#define MV64360_RX_QUEUE_SIZE 4
#endif
#ifdef CONFIG_RX_BUFFER_SIZE
#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
#else
#define MV64360_RX_BUFFER_SIZE 1600
#endif
#ifdef CONFIG_TX_BUFFER_SIZE
#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
#else
#define MV64360_TX_BUFFER_SIZE 1600
#endif
/*
* Network device statistics. Akin to the 2.0 ether stats but
* with byte counters.
*/
struct net_device_stats
{
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_errors; /* bad packets received */
unsigned long tx_errors; /* packet transmit problems */
unsigned long rx_dropped; /* no space in linux buffers */
unsigned long tx_dropped; /* no space available in linux */
unsigned long multicast; /* multicast packets received */
unsigned long collisions;
/* detailed rx_errors: */
unsigned long rx_length_errors;
unsigned long rx_over_errors; /* receiver ring buff overflow */
unsigned long rx_crc_errors; /* recved pkt with crc error */
unsigned long rx_frame_errors; /* recv'd frame alignment error */
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
unsigned long rx_missed_errors; /* receiver missed packet */
/* detailed tx_errors */
unsigned long tx_aborted_errors;
unsigned long tx_carrier_errors;
unsigned long tx_fifo_errors;
unsigned long tx_heartbeat_errors;
unsigned long tx_window_errors;
/* for cslip etc */
unsigned long rx_compressed;
unsigned long tx_compressed;
};
/* Private data structure used for ethernet device */
struct mv64360_eth_priv {
unsigned int port_num;
struct net_device_stats *stats;
/* to buffer area aligned */
char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
/* Size of Tx Ring per queue */
unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
/* Size of Rx Ring per queue */
unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
/* Magic Number for Ethernet running */
unsigned int eth_running;
};
int mv64360_eth_init (struct eth_device *dev);
int mv64360_eth_stop (struct eth_device *dev);
int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
int mv64360_eth_open (struct eth_device *dev);
/*************************************************************************
**************************************************************************
**************************************************************************
* The second part is the low level driver of the gigE ethernet ports. *
**************************************************************************
**************************************************************************
*************************************************************************/
/********************************************************************************
* Header File for : MV-643xx network interface header
*
* DESCRIPTION:
* This header file contains macros typedefs and function declaration for
* the Marvell Gig Bit Ethernet Controller.
*
* DEPENDENCIES:
* None.
*
*******************************************************************************/
#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
#ifdef CONFIG_MV64360_SRAM_CACHEABLE
/* In case SRAM is cacheable but not cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) \
{ \
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
}
#else
/* In case SRAM is cache coherent or non-cacheable */
#define D_CACHE_FLUSH_LINE(addr, offset) ;
#endif
#else
#ifdef CONFIG_NOT_COHERENT_CACHE
/* In case of descriptors on DDR but not cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) \
{ \
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
}
#else
/* In case of descriptors on DDR and cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) ;
#endif /* CONFIG_NOT_COHERENT_CACHE */
#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
#define CPU_PIPE_FLUSH \
{ \
__asm__ __volatile__ ("eieio"); \
}
/* defines */
/* Default port configuration value */
#define PORT_CONFIG_VALUE \
ETH_UNICAST_NORMAL_MODE | \
ETH_DEFAULT_RX_QUEUE_0 | \
ETH_DEFAULT_RX_ARP_QUEUE_0 | \
ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
ETH_RECEIVE_BC_IF_IP | \
ETH_RECEIVE_BC_IF_ARP | \
ETH_CAPTURE_TCP_FRAMES_DIS | \
ETH_CAPTURE_UDP_FRAMES_DIS | \
ETH_DEFAULT_RX_TCP_QUEUE_0 | \
ETH_DEFAULT_RX_UDP_QUEUE_0 | \
ETH_DEFAULT_RX_BPDU_QUEUE_0
/* Default port extend configuration value */
#define PORT_CONFIG_EXTEND_VALUE \
ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
ETH_PARTITION_DISABLE
/* Default sdma control value */
#ifdef CONFIG_NOT_COHERENT_CACHE
#define PORT_SDMA_CONFIG_VALUE \
ETH_RX_BURST_SIZE_16_64BIT | \
GT_ETH_IPG_INT_RX(0) | \
ETH_TX_BURST_SIZE_16_64BIT;
#else
#define PORT_SDMA_CONFIG_VALUE \
ETH_RX_BURST_SIZE_4_64BIT | \
GT_ETH_IPG_INT_RX(0) | \
ETH_TX_BURST_SIZE_4_64BIT;
#endif
#define GT_ETH_IPG_INT_RX(value) \
((value & 0x3fff) << 8)
/* Default port serial control value */
#define PORT_SERIAL_CONTROL_VALUE \
ETH_FORCE_LINK_PASS | \
ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
ETH_ADV_SYMMETRIC_FLOW_CTRL | \
ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
ETH_FORCE_BP_MODE_NO_JAM | \
BIT9 | \
ETH_DO_NOT_FORCE_LINK_FAIL | \
ETH_RETRANSMIT_16_ETTEMPTS | \
ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
ETH_DTE_ADV_0 | \
ETH_DISABLE_AUTO_NEG_BYPASS | \
ETH_AUTO_NEG_NO_CHANGE | \
ETH_MAX_RX_PACKET_1552BYTE | \
ETH_CLR_EXT_LOOPBACK | \
ETH_SET_FULL_DUPLEX_MODE | \
ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
#define RX_BUFFER_MAX_SIZE 0xFFFF
#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
#define RX_BUFFER_MIN_SIZE 0x8
#define TX_BUFFER_MIN_SIZE 0x8
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
/* MAC accepet/reject macros */
#define ACCEPT_MAC_ADDR 0
#define REJECT_MAC_ADDR 1
/* Size of a Tx/Rx descriptor used in chain list data structure */
#define RX_DESC_ALIGNED_SIZE 0x20
#define TX_DESC_ALIGNED_SIZE 0x20
/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
#define TX_BUF_OFFSET_IN_DESC 0x18
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Gap define */
#define ETH_BAR_GAP 0x8
#define ETH_SIZE_REG_GAP 0x8
#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
#define ETH_PORT_ACCESS_CTRL_GAP 0x4
/* Gigabit Ethernet Unit Global Registers */
/* MIB Counters register definitions */
#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
#define ETH_MIB_FRAMES_64_OCTETS 0x20
#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
#define ETH_MIB_GOOD_FRAMES_SENT 0x40
#define ETH_MIB_EXCESSIVE_COLLISION 0x44
#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
#define ETH_MIB_FC_SENT 0x54
#define ETH_MIB_GOOD_FC_RECEIVED 0x58
#define ETH_MIB_BAD_FC_RECEIVED 0x5c
#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
#define ETH_MIB_OVERSIZE_RECEIVED 0x68
#define ETH_MIB_JABBER_RECEIVED 0x6c
#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
#define ETH_MIB_BAD_CRC_EVENT 0x74
#define ETH_MIB_COLLISION 0x78
#define ETH_MIB_LATE_COLLISION 0x7c
/* Port serial status reg (PSR) */
#define ETH_INTERFACE_GMII_MII 0
#define ETH_INTERFACE_PCM BIT0
#define ETH_LINK_IS_DOWN 0
#define ETH_LINK_IS_UP BIT1
#define ETH_PORT_AT_HALF_DUPLEX 0
#define ETH_PORT_AT_FULL_DUPLEX BIT2
#define ETH_RX_FLOW_CTRL_DISABLED 0
#define ETH_RX_FLOW_CTRL_ENBALED BIT3
#define ETH_GMII_SPEED_100_10 0
#define ETH_GMII_SPEED_1000 BIT4
#define ETH_MII_SPEED_10 0
#define ETH_MII_SPEED_100 BIT5
#define ETH_NO_TX 0
#define ETH_TX_IN_PROGRESS BIT7
#define ETH_BYPASS_NO_ACTIVE 0
#define ETH_BYPASS_ACTIVE BIT8
#define ETH_PORT_NOT_AT_PARTITION_STATE 0
#define ETH_PORT_AT_PARTITION_STATE BIT9
#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
#define ETH_PORT_TX_FIFO_EMPTY BIT10
/* These macros describes the Port configuration reg (Px_cR) bits */
#define ETH_UNICAST_NORMAL_MODE 0
#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
#define ETH_DEFAULT_RX_QUEUE_0 0
#define ETH_DEFAULT_RX_QUEUE_1 BIT1
#define ETH_DEFAULT_RX_QUEUE_2 BIT2
#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
#define ETH_DEFAULT_RX_QUEUE_4 BIT3
#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
#define ETH_RECEIVE_BC_IF_IP 0
#define ETH_REJECT_BC_IF_IP BIT8
#define ETH_RECEIVE_BC_IF_ARP 0
#define ETH_REJECT_BC_IF_ARP BIT9
#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
#define ETH_CAPTURE_TCP_FRAMES_DIS 0
#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
#define ETH_CAPTURE_UDP_FRAMES_DIS 0
#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
#define ETH_CLASSIFY_EN BIT0
#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
#define ETH_PARTITION_DISABLE 0
#define ETH_PARTITION_ENABLE BIT2
/* Tx/Rx queue command reg (RQCR/TQCR)*/
#define ETH_QUEUE_0_ENABLE BIT0
#define ETH_QUEUE_1_ENABLE BIT1
#define ETH_QUEUE_2_ENABLE BIT2
#define ETH_QUEUE_3_ENABLE BIT3
#define ETH_QUEUE_4_ENABLE BIT4
#define ETH_QUEUE_5_ENABLE BIT5
#define ETH_QUEUE_6_ENABLE BIT6
#define ETH_QUEUE_7_ENABLE BIT7
#define ETH_QUEUE_0_DISABLE BIT8
#define ETH_QUEUE_1_DISABLE BIT9
#define ETH_QUEUE_2_DISABLE BIT10
#define ETH_QUEUE_3_DISABLE BIT11
#define ETH_QUEUE_4_DISABLE BIT12
#define ETH_QUEUE_5_DISABLE BIT13
#define ETH_QUEUE_6_DISABLE BIT14
#define ETH_QUEUE_7_DISABLE BIT15
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
#define ETH_RIFB BIT0
#define ETH_RX_BURST_SIZE_1_64BIT 0
#define ETH_RX_BURST_SIZE_2_64BIT BIT1
#define ETH_RX_BURST_SIZE_4_64BIT BIT2
#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
#define ETH_RX_BURST_SIZE_16_64BIT BIT3
#define ETH_BLM_RX_NO_SWAP BIT4
#define ETH_BLM_RX_BYTE_SWAP 0
#define ETH_BLM_TX_NO_SWAP BIT5
#define ETH_BLM_TX_BYTE_SWAP 0
#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
#define ETH_DESCRIPTORS_NO_SWAP 0
#define ETH_TX_BURST_SIZE_1_64BIT 0
#define ETH_TX_BURST_SIZE_2_64BIT BIT22
#define ETH_TX_BURST_SIZE_4_64BIT BIT23
#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
#define ETH_TX_BURST_SIZE_16_64BIT BIT24
/* These macros describes the Port serial control reg (PSCR) bits */
#define ETH_SERIAL_PORT_DISABLE 0
#define ETH_SERIAL_PORT_ENABLE BIT0
#define ETH_FORCE_LINK_PASS BIT1
#define ETH_DO_NOT_FORCE_LINK_PASS 0
#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
#define ETH_ADV_NO_FLOW_CTRL 0
#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
#define ETH_FORCE_BP_MODE_NO_JAM 0
#define ETH_FORCE_BP_MODE_JAM_TX BIT7
#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
#define ETH_FORCE_LINK_FAIL 0
#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
#define ETH_RETRANSMIT_16_ETTEMPTS 0
#define ETH_RETRANSMIT_FOREVER BIT11
#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
#define ETH_DTE_ADV_0 0
#define ETH_DTE_ADV_1 BIT14
#define ETH_DISABLE_AUTO_NEG_BYPASS 0
#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
#define ETH_AUTO_NEG_NO_CHANGE 0
#define ETH_RESTART_AUTO_NEG BIT16
#define ETH_MAX_RX_PACKET_1518BYTE 0
#define ETH_MAX_RX_PACKET_1522BYTE BIT17
#define ETH_MAX_RX_PACKET_1552BYTE BIT18
#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
#define ETH_MAX_RX_PACKET_9192BYTE BIT19
#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
#define ETH_SET_EXT_LOOPBACK BIT20
#define ETH_CLR_EXT_LOOPBACK 0
#define ETH_SET_FULL_DUPLEX_MODE BIT21
#define ETH_SET_HALF_DUPLEX_MODE 0
#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
#define ETH_SET_GMII_SPEED_TO_10_100 0
#define ETH_SET_GMII_SPEED_TO_1000 BIT23
#define ETH_SET_MII_SPEED_TO_10 0
#define ETH_SET_MII_SPEED_TO_100 BIT24
/* SMI reg */
#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
#define ETH_ERROR_SUMMARY (BIT0)
/* Tx & Rx descriptors command */
#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
/* Tx descriptors status */
#define ETH_LC_ERROR (0 )
#define ETH_UR_ERROR (BIT1 )
#define ETH_RL_ERROR (BIT2 )
#define ETH_LLC_SNAP_FORMAT (BIT9 )
/* Rx descriptors status */
#define ETH_CRC_ERROR (0 )
#define ETH_OVERRUN_ERROR (BIT1 )
#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
#define ETH_VLAN_TAGGED (BIT19)
#define ETH_BPDU_FRAME (BIT20)
#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
#define ETH_OTHER_FRAME_TYPE (BIT22)
#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
#define ETH_FRAME_HEADER_OK (BIT25)
#define ETH_RX_LAST_DESC (BIT26)
#define ETH_RX_FIRST_DESC (BIT27)
#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
#define ETH_RX_ENABLE_INTERRUPT (BIT29)
#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
/* Rx descriptors byte count */
#define ETH_FRAME_FRAGMENTED (BIT2)
/* Tx descriptors command */
#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
#define ETH_FRAME_SET_TO_VLAN (BIT15)
#define ETH_TCP_FRAME (0 )
#define ETH_UDP_FRAME (BIT16)
#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
#define ETH_ZERO_PADDING (BIT19)
#define ETH_TX_LAST_DESC (BIT20)
#define ETH_TX_FIRST_DESC (BIT21)
#define ETH_GEN_CRC (BIT22)
#define ETH_TX_ENABLE_INTERRUPT (BIT23)
#define ETH_AUTO_MODE (BIT30)
/* Address decode parameters */
/* Ethernet Base Address Register bits */
#define EBAR_TARGET_DRAM 0x00000000
#define EBAR_TARGET_DEVICE 0x00000001
#define EBAR_TARGET_CBS 0x00000002
#define EBAR_TARGET_PCI0 0x00000003
#define EBAR_TARGET_PCI1 0x00000004
#define EBAR_TARGET_CUNIT 0x00000005
#define EBAR_TARGET_AUNIT 0x00000006
#define EBAR_TARGET_GUNIT 0x00000007
/* Window attributes */
#define EBAR_ATTR_DRAM_CS0 0x00000E00
#define EBAR_ATTR_DRAM_CS1 0x00000D00
#define EBAR_ATTR_DRAM_CS2 0x00000B00
#define EBAR_ATTR_DRAM_CS3 0x00000700
/* DRAM Target interface */
#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
/* Device Bus Target interface */
#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
/* PCI Target interface */
#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
/* CPU 60x bus or internal SRAM interface */
#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
#define EBAR_ATTR_CBS_SRAM 0x00000000
#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
/* Window access control */
#define EWIN_ACCESS_NOT_ALLOWED 0
#define EWIN_ACCESS_READ_ONLY BIT0
#define EWIN_ACCESS_FULL (BIT1 | BIT0)
#define EWIN0_ACCESS_MASK 0x0003
#define EWIN1_ACCESS_MASK 0x000C
#define EWIN2_ACCESS_MASK 0x0030
#define EWIN3_ACCESS_MASK 0x00C0
/* typedefs */
typedef enum _eth_port
{
ETH_0 = 0,
ETH_1 = 1,
ETH_2 = 2
}ETH_PORT;
typedef enum _eth_func_ret_status
{
ETH_OK, /* Returned as expected. */
ETH_ERROR, /* Fundamental error. */
ETH_RETRY, /* Could not process request. Try later. */
ETH_END_OF_JOB, /* Ring has nothing to process. */
ETH_QUEUE_FULL, /* Ring resource error. */
ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
}ETH_FUNC_RET_STATUS;
typedef enum _eth_queue
{
ETH_Q0 = 0,
ETH_Q1 = 1,
ETH_Q2 = 2,
ETH_Q3 = 3,
ETH_Q4 = 4,
ETH_Q5 = 5,
ETH_Q6 = 6,
ETH_Q7 = 7
} ETH_QUEUE;
typedef enum _addr_win
{
ETH_WIN0,
ETH_WIN1,
ETH_WIN2,
ETH_WIN3,
ETH_WIN4,
ETH_WIN5
} ETH_ADDR_WIN;
typedef enum _eth_target
{
ETH_TARGET_DRAM ,
ETH_TARGET_DEVICE,
ETH_TARGET_CBS ,
ETH_TARGET_PCI0 ,
ETH_TARGET_PCI1
}ETH_TARGET;
typedef struct _eth_rx_desc
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short buf_size ; /* Buffer size */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int next_desc_ptr; /* Next descriptor pointer */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} ETH_RX_DESC;
typedef struct _eth_tx_desc
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short l4i_chk ; /* CPU provided TCP Checksum */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int next_desc_ptr; /* Next descriptor pointer */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} ETH_TX_DESC;
/* Unified struct for Rx and Tx operations. The user is not required to */
/* be familier with neither Tx nor Rx descriptors. */
typedef struct _pkt_info
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} PKT_INFO;
typedef struct _eth_win_param
{
ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
ETH_TARGET target; /* System targets. See ETH_TARGET enum */
unsigned short attributes; /* BAR attributes. See above macros. */
unsigned int base_addr; /* Window base address in unsigned int form */
unsigned int high_addr; /* Window high address in unsigned int form */
unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
bool enable; /* Enable/disable access to the window. */
unsigned short access_ctrl; /* Access ctrl register. see above macros */
} ETH_WIN_PARAM;
/* Ethernet port specific infomation */
typedef struct _eth_port_ctrl
{
ETH_PORT port_num; /* User Ethernet port number */
int port_phy_addr; /* User phy address of Ethrnet port */
unsigned char port_mac_addr[6]; /* User defined port MAC address. */
unsigned int port_config; /* User port configuration value */
unsigned int port_config_extend; /* User port config extend value */
unsigned int port_sdma_config; /* User port SDMA config value */
unsigned int port_serial_control; /* User port serial control value */
unsigned int port_tx_queue_command; /* Port active Tx queues summary */
unsigned int port_rx_queue_command; /* Port active Rx queues summary */
/* User function to cast virtual address to CPU bus address */
unsigned int (*port_virt_to_phys)(unsigned int addr);
/* User scratch pad for user specific data structures */
void *port_private;
bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
/* Tx/Rx rings managment indexes fields. For driver use */
/* Next available Rx resource */
volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
/* Returning Rx resource */
volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
/* Next available Tx resource */
volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
/* Returning Tx resource */
volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
/* An extra Tx index to support transmit of multiple buffers per packet */
volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
/* Tx/Rx rings size and base variables fields. For driver use */
volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
} ETH_PORT_INFO;
/* ethernet.h API list */
/* Port operation control routines */
static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
static void eth_port_reset(ETH_PORT eth_port_num);
static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
/* Port MAC address routines */
static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
unsigned char *p_addr,
ETH_QUEUE queue);
#if 0 /* FIXME */
static void eth_port_mc_addr (ETH_PORT eth_port_num,
unsigned char *p_addr,
ETH_QUEUE queue,
int option);
#endif
/* PHY and MIB routines */
static bool ethernet_phy_reset(ETH_PORT eth_port_num);
static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
unsigned int phy_reg,
unsigned int value);
static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
unsigned int phy_reg,
unsigned int* value);
static void eth_clear_mib_counters(ETH_PORT eth_port_num);
/* Port data flow control routines */
static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
PKT_INFO *p_pkt_info);
static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
int tx_desc_num,
int tx_buff_size,
unsigned int tx_desc_base_addr,
unsigned int tx_buff_base_addr);
static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
int rx_desc_num,
int rx_buff_size,
unsigned int rx_desc_base_addr,
unsigned int rx_buff_base_addr);
#endif /* MV64360_ETH_ */

1108
board/esd/cpci750/mv_regs.h
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1028
board/esd/cpci750/pci.c
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1702
board/esd/cpci750/sdram_init.c
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106
board/esd/cpci750/serial.c
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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* modified for marvell db64360 eval board by
* Ingo Assmus <ingo.assmus@keymile.com>
*
* modified for cpci750 board by
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* serial.c - serial support for esd cpci750 board
*/
/* supports the MPSC */
#include <common.h>
#include <command.h>
#include <serial.h>
#include <linux/compiler.h>
#include "../../Marvell/include/memory.h"
#include "mpsc.h"
DECLARE_GLOBAL_DATA_PTR;
static int cpci750_serial_init(void)
{
mpsc_init (gd->baudrate);
return (0);
}
static void cpci750_serial_putc(const char c)
{
if (c == '\n')
mpsc_putchar ('\r');
mpsc_putchar (c);
}
static int cpci750_serial_getc(void)
{
return mpsc_getchar ();
}
static int cpci750_serial_tstc(void)
{
return mpsc_test_char ();
}
static void cpci750_serial_setbrg(void)
{
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
}
static struct serial_device cpci750_serial_drv = {
.name = "cpci750_serial",
.start = cpci750_serial_init,
.stop = NULL,
.setbrg = cpci750_serial_setbrg,
.putc = cpci750_serial_putc,
.puts = default_serial_puts,
.getc = cpci750_serial_getc,
.tstc = cpci750_serial_tstc,
};
void cpci750_serial_initialize(void)
{
serial_register(&cpci750_serial_drv);
}
__weak struct serial_device *default_serial_console(void)
{
return &cpci750_serial_drv;
}
#if defined(CONFIG_CMD_KGDB)
void kgdb_serial_init (void)
{
}
void putDebugChar (int c)
{
serial_putc (c);
}
void putDebugStr (const char *str)
{
serial_puts (str);
}
int getDebugChar (void)
{
return serial_getc ();
}
void kgdb_interruptible (int yes)
{
return;
}
#endif

12
board/exmeritus/hww1u1a/Kconfig
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if TARGET_HWW1U1A
config SYS_BOARD
default "hww1u1a"
config SYS_VENDOR
default "exmeritus"
config SYS_CONFIG_NAME
default "HWW1U1A"
endif

6
board/exmeritus/hww1u1a/MAINTAINERS
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HWW1U1A BOARD
#M: Kyle Moffett <Kyle.D.Moffett@boeing.com>
S: Orphan (since 2014-06)
F: board/exmeritus/hww1u1a/
F: include/configs/HWW1U1A.h
F: configs/HWW1U1A_defconfig

12
board/exmeritus/hww1u1a/Makefile
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#
# Copyright 2007-2009 Freescale Semiconductor, Inc.
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += hww1u1a.o
obj-y += law.o
obj-y += tlb.o
obj-$(CONFIG_DDR_SPD) += ddr.o

34
board/exmeritus/hww1u1a/ddr.c
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/*
* Copyright 2009-2010 eXMeritus, A Boeing Company
* Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
/*
* We only support one DIMM, so according to the P2020 docs we should
* set the options as follows:
*/
popts->cs_local_opts[0].odt_rd_cfg = 0;
popts->cs_local_opts[0].odt_wr_cfg = 4;
popts->cs_local_opts[1].odt_rd_cfg = 0;
popts->cs_local_opts[1].odt_wr_cfg = 0;
popts->half_strength_driver_enable = 0;
/* Manually configured for our static clock rate */
popts->clk_adjust = 4;
popts->cpo_override = 4;
popts->write_data_delay = 2;
popts->twot_en = 0;
}

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board/exmeritus/hww1u1a/gpios.h
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/*
* Copyright 2010 eXMeritus, A Boeing Company
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/mpc85xx_gpio.h>
/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */
#define GPIO_CPU_ID (1UL << (31 - 8))
#define GPIO_BLUE_LED (1UL << (31 - 9))
#define GPIO_DIMM_RESET (1UL << (31 - 10))
#define GPIO_USB_RESET (1UL << (31 - 11))
#define GPIO_UNUSED_12 (1UL << (31 - 12))
#define GPIO_GETH0_RESET (1UL << (31 - 13))
#define GPIO_RS422_RE (1UL << (31 - 14))
#define GPIO_RS422_DE (1UL << (31 - 15))
#define IRQ_I2CINT (1UL << (31 - 20))
#define IRQ_FANINT (1UL << (31 - 21))
#define IRQ_DIMM_EVENT (1UL << (31 - 22))
#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET)
/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
#define GPIO_CPUA_UNUSED_0 (1UL << (31 - 0))
#define GPIO_CPUA_CPU_READY (1UL << (31 - 1))
#define GPIO_CPUA_DEBUG_LED2 (1UL << (31 - 2))
#define GPIO_CPUA_DEBUG_LED1 (1UL << (31 - 3))
#define GPIO_CPUA_TDIS2B (1UL << (31 - 4)) /* MAC 2 TX B */
#define GPIO_CPUA_TDIS2A (1UL << (31 - 5)) /* MAC 2 TX A */
#define GPIO_CPUA_TDIS1B (1UL << (31 - 6)) /* MAC 1 TX B */
#define GPIO_CPUA_TDIS1A (1UL << (31 - 7)) /* MAC 1 TX A */
#define IRQ_CPUA_UNUSED_0 (1UL << (31 - 16))
#define IRQ_CPUA_UNUSED_1 (1UL << (31 - 17))
#define IRQ_CPUA_UNUSED_2 (1UL << (31 - 18))
#define IRQ_CPUA_UNUSED_3 (1UL << (31 - 19))
/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
#define GPIO_CPUB_RMUX_SEL1B (1UL << (31 - 0))
#define GPIO_CPUB_RMUX_SEL0B (1UL << (31 - 1))
#define GPIO_CPUB_RMUX_SEL1A (1UL << (31 - 2))
#define GPIO_CPUB_RMUX_SEL0A (1UL << (31 - 3))
#define GPIO_CPUB_UNUSED_4 (1UL << (31 - 4))
#define GPIO_CPUB_CPU_READY (1UL << (31 - 5))
#define GPIO_CPUB_DEBUG_LED2 (1UL << (31 - 6))
#define GPIO_CPUB_DEBUG_LED1 (1UL << (31 - 7))
#define IRQ_CPUB_SD_1A (1UL << (31 - 16))
#define IRQ_CPUB_SD_2B (1UL << (31 - 17))
#define IRQ_CPUB_SD_2A (1UL << (31 - 18))
#define IRQ_CPUB_SD_1B (1UL << (31 - 19))
/* If it isn't CPU A then it's CPU B */
static inline unsigned int hww1u1a_is_cpu_a(void)
{
return !mpc85xx_gpio_get(GPIO_CPU_ID);
}

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board/exmeritus/hww1u1a/hww1u1a.c
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/*
* Copyright 2009-2011 eXMeritus, A Boeing Company
* Copyright 2007-2009 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <linux/ctype.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <asm/fsl_law.h>
#include <netdev.h>
#include <malloc.h>
#include <i2c.h>
#include <pca953x.h>
#include "gpios.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
unsigned int gpio_high = 0;
unsigned int gpio_low = 0;
unsigned int gpio_in = 0;
unsigned int i;
struct ccsr_ddr __iomem *ddr;
puts("Board: HWW-1U-1A ");
/*
* First just figure out which CPU we're on, then use that to
* configure the lists of other GPIOs to be programmed.
*/
mpc85xx_gpio_set_in(GPIO_CPU_ID);
if (hww1u1a_is_cpu_a()) {
puts("CPU A\n");
/* We want to turn on some LEDs */
gpio_high |= GPIO_CPUA_CPU_READY;
gpio_low |= GPIO_CPUA_DEBUG_LED1;
gpio_low |= GPIO_CPUA_DEBUG_LED2;
/* Disable the unused transmitters */
gpio_low |= GPIO_CPUA_TDIS1A;
gpio_high |= GPIO_CPUA_TDIS1B;
gpio_low |= GPIO_CPUA_TDIS2A;
gpio_high |= GPIO_CPUA_TDIS2B;
} else {
puts("CPU B\n");
/* We want to turn on some LEDs */
gpio_high |= GPIO_CPUB_CPU_READY;
gpio_low |= GPIO_CPUB_DEBUG_LED1;
gpio_low |= GPIO_CPUB_DEBUG_LED2;
/* Enable the appropriate receivers */
gpio_high |= GPIO_CPUB_RMUX_SEL0A;
gpio_high |= GPIO_CPUB_RMUX_SEL0B;
gpio_low |= GPIO_CPUB_RMUX_SEL1A;
gpio_low |= GPIO_CPUB_RMUX_SEL1B;
}
/* These GPIOs are common */
gpio_in |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT;
gpio_low |= GPIO_RS422_RE;
gpio_high |= GPIO_RS422_DE;
/* Ok, now go ahead and program all of those in one go */
mpc85xx_gpio_set(gpio_high|gpio_low|gpio_in,
gpio_high|gpio_low,
gpio_high);
/*
* If things have been taken out of reset early (for example, by one
* of the BDI3000 debuggers), then we need to put them back in reset
* and delay a while before we continue.
*/
if (mpc85xx_gpio_get(GPIO_RESETS)) {
ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
puts("Debugger detected... extra device reset enabled!\n");
/* Put stuff into reset and disable the DDR controller */
mpc85xx_gpio_set_low(GPIO_RESETS);
out_be32(&ddr->sdram_cfg, 0x00000000);
puts(" Waiting 1 sec for reset...");
for (i = 0; i < 10; i++) {
udelay(100000);
puts(".");
}
puts("\n");
}
/* Now bring everything back out of reset again */
mpc85xx_gpio_set_high(GPIO_RESETS);
return 0;
}
/*
* This little shell function just returns whether or not it's CPU A.
* It can be used to select the right device-tree when booting, etc.
*/
int do_hww1u1a_test_cpu_a(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
if (argc > 1)
cmd_usage(cmdtp);
if (hww1u1a_is_cpu_a())
return 0;
else
return 1;
}
U_BOOT_CMD(
test_cpu_a, 1, 0, do_hww1u1a_test_cpu_a,
"Test if this is CPU A (versus B) on the eXMeritus HWW-1U-1A board",
""
);
/* Create a prompt-like string: "uboot@HOSTNAME% " */
#define PROMPT_PREFIX "uboot@exm"
#define PROMPT_SUFFIX "% "
/* This function returns a PS1 prompt based on the serial number */
static char *hww1u1a_prompt;
const char *hww1u1a_get_ps1(void)
{
unsigned long len, i, j;
const char *serialnr;
/* If our prompt was already set, just use that */
if (hww1u1a_prompt)
return hww1u1a_prompt;
/* Use our serial number if present, otherwise a default */
serialnr = getenv("serial#");
if (!serialnr || !serialnr[0])
serialnr = "999999-X";
/*
* We will turn the serial number into a hostname by:
* (A) Delete all non-alphanumerics.
* (B) Lowercase all letters.
* (C) Prefix "exm".
* (D) Suffix "a" for CPU A and "b" for CPU B.
*/
for (i = 0, len = 0; serialnr[i]; i++) {
if (isalnum(serialnr[i]))
len++;
}
len += sizeof(PROMPT_PREFIX PROMPT_SUFFIX) + 1; /* Includes NUL */
hww1u1a_prompt = malloc(len);
if (!hww1u1a_prompt)
return PROMPT_PREFIX "UNKNOWN(ENOMEM)" PROMPT_SUFFIX;
/* Now actually fill it in */
i = 0;
/* Handle the prefix */
for (j = 0; j < sizeof(PROMPT_PREFIX) - 1; j++)
hww1u1a_prompt[i++] = PROMPT_PREFIX[j];
/* Now the serial# part of the hostname */
for (j = 0; serialnr[j]; j++)
if (isalnum(serialnr[j]))
hww1u1a_prompt[i++] = tolower(serialnr[j]);
/* Now the CPU id ("a" or "b") */
hww1u1a_prompt[i++] = hww1u1a_is_cpu_a() ? 'a' : 'b';
/* Finally the suffix */
for (j = 0; j < sizeof(PROMPT_SUFFIX); j++)
hww1u1a_prompt[i++] = PROMPT_SUFFIX[j];
/* This should all have added up, but just in case */
hww1u1a_prompt[len - 1] = '\0';
/* Now we're done */
return hww1u1a_prompt;
}
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap bootflash region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for FLASH */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
return 0;
}
int board_eth_init(bd_t *bis)
{
struct tsec_info_struct tsec_info[4];
struct fsl_pq_mdio_info mdio_info;
SET_STD_TSEC_INFO(tsec_info[0], 1);
SET_STD_TSEC_INFO(tsec_info[1], 2);
SET_STD_TSEC_INFO(tsec_info[2], 3);
if (hww1u1a_is_cpu_a())
tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUA;
else
tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUB;
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, 3);
return pci_eth_init(bis);
}
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
FT_FSL_PCI_SETUP;
}

18
board/exmeritus/hww1u1a/law.c
View File

@ -1,18 +0,0 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

90
board/exmeritus/hww1u1a/tlb.c
View File

@ -1,90 +0,0 @@
/*
* Copyright 2009-2010 eXMeritus, A Boeing Company
* Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 0 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Boot page */
SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR,
CONFIG_BPTR_VIRT_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR,
CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
/*
* W**G* - FLASH (Will be *I*G* after relocation to RAM)
*
* This maps both SPI FLASH chips (128MByte per chip)
*/
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* *I*G* - PCI memory
*
* We have 1.5GB total PCI-E memory space to map and we want to use
* the minimum possible number of TLB entries. Since Book-E TLB
* entries are sized in powers of 4, we use 1GB + 256MB + 256MB.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT,
CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/*
* *I*G* - PCI I/O
*
* This one entry covers all 3 64k PCI-E I/O windows
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT,
CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

4
board/freescale/mpc5121ads/README
View File

@ -1,7 +1,7 @@
To configure for the current (Rev 3.x) ADS5121
make ads5121_config
make mpc5121ads_config
This will automatically include PCI, the Real Time CLock, add backup flash
ability and set the correct frequency and memory configuration.
To configure for the older Rev 2 ADS5121 type (this will not have PCI)
make ads5121_rev2_config
make mpc5121ads_rev2_config

9
board/hymod/Kconfig
View File

@ -1,9 +0,0 @@
if TARGET_HYMOD
config SYS_BOARD
default "hymod"
config SYS_CONFIG_NAME
default "hymod"
endif

6
board/hymod/MAINTAINERS
View File

@ -1,6 +0,0 @@
HYMOD BOARD
M: Murray Jensen <Murray.Jensen@csiro.au>
S: Maintained
F: board/hymod/
F: include/configs/hymod.h
F: configs/hymod_defconfig

8
board/hymod/Makefile
View File

@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = hymod.o flash.o bsp.o eeprom.o fetch.o input.o env.o

387
board/hymod/bsp.c
View File

@ -1,387 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*
* hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01
*/
#include <common.h>
#include <command.h>
#include <net.h>
#include <asm/iopin_8260.h>
DECLARE_GLOBAL_DATA_PTR;
/*-----------------------------------------------------------------------
* Board Special Commands: FPGA load/store, EEPROM erase
*/
#if defined(CONFIG_CMD_BSP)
#define LOAD_SUCCESS 0
#define LOAD_FAIL_NOCONF 1
#define LOAD_FAIL_NOINIT 2
#define LOAD_FAIL_NODONE 3
#define STORE_SUCCESS 0
/*
* Programming the Hymod FPGAs
*
* The 8260 io port config table is set up so that the INIT pin is
* held Low (Open Drain output 0) - this will delay the automatic
* Power-On config until INIT is released (by making it an input).
*
* If the FPGA has been programmed before, then the assertion of PROGRAM
* will initiate configuration (i.e. it begins clearing the RAM).
*
* When the FPGA is ready to receive configuration data (either after
* releasing INIT after Power-On, or after asserting PROGRAM), it will
* pull INIT high.
*
* Notes from Paul Dunn:
*
* 1. program pin should be forced low for >= 300ns
* (about 20 bus clock cycles minimum).
*
* 2. then wait for init to go high, which signals
* that the FPGA has cleared its internal memory
* and is ready to load
*
* 3. perform load writes of entire config file
*
* 4. wait for done to go high, which should be
* within a few bus clock cycles. If done has not
* gone high after reasonable period, then load
* has not worked (wait several ms?)
*/
int
fpga_load(int mezz, const uchar *addr, ulong size)
{
hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
xlx_info_t *fp;
xlx_iopins_t *fpgaio;
volatile uchar *fpgabase;
volatile uint cnt;
const uchar *eaddr = addr + size;
int result;
if (mezz)
fp = &cp->mezz.xlx[0];
else
fp = &cp->main.xlx[0];
if (!fp->mmap.prog.exists)
return (LOAD_FAIL_NOCONF);
fpgabase = (uchar *)fp->mmap.prog.base;
fpgaio = &fp->iopins;
/* set enable HIGH if required */
if (fpgaio->enable_pin.flag)
iopin_set_high (&fpgaio->enable_pin);
/* ensure INIT is released (set it to be an input) */
iopin_set_in (&fpgaio->init_pin);
/* toggle PROG Low then High (will already be Low after Power-On) */
iopin_set_low (&fpgaio->prog_pin);
udelay (1); /* minimum 300ns - 1usec should do it */
iopin_set_high (&fpgaio->prog_pin);
/* wait for INIT High */
cnt = 0;
while (!iopin_is_high (&fpgaio->init_pin))
if (++cnt == 10000000) {
result = LOAD_FAIL_NOINIT;
goto done;
}
/* write configuration data */
while (addr < eaddr)
*fpgabase = *addr++;
/* wait for DONE High */
cnt = 0;
while (!iopin_is_high (&fpgaio->done_pin))
if (++cnt == 100000000) {
result = LOAD_FAIL_NODONE;
goto done;
}
/* success */
result = LOAD_SUCCESS;
done:
if (fpgaio->enable_pin.flag)
iopin_set_low (&fpgaio->enable_pin);
return (result);
}
/* ------------------------------------------------------------------------- */
int
do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
uchar *addr, *save_addr;
ulong size;
int mezz, arg, result;
switch (argc) {
case 0:
case 1:
break;
case 2:
if (strcmp (argv[1], "info") == 0) {
printf ("\nHymod FPGA Info...\n");
printf ("\t\t\t\tAddress\t\tSize\n");
printf ("\tMain Configuration:\t0x%08x\t%d\n",
FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE);
printf ("\tMain Register:\t\t0x%08x\t%d\n",
FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE);
printf ("\tMain Port:\t\t0x%08x\t%d\n",
FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE);
printf ("\tMezz Configuration:\t0x%08x\t%d\n",
FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE);
return 0;
}
break;
case 3:
if (strcmp (argv[1], "store") == 0) {
addr = (uchar *) simple_strtoul (argv[2], NULL, 16);
save_addr = addr;
#if 0
/* fpga readback unimplemented */
while (more readback data)
*addr++ = *fpga;
result = error ? STORE_FAIL_XXX : STORE_SUCCESS;
#else
result = STORE_SUCCESS;
#endif
if (result == STORE_SUCCESS) {
printf ("SUCCEEDED (%d bytes)\n",
addr - save_addr);
return 0;
} else
printf ("FAILED (%d bytes)\n",
addr - save_addr);
return 1;
}
break;
case 4:
if (strcmp (argv[1], "tftp") == 0) {
copy_filename (BootFile, argv[2], sizeof (BootFile));
load_addr = simple_strtoul (argv[3], NULL, 16);
NetBootFileXferSize = 0;
if (NetLoop(TFTPGET) <= 0) {
printf ("tftp transfer failed - aborting "
"fgpa load\n");
return 1;
}
if (NetBootFileXferSize == 0) {
printf ("can't determine file size - "
"aborting fpga load\n");
return 1;
}
printf ("File transfer succeeded - "
"beginning fpga load...");
result = fpga_load (0, (uchar *) load_addr,
NetBootFileXferSize);
if (result == LOAD_SUCCESS) {
printf ("SUCCEEDED\n");
return 0;
} else if (result == LOAD_FAIL_NOCONF)
printf ("FAILED (no CONF)\n");
else if (result == LOAD_FAIL_NOINIT)
printf ("FAILED (no INIT)\n");
else
printf ("FAILED (no DONE)\n");
return 1;
}
/* fall through ... */
case 5:
if (strcmp (argv[1], "load") == 0) {
if (argc == 5) {
if (strcmp (argv[2], "main") == 0)
mezz = 0;
else if (strcmp (argv[2], "mezz") == 0)
mezz = 1;
else {
printf ("FPGA type must be either "
"`main' or `mezz'\n");
return 1;
}
arg = 3;
} else {
mezz = 0;
arg = 2;
}
addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16);
size = (ulong) simple_strtoul (argv[arg], NULL, 16);
result = fpga_load (mezz, addr, size);
if (result == LOAD_SUCCESS) {
printf ("SUCCEEDED\n");
return 0;
} else if (result == LOAD_FAIL_NOCONF)
printf ("FAILED (no CONF)\n");
else if (result == LOAD_FAIL_NOINIT)
printf ("FAILED (no INIT)\n");
else
printf ("FAILED (no DONE)\n");
return 1;
}
break;
default:
break;
}
return cmd_usage(cmdtp);
}
U_BOOT_CMD(
fpga, 6, 1, do_fpga,
"FPGA sub-system",
"load [type] addr size\n"
" - write the configuration data at memory address `addr',\n"
" size `size' bytes, into the FPGA of type `type' (either\n"
" `main' or `mezz', default `main'). e.g.\n"
" `fpga load 100000 7d8f'\n"
" loads the main FPGA with config data at address 100000\n"
" HEX, size 7d8f HEX (32143 DEC) bytes\n"
"fpga tftp file addr\n"
" - transfers `file' from the tftp server into memory at\n"
" address `addr', then writes the entire file contents\n"
" into the main FPGA\n"
"fpga store addr\n"
" - read configuration data from the main FPGA (the mezz\n"
" FPGA is write-only), into address `addr'. There must be\n"
" enough memory available at `addr' to hold all the config\n"
" data - the size of which is determined by VC:???\n"
"fpga info\n"
" - print information about the Hymod FPGA, namely the\n"
" memory addresses at which the four FPGA local bus\n"
" address spaces appear in the physical address space"
);
/* ------------------------------------------------------------------------- */
int
do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
uchar data[HYMOD_EEPROM_SIZE];
uint addr = CONFIG_SYS_I2C_EEPROM_ADDR;
switch (argc) {
case 1:
addr |= HYMOD_EEOFF_MAIN;
break;
case 2:
if (strcmp (argv[1], "main") == 0) {
addr |= HYMOD_EEOFF_MAIN;
break;
}
if (strcmp (argv[1], "mezz") == 0) {
addr |= HYMOD_EEOFF_MEZZ;
break;
}
/* fall through ... */
default:
return cmd_usage(cmdtp);
}
memset (data, 0, HYMOD_EEPROM_SIZE);
eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE);
return 0;
}
U_BOOT_CMD(
eeclear, 1, 0, do_eecl,
"Clear the eeprom on a Hymod board",
"[type]\n"
" - write zeroes into the EEPROM on the board of type `type'\n"
" (`type' is either `main' or `mezz' - default `main')\n"
" Note: the EEPROM write enable jumper must be installed"
);
/* ------------------------------------------------------------------------- */
int
do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if 0
int rc;
#endif
#ifdef CONFIG_ETHER_LOOPBACK_TEST
extern void eth_loopback_test (void);
#endif /* CONFIG_ETHER_LOOPBACK_TEST */
printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n");
#if 0
/* Load FPGA with test program */
printf ("Loading test FPGA program ...");
rc = fpga_load (0, test_bitfile, sizeof (test_bitfile));
switch (rc) {
case LOAD_SUCCESS:
printf (" SUCCEEDED\n");
break;
case LOAD_FAIL_NOCONF:
printf (" FAILED (no configuration space defined)\n");
return 1;
case LOAD_FAIL_NOINIT:
printf (" FAILED (timeout - no INIT signal seen)\n");
return 1;
case LOAD_FAIL_NODONE:
printf (" FAILED (timeout - no DONE signal seen)\n");
return 1;
default:
printf (" FAILED (unknown return code from fpga_load\n");
return 1;
}
/* run Local Bus <=> Xilinx tests */
/* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */
/* run SDRAM test */
#endif
#ifdef CONFIG_ETHER_LOOPBACK_TEST
/* run Ethernet test */
eth_loopback_test ();
#endif /* CONFIG_ETHER_LOOPBACK_TEST */
return 0;
}
#endif

14
board/hymod/config.mk
View File

@ -1,14 +0,0 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
#
# HYMOD boards
#
PLATFORM_CPPFLAGS += -I$(srctree)
OBJCOPYFLAGS = --remove-section=.ppcenv

678
board/hymod/eeprom.c
View File

@ -1,678 +0,0 @@
/*
* (C) Copyright 2001
* Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc8260.h>
/* imports from fetch.c */
extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
/* imports from input.c */
extern int hymod_get_serno (const char *);
/* this is relative to the root of the server's tftp directory */
static char *def_bddb_cfgdir = "/hymod/bddb";
static int
hymod_eeprom_load (int which, hymod_eeprom_t *ep)
{
unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
unsigned offset = 0;
uchar data[HYMOD_EEPROM_MAXLEN], *dp, *edp;
hymod_eehdr_t hdr;
ulong len, crc;
memset (ep, 0, sizeof *ep);
eeprom_read (dev_addr, offset, (uchar *)&hdr, sizeof (hdr));
offset += sizeof (hdr);
if (hdr.id != HYMOD_EEPROM_ID || hdr.ver > HYMOD_EEPROM_VER ||
(len = hdr.len) > HYMOD_EEPROM_MAXLEN)
return (0);
eeprom_read (dev_addr, offset, data, len);
offset += len;
eeprom_read (dev_addr, offset, (uchar *)&crc, sizeof (ulong));
offset += sizeof (ulong);
if (crc32 (crc32 (0, (uchar *)&hdr, sizeof hdr), data, len) != crc)
return (0);
ep->ver = hdr.ver;
dp = data; edp = dp + len;
for (;;) {
ulong rtyp;
uchar rlen, *rdat;
rtyp = *dp++;
if ((rtyp & 0x80) == 0)
rlen = *dp++;
else {
uchar islarge = rtyp & 0x40;
rtyp = ((rtyp & 0x3f) << 8) | *dp++;
if (islarge) {
rtyp = (rtyp << 8) | *dp++;
rtyp = (rtyp << 8) | *dp++;
}
rlen = *dp++;
rlen = (rlen << 8) | *dp++;
if (islarge) {
rlen = (rlen << 8) | *dp++;
rlen = (rlen << 8) | *dp++;
}
}
if (rtyp == 0)
break;
rdat = dp;
dp += rlen;
if (dp > edp) /* error? */
break;
switch (rtyp) {
case HYMOD_EEREC_SERNO: /* serial number */
if (rlen == sizeof (ulong))
ep->serno = \
((ulong)rdat[0] << 24) | \
((ulong)rdat[1] << 16) | \
((ulong)rdat[2] << 8) | \
(ulong)rdat[3];
break;
case HYMOD_EEREC_DATE: /* date */
if (rlen == sizeof (hymod_date_t)) {
ep->date.year = ((ushort)rdat[0] << 8) | \
(ushort)rdat[1];
ep->date.month = rdat[2];
ep->date.day = rdat[3];
}
break;
case HYMOD_EEREC_BATCH: /* batch */
if (rlen <= HYMOD_MAX_BATCH)
memcpy (ep->batch, rdat, ep->batchlen = rlen);
break;
case HYMOD_EEREC_TYPE: /* board type */
if (rlen == 1)
ep->bdtype = *rdat;
break;
case HYMOD_EEREC_REV: /* board revision */
if (rlen == 1)
ep->bdrev = *rdat;
break;
case HYMOD_EEREC_SDRAM: /* sdram size(s) */
if (rlen > 0 && rlen <= HYMOD_MAX_SDRAM) {
int i;
for (i = 0; i < rlen; i++)
ep->sdramsz[i] = rdat[i];
ep->nsdram = rlen;
}
break;
case HYMOD_EEREC_FLASH: /* flash size(s) */
if (rlen > 0 && rlen <= HYMOD_MAX_FLASH) {
int i;
for (i = 0; i < rlen; i++)
ep->flashsz[i] = rdat[i];
ep->nflash = rlen;
}
break;
case HYMOD_EEREC_ZBT: /* zbt ram size(s) */
if (rlen > 0 && rlen <= HYMOD_MAX_ZBT) {
int i;
for (i = 0; i < rlen; i++)
ep->zbtsz[i] = rdat[i];
ep->nzbt = rlen;
}
break;
case HYMOD_EEREC_XLXTYP: /* xilinx fpga type(s) */
if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
int i;
for (i = 0; i < rlen; i++)
ep->xlx[i].type = rdat[i];
ep->nxlx = rlen;
}
break;
case HYMOD_EEREC_XLXSPD: /* xilinx fpga speed(s) */
if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
int i;
for (i = 0; i < rlen; i++)
ep->xlx[i].speed = rdat[i];
}
break;
case HYMOD_EEREC_XLXTMP: /* xilinx fpga temperature(s) */
if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
int i;
for (i = 0; i < rlen; i++)
ep->xlx[i].temp = rdat[i];
}
break;
case HYMOD_EEREC_XLXGRD: /* xilinx fpga grade(s) */
if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
int i;
for (i = 0; i < rlen; i++)
ep->xlx[i].grade = rdat[i];
}
break;
case HYMOD_EEREC_CPUTYP: /* CPU type */
if (rlen == 1)
ep->mpc.type = *rdat;
break;
case HYMOD_EEREC_CPUSPD: /* CPU speed */
if (rlen == 1)
ep->mpc.cpuspd = *rdat;
break;
case HYMOD_EEREC_CPMSPD: /* CPM speed */
if (rlen == 1)
ep->mpc.cpmspd = *rdat;
break;
case HYMOD_EEREC_BUSSPD: /* bus speed */
if (rlen == 1)
ep->mpc.busspd = *rdat;
break;
case HYMOD_EEREC_HSTYPE: /* hs-serial chip type */
if (rlen == 1)
ep->hss.type = *rdat;
break;
case HYMOD_EEREC_HSCHIN: /* num hs-serial input chans */
if (rlen == 1)
ep->hss.nchin = *rdat;
break;
case HYMOD_EEREC_HSCHOUT: /* num hs-serial output chans */
if (rlen == 1)
ep->hss.nchout = *rdat;
break;
default: /* ignore */
break;
}
}
return (1);
}
/* maps an ascii "name=value" into a binary eeprom data record */
typedef
struct _eerec_map {
char *name;
uint type;
uchar *(*handler) \
(struct _eerec_map *, uchar *, uchar *, uchar *);
uint length;
uint maxlen;
}
eerec_map_t;
static uchar *
uint_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
{
char *eval;
ulong lval;
lval = simple_strtol ((char *)val, &eval, 10);
if ((uchar *)eval == val || *eval != '\0') {
printf ("%s rec (%s) is not a valid uint\n", rp->name, val);
return (NULL);
}
if (dp + 2 + rp->length > edp) {
printf ("can't fit %s rec into eeprom\n", rp->name);
return (NULL);
}
*dp++ = rp->type;
*dp++ = rp->length;
switch (rp->length) {
case 1:
if (lval >= 256) {
printf ("%s rec value (%lu) out of range (0-255)\n",
rp->name, lval);
return (NULL);
}
*dp++ = lval;
break;
case 2:
if (lval >= 65536) {
printf ("%s rec value (%lu) out of range (0-65535)\n",
rp->name, lval);
return (NULL);
}
*dp++ = lval >> 8;
*dp++ = lval;
break;
case 4:
*dp++ = lval >> 24;
*dp++ = lval >> 16;
*dp++ = lval >> 8;
*dp++ = lval;
break;
default:
printf ("huh? rp->length not 1, 2 or 4! (%d)\n", rp->length);
return (NULL);
}
return (dp);
}
static uchar *
date_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
{
hymod_date_t date;
char *p = (char *)val;
char *ep;
ulong lval;
lval = simple_strtol (p, &ep, 10);
if (ep == p || *ep++ != '-') {
bad_date:
printf ("%s rec (%s) is not a valid date\n", rp->name, val);
return (NULL);
}
if (lval >= 65536)
goto bad_date;
date.year = lval;
lval = simple_strtol (p = ep, &ep, 10);
if (ep == p || *ep++ != '-' || lval == 0 || lval > 12)
goto bad_date;
date.month = lval;
lval = simple_strtol (p = ep, &ep, 10);
if (ep == p || *ep != '\0' || lval == 0 || lval > 31)
goto bad_date;
date.day = lval;
if (dp + 2 + rp->length > edp) {
printf ("can't fit %s rec into eeprom\n", rp->name);
return (NULL);
}
*dp++ = rp->type;
*dp++ = rp->length;
*dp++ = date.year >> 8;
*dp++ = date.year;
*dp++ = date.month;
*dp++ = date.day;
return (dp);
}
static uchar *
string_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
{
uint len;
if ((len = strlen ((char *)val)) > rp->maxlen) {
printf ("%s rec (%s) string is too long (%d>%d)\n",
rp->name, val, len, rp->maxlen);
return (NULL);
}
if (dp + 2 + len > edp) {
printf ("can't fit %s rec into eeprom\n", rp->name);
return (NULL);
}
*dp++ = rp->type;
*dp++ = len;
memcpy (dp, val, len);
dp += len;
return (dp);
}
static uchar *
bytes_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
{
uchar bytes[HYMOD_MAX_BYTES], nbytes, *p;
char *ep;
for (nbytes = 0, p = val; *p != '\0'; p = (uchar *)ep) {
ulong lval;
lval = simple_strtol ((char *)p, &ep, 10);
if ((uchar *)ep == p || (*ep != '\0' && *ep != ',') || \
lval >= 256) {
printf ("%s rec (%s) byte array has invalid uint\n",
rp->name, val);
return (NULL);
}
if (nbytes >= HYMOD_MAX_BYTES) {
printf ("%s rec (%s) byte array too long\n",
rp->name, val);
return (NULL);
}
bytes[nbytes++] = lval;
if (*ep != '\0')
ep++;
}
if (dp + 2 + nbytes > edp) {
printf ("can't fit %s rec into eeprom\n", rp->name);
return (NULL);
}
*dp++ = rp->type;
*dp++ = nbytes;
memcpy (dp, bytes, nbytes);
dp += nbytes;
return (dp);
}
static eerec_map_t eerec_map[] = {
/* name type handler len max */
{ "serno", HYMOD_EEREC_SERNO, uint_handler, 4, 0 },
{ "date", HYMOD_EEREC_DATE, date_handler, 4, 0 },
{ "batch", HYMOD_EEREC_BATCH, string_handler, 0, HYMOD_MAX_BATCH },
{ "type", HYMOD_EEREC_TYPE, uint_handler, 1, 0 },
{ "rev", HYMOD_EEREC_REV, uint_handler, 1, 0 },
{ "sdram", HYMOD_EEREC_SDRAM, bytes_handler, 0, HYMOD_MAX_SDRAM },
{ "flash", HYMOD_EEREC_FLASH, bytes_handler, 0, HYMOD_MAX_FLASH },
{ "zbt", HYMOD_EEREC_ZBT, bytes_handler, 0, HYMOD_MAX_ZBT },
{ "xlxtyp", HYMOD_EEREC_XLXTYP, bytes_handler, 0, HYMOD_MAX_XLX },
{ "xlxspd", HYMOD_EEREC_XLXSPD, bytes_handler, 0, HYMOD_MAX_XLX },
{ "xlxtmp", HYMOD_EEREC_XLXTMP, bytes_handler, 0, HYMOD_MAX_XLX },
{ "xlxgrd", HYMOD_EEREC_XLXGRD, bytes_handler, 0, HYMOD_MAX_XLX },
{ "cputyp", HYMOD_EEREC_CPUTYP, uint_handler, 1, 0 },
{ "cpuspd", HYMOD_EEREC_CPUSPD, uint_handler, 1, 0 },
{ "cpmspd", HYMOD_EEREC_CPMSPD, uint_handler, 1, 0 },
{ "busspd", HYMOD_EEREC_BUSSPD, uint_handler, 1, 0 },
{ "hstype", HYMOD_EEREC_HSTYPE, uint_handler, 1, 0 },
{ "hschin", HYMOD_EEREC_HSCHIN, uint_handler, 1, 0 },
{ "hschout", HYMOD_EEREC_HSCHOUT, uint_handler, 1, 0 },
};
static int neerecs = sizeof eerec_map / sizeof eerec_map[0];
static uchar data[HYMOD_EEPROM_SIZE], *sdp, *dp, *edp;
static int
eerec_callback (uchar *name, uchar *val)
{
eerec_map_t *rp;
for (rp = eerec_map; rp < &eerec_map[neerecs]; rp++)
if (strcmp ((char *)name, rp->name) == 0)
break;
if (rp >= &eerec_map[neerecs])
return (0);
if ((dp = (*rp->handler) (rp, val, dp, edp)) == NULL)
return (0);
return (1);
}
static int
hymod_eeprom_fetch(int which, char *filename, ulong addr)
{
unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
hymod_eehdr_t *hp = (hymod_eehdr_t *)&data[0];
ulong crc;
memset (hp, 0, sizeof *hp);
hp->id = HYMOD_EEPROM_ID;
hp->ver = HYMOD_EEPROM_VER;
dp = sdp = (uchar *)(hp + 1);
edp = dp + HYMOD_EEPROM_MAXLEN;
if (fetch_and_parse (filename, addr, eerec_callback) == 0)
return (0);
hp->len = dp - sdp;
crc = crc32 (0, data, dp - data);
memcpy (dp, &crc, sizeof (ulong));
dp += sizeof (ulong);
eeprom_write (dev_addr, 0, data, dp - data);
return (1);
}
static char *type_vals[] = {
"NONE", "IO", "CLP", "DSP", "INPUT", "ALT-INPUT", "DISPLAY"
};
static char *xlxtyp_vals[] = {
"NONE", "XCV300E", "XCV400E", "XCV600E"
};
static char *xlxspd_vals[] = {
"NONE", "6", "7", "8"
};
static char *xlxtmp_vals[] = {
"NONE", "COM", "IND"
};
static char *xlxgrd_vals[] = {
"NONE", "NORMAL", "ENGSAMP"
};
static char *cputyp_vals[] = {
"NONE", "MPC8260"
};
static char *clk_vals[] = {
"NONE", "33", "66", "100", "133", "166", "200"
};
static char *hstype_vals[] = {
"NONE", "AMCC-S2064A"
};
static void
print_mem (char *l, char *s, uchar n, uchar a[])
{
if (n > 0) {
if (n == 1)
printf ("%s%dMB %s", s, 1 << (a[0] - 20), l);
else {
ulong t = 0;
int i;
for (i = 0; i < n; i++)
t += 1 << (a[i] - 20);
printf ("%s%luMB %s (%d banks:", s, t, l, n);
for (i = 0; i < n; i++)
printf ("%dMB%s",
1 << (a[i] - 20),
(i == n - 1) ? ")" : ",");
}
}
else
printf ("%sNO %s", s, l);
}
void
hymod_eeprom_print (hymod_eeprom_t *ep)
{
int i;
printf (" Hymod %s board, rev %03d\n",
type_vals[ep->bdtype], ep->bdrev);
printf (" serial #: %010lu, date %04d-%02d-%02d",
ep->serno, ep->date.year, ep->date.month, ep->date.day);
if (ep->batchlen > 0)
printf (", batch \"%.*s\"", ep->batchlen, ep->batch);
puts ("\n");
switch (ep->bdtype) {
case HYMOD_BDTYPE_IO:
case HYMOD_BDTYPE_CLP:
case HYMOD_BDTYPE_DSP:
printf (" Motorola %s CPU, speeds: %s/%s/%s",
cputyp_vals[ep->mpc.type], clk_vals[ep->mpc.cpuspd],
clk_vals[ep->mpc.cpmspd], clk_vals[ep->mpc.busspd]);
print_mem ("SDRAM", ", ", ep->nsdram, ep->sdramsz);
print_mem ("FLASH", ", ", ep->nflash, ep->flashsz);
puts ("\n");
print_mem ("ZBT", " ", ep->nzbt, ep->zbtsz);
if (ep->nxlx > 0) {
hymod_xlx_t *xp;
if (ep->nxlx == 1) {
xp = &ep->xlx[0];
printf (", Xilinx %s FPGA (%s/%s/%s)",
xlxtyp_vals[xp->type],
xlxspd_vals[xp->speed],
xlxtmp_vals[xp->temp],
xlxgrd_vals[xp->grade]);
}
else {
printf (", %d Xilinx FPGAs (", ep->nxlx);
for (i = 0; i < ep->nxlx; i++) {
xp = &ep->xlx[i];
printf ("%s[%s/%s/%s]%s",
xlxtyp_vals[xp->type],
xlxspd_vals[xp->speed],
xlxtmp_vals[xp->temp],
xlxgrd_vals[xp->grade],
(i == ep->nxlx - 1) ? ")" : ", ");
}
}
}
else
puts(", NO FPGAs");
puts ("\n");
if (ep->hss.type > 0)
printf (" High Speed Serial: "
"%s, %d input%s, %d output%s\n",
hstype_vals[ep->hss.type],
ep->hss.nchin,
(ep->hss.nchin == 1 ? "" : "s"),
ep->hss.nchout,
(ep->hss.nchout == 1 ? "" : "s"));
break;
case HYMOD_BDTYPE_INPUT:
case HYMOD_BDTYPE_ALTINPUT:
case HYMOD_BDTYPE_DISPLAY:
break;
default:
/* crap! */
printf (" UNKNOWN BOARD TYPE: %d\n", ep->bdtype);
break;
}
}
int
hymod_eeprom_read (int which, hymod_eeprom_t *ep)
{
char *label = which ? "mezzanine" : "main";
unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
char filename[50], prompt[50], *dir;
int serno, count = 0, rc;
rc = eeprom_probe (dev_addr, 0);
if (rc > 0) {
printf ("*** probe for eeprom failed with code %d\n", rc);
return (0);
}
if (rc < 0)
return (rc);
sprintf (prompt, "Enter %s board serial number: ", label);
if ((dir = getenv ("bddb_cfgdir")) == NULL)
dir = def_bddb_cfgdir;
for (;;) {
int rc;
if (hymod_eeprom_load (which, ep))
return (1);
printf ("*** %s board EEPROM contents are %sinvalid\n",
label, count == 0 ? "" : "STILL ");
puts ("*** will fetch from server (Ctrl-C to abort)\n");
serno = hymod_get_serno (prompt);
if (serno < 0) {
if (serno == -1)
puts ("\n*** interrupted!");
else
puts ("\n*** timeout!");
puts (" - ignoring eeprom contents\n");
return (0);
}
sprintf (filename, "%s/%010d.cfg", dir, serno);
printf ("*** fetching %s board EEPROM contents from server\n",
label);
rc = hymod_eeprom_fetch (which, filename, CONFIG_SYS_LOAD_ADDR);
if (rc == 0) {
puts ("*** fetch failed - ignoring eeprom contents\n");
return (0);
}
count++;
}
}

221
board/hymod/env.c
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@ -1,221 +0,0 @@
/*
* (C) Copyright 2003
* Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/ctype.h>
DECLARE_GLOBAL_DATA_PTR;
/* imports from fetch.c */
extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
/* this is relative to the root of the server's tftp directory */
static char *def_global_env_path = "/hymod/global_env";
static int
env_callback (uchar *name, uchar *value)
{
hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
char ov[CONFIG_SYS_CBSIZE], nv[CONFIG_SYS_CBSIZE], *p, *q, *nn, c, *curver, *newver;
int override = 1, append = 0, remove = 0, nnl, ovl, nvl;
nn = (char *)name;
if (*nn == '-') {
override = 0;
nn++;
}
while (isblank(*nn))
nn++;
if ((nnl = strlen (nn)) == 0) {
printf ("Empty name in global env file\n");
return (0);
}
if ((c = nn[nnl - 1]) == '+' || c == '-') {
if (c == '+')
append = 1;
else
remove = 1;
nn[--nnl] = '\0';
}
while (nnl > 0 && isblank(nn[nnl - 1]))
nn[--nnl] = '\0';
if (nnl == 0) {
printf ("Empty name in global env file\n");
return (0);
}
p = (char *)value;
q = nv;
while (isblank(*p))
p++;
nvl = strlen (p);
while (nvl > 0 && isblank(p[nvl - 1]))
p[--nvl] = '\0';
while ((*q = *p++) != '\0') {
if (*q == '%') {
switch (*p++) {
case '\0': /* whoops - back up */
p--;
break;
case '%': /* a single percent character */
q++;
break;
case 's': /* main board serial number as string */
q += sprintf (q, "%010lu",
cp->main.eeprom.serno);
break;
case 'S': /* main board serial number as number */
q += sprintf (q, "%lu", cp->main.eeprom.serno);
break;
default: /* ignore any others */
break;
}
}
else
q++;
}
if ((nvl = q - nv) == 0) {
setenv (nn, NULL);
return (1);
}
if ((curver = getenv ("global_env_version")) == NULL)
curver = "unknown";
if ((newver = getenv ("new_genv_version")) == NULL || \
strcmp (curver, newver) == 0) {
if (strcmp (nn, "version") == 0)
setenv ("new_genv_version", nv);
return (1);
}
if ((p = getenv (nn)) != NULL) {
strcpy (ov, p);
ovl = strlen (ov);
if (append) {
if (strstr (ov, nv) == NULL) {
printf ("Appending '%s' to env var '%s'\n",
nv, nn);
while (nvl >= 0) {
nv[ovl + 1 + nvl] = nv[nvl];
nvl--;
}
nv[ovl] = ' ';
while (--ovl >= 0)
nv[ovl] = ov[ovl];
setenv (nn, nv);
}
return (1);
}
if (remove) {
if (strstr (ov, nv) != NULL) {
printf ("Removing '%s' from env var '%s'\n",
nv, nn);
while ((p = strstr (ov, nv)) != NULL) {
q = p + nvl;
if (*q == ' ')
q++;
strcpy(p, q);
}
setenv (nn, ov);
}
return (1);
}
if (!override || strcmp (ov, nv) == 0)
return (1);
printf ("Re-setting env cmd '%s' from '%s' to '%s'\n",
nn, ov, nv);
}
else
printf ("Setting env cmd '%s' to '%s'\n", nn, nv);
setenv (nn, nv);
return (1);
}
void
hymod_check_env (void)
{
char *p, *path, *curver, *newver;
int firsttime = 0, needsave = 0;
if (getenv ("global_env_loaded") == NULL) {
puts ("*** global environment has never been loaded\n");
puts ("*** fetching from server");
firsttime = 1;
}
else if ((p = getenv ("always_check_env")) != NULL &&
strcmp (p, "yes") == 0)
puts ("*** checking for updated global environment");
else
return;
puts (" (Control-C to Abort)\n");
if ((path = getenv ("global_env_path")) == NULL || *path == '\0')
path = def_global_env_path;
if (fetch_and_parse (path, CONFIG_SYS_LOAD_ADDR, env_callback) == 0) {
puts ("*** Fetch of global environment failed!\n");
return;
}
if ((newver = getenv ("new_genv_version")) == NULL) {
puts ("*** Version number not set - contents ignored!\n");
return;
}
if ((curver = getenv ("global_env_version")) == NULL || \
strcmp (curver, newver) != 0) {
setenv ("global_env_version", newver);
needsave = 1;
}
else
printf ("*** Global environment up-to-date (ver %s)\n", curver);
setenv ("new_genv_version", NULL);
if (firsttime) {
setenv ("global_env_loaded", "yes");
needsave = 1;
}
if (needsave)
puts ("\n*** Remember to run the 'saveenv' "
"command to save the changes\n\n");
}

91
board/hymod/fetch.c
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@ -1,91 +0,0 @@
/*
* (C) Copyright 2001
* Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <net.h>
/* imports from input.c */
extern int hymod_get_ethaddr (void);
int
fetch_and_parse (char *fn, ulong addr, int (*cback)(uchar *, uchar *))
{
char *ethaddr;
uchar *fp, *efp;
int rc, count = 0;
while ((ethaddr = getenv ("ethaddr")) == NULL || *ethaddr == '\0') {
printf ("*** Ethernet address is%s not set\n",
count == 0 ? "" : " STILL");
if ((rc = hymod_get_ethaddr ()) < 0) {
if (rc == -1)
puts ("\n*** interrupted!");
else
puts ("\n*** timeout!");
printf (" - fetch of '%s' aborted\n", fn);
return (0);
}
count++;
}
copy_filename (BootFile, fn, sizeof (BootFile));
load_addr = addr;
NetBootFileXferSize = 0;
if (NetLoop(TFTPGET) == 0) {
printf ("tftp transfer of file '%s' failed\n", fn);
return (0);
}
if (NetBootFileXferSize == 0) {
printf ("can't determine size of file '%s'\n", fn);
return (0);
}
fp = (uchar *)load_addr;
efp = fp + NetBootFileXferSize;
do {
uchar *name, *value;
if (*fp == '#' || *fp == '\n') {
/* skip this line */
while (fp < efp && *fp++ != '\n')
;
continue;
}
name = fp;
while (fp < efp && *fp != '=' && *fp != '\n')
fp++;
if (fp >= efp)
break;
if (*fp == '\n') {
fp++;
continue;
}
*fp++ = '\0';
value = fp;
while (fp < efp && *fp != '\n')
fp++;
if (fp[-1] == '\r')
fp[-1] = '\0';
*fp++ = '\0'; /* ok if we go off the end here */
if ((*cback)(name, value) == 0)
return (0);
} while (fp < efp);
return (1);
}

490
board/hymod/flash.c
View File

@ -1,490 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
*/
#include <common.h>
#include <mpc8260.h>
#include <board/hymod/flash.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Protection Flags:
*/
#define FLAG_PROTECT_SET 0x01
#define FLAG_PROTECT_CLEAR 0x02
/*-----------------------------------------------------------------------
*/
/*
* probe for flash bank at address "base" and store info about it
* in the flash_info entry "fip". Fatal error if nothing there.
*/
static void
bank_probe (flash_info_t *fip, volatile bank_addr_t base)
{
volatile bank_addr_t addr;
bank_word_t word;
int i;
/* reset the flash */
*base = BANK_CMD_RST;
/* put flash into read id mode */
*base = BANK_CMD_RD_ID;
/* check the manufacturer id - must be intel */
word = *BANK_REG_MAN_CODE (base);
if (word != BANK_FILL_WORD (INTEL_MANUFACT&0xff))
panic ("\nbad manufacturer's code (0x%08lx) at addr 0x%08lx",
(unsigned long)word, (unsigned long)base);
/* check the device id */
word = *BANK_REG_DEV_CODE (base);
switch (word) {
case BANK_FILL_WORD (INTEL_ID_28F320J5&0xff):
fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J5;
fip->sector_count = 32;
break;
case BANK_FILL_WORD (INTEL_ID_28F640J5&0xff):
fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J5;
fip->sector_count = 64;
break;
case BANK_FILL_WORD (INTEL_ID_28F320J3A&0xff):
fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J3A;
fip->sector_count = 32;
break;
case BANK_FILL_WORD (INTEL_ID_28F640J3A&0xff):
fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J3A;
fip->sector_count = 64;
break;
case BANK_FILL_WORD (INTEL_ID_28F128J3A&0xff):
fip->flash_id = FLASH_MAN_INTEL | FLASH_28F128J3A;
fip->sector_count = 128;
break;
default:
panic ("\nbad device code (0x%08lx) at addr 0x%08lx",
(unsigned long)word, (unsigned long)base);
}
if (fip->sector_count >= CONFIG_SYS_MAX_FLASH_SECT)
panic ("\ntoo many sectors (%d) in flash at address 0x%08lx",
fip->sector_count, (unsigned long)base);
addr = base;
for (i = 0; i < fip->sector_count; i++) {
fip->start[i] = (unsigned long)addr;
fip->protect[i] = 0;
addr = BANK_ADDR_NEXT_BLK (addr);
}
fip->size = (bank_size_t)addr - (bank_size_t)base;
/* reset the flash */
*base = BANK_CMD_RST;
}
static void
bank_reset (flash_info_t *info, int sect)
{
volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
#ifdef FLASH_DEBUG
printf ("writing reset cmd to addr 0x%08lx\n", (unsigned long)addr);
#endif
*addr = BANK_CMD_RST;
}
static void
bank_erase_init (flash_info_t *info, int sect)
{
volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
int flag;
#ifdef FLASH_DEBUG
printf ("erasing sector %d, addr = 0x%08lx\n",
sect, (unsigned long)addr);
#endif
/* Disable intrs which might cause a timeout here */
flag = disable_interrupts ();
#ifdef FLASH_DEBUG
printf ("writing erase cmd to addr 0x%08lx\n", (unsigned long)addr);
#endif
*addr = BANK_CMD_ERASE1;
*addr = BANK_CMD_ERASE2;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
}
static int
bank_erase_poll (flash_info_t *info, int sect)
{
volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
bank_word_t stat = *addr;
#ifdef FLASH_DEBUG
printf ("checking status at addr 0x%08lx [0x%08lx]\n",
(unsigned long)addr, (unsigned long)stat);
#endif
if ((stat & BANK_STAT_RDY) == BANK_STAT_RDY) {
if ((stat & BANK_STAT_ERR) != 0) {
printf ("failed on sector %d [0x%08lx] at "
"address 0x%08lx\n", sect,
(unsigned long)stat, (unsigned long)addr);
*addr = BANK_CMD_CLR_STAT;
return (-1);
}
else
return (1);
}
else
return (0);
}
static int
bank_write_word (volatile bank_addr_t addr, bank_word_t value)
{
bank_word_t stat;
ulong start;
int flag, retval;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
*addr = BANK_CMD_PROG;
*addr = value;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
retval = 0;
/* data polling for D7 */
start = get_timer (0);
do {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
retval = 1;
goto done;
}
stat = *addr;
} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
if ((stat & BANK_STAT_ERR) != 0) {
printf ("flash program failed [0x%08lx] at address 0x%08lx\n",
(unsigned long)stat, (unsigned long)addr);
*addr = BANK_CMD_CLR_STAT;
retval = 3;
}
done:
/* reset to read mode */
*addr = BANK_CMD_RST;
return (retval);
}
/*-----------------------------------------------------------------------
*/
unsigned long
flash_init (void)
{
int i;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
bank_probe (&flash_info[0], (bank_addr_t)CONFIG_SYS_FLASH_BASE);
/*
* protect monitor and environment sectors
*/
#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
(void)flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
#if defined(CONFIG_SYS_FLASH_ENV_ADDR)
(void)flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_ENV_ADDR,
#if defined(CONFIG_SYS_FLASH_ENV_BUF)
CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_BUF - 1,
#else
CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_SIZE - 1,
#endif
&flash_info[0]);
#endif
return flash_info[0].size;
}
/*-----------------------------------------------------------------------
*/
void
flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL: printf ("INTEL "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F320J5: printf ("28F320J5 (32 Mbit, 2 x 16bit)\n");
break;
case FLASH_28F640J5: printf ("28F640J5 (64 Mbit, 2 x 16bit)\n");
break;
case FLASH_28F320J3A: printf ("28F320J3A (32 Mbit, 2 x 16bit)\n");
break;
case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 2 x 16bit)\n");
break;
case FLASH_28F128J3A: printf ("28F320J3A (128 Mbit, 2 x 16bit)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
return;
}
/*
* The following code cannot be run from FLASH!
*/
/*-----------------------------------------------------------------------
*/
int
flash_erase (flash_info_t *info, int s_first, int s_last)
{
int prot, sect, haderr;
ulong start, now, last;
int rcode = 0;
#ifdef FLASH_DEBUG
printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
" Bank # %d: ", s_last - s_first + 1, s_first, s_last,
(info - flash_info) + 1);
flash_print_info (info);
#endif
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sector%s will not be erased\n",
prot, (prot > 1 ? "s" : ""));
}
start = get_timer (0);
last = 0;
haderr = 0;
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
ulong estart;
int sectdone;
bank_erase_init (info, sect);
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
estart = get_timer (start);
do {
now = get_timer (start);
if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout (sect %d)\n", sect);
haderr = 1;
rcode = 1;
break;
}
#ifndef FLASH_DEBUG
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
#endif
sectdone = bank_erase_poll (info, sect);
if (sectdone < 0) {
haderr = 1;
rcode = 1;
break;
}
} while (!sectdone);
if (haderr)
break;
}
}
if (haderr > 0)
printf (" failed\n");
else
printf (" done\n");
/* reset to read mode */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
bank_reset (info, sect);
}
}
return rcode;
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 3 - Program failed
*/
static int
write_word (flash_info_t *info, ulong dest, ulong data)
{
/* Check if Flash is (sufficiently) erased */
if ((*(ulong *)dest & data) != data)
return (2);
return (bank_write_word ((bank_addr_t)dest, (bank_word_t)data));
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 3 - Program failed
*/
int
write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word (info, wp, data));
}
/*-----------------------------------------------------------------------
*/

140
board/hymod/flash.h
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@ -1,140 +0,0 @@
/*
* (C) Copyright 2000
* Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
/* Commands */
#define ISF_CMD_RST 0xFF /* reset flash */
#define ISF_CMD_RD_ID 0x90 /* read the id and lock bits */
#define ISF_CMD_RD_QUERY 0x98 /* read device capabilities */
#define ISF_CMD_RD_STAT 0x70 /* read the status register */
#define ISF_CMD_CLR_STAT 0x50 /* clear the staus register */
#define ISF_CMD_WR_BUF 0xE8 /* clear the staus register */
#define ISF_CMD_PROG 0x40 /* program word command */
#define ISF_CMD_ERASE1 0x20 /* 1st word for block erase */
#define ISF_CMD_ERASE2 0xD0 /* 2nd word for block erase */
#define ISF_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
#define ISF_CMD_LOCK 0x60 /* 1st word for all lock cmds */
#define ISF_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
#define ISF_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
#define ISF_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
/* status register bits */
#define ISF_STAT_DPS 0x02 /* Device Protect Status */
#define ISF_STAT_VPPS 0x08 /* VPP Status */
#define ISF_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
#define ISF_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
#define ISF_STAT_ESS 0x40 /* Erase Suspend Status */
#define ISF_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
#define ISF_STAT_ERR (ISF_STAT_VPPS | ISF_STAT_DPS | \
ISF_STAT_ECLBS | ISF_STAT_PSLBS)
/* register addresses, valid only following an ISF_CMD_RD_ID command */
#define ISF_REG_MAN_CODE 0x00 /* manufacturer code */
#define ISF_REG_DEV_CODE 0x01 /* device code */
#define ISF_REG_BLK_LCK 0x02 /* block lock configuration */
#define ISF_REG_MST_LCK 0x03 /* master lock configuration */
/********************** DEFINES for Hymod Flash ******************************/
/*
* this code requires that the flash on any Hymod board appear as a bank
* of two (identical) 16bit Intel StrataFlash chips with 64Kword erase
* sectors (or blocks), running in x16 bit mode and connected side-by-side
* to make a 32-bit wide bus.
*/
typedef unsigned long bank_word_t;
typedef bank_word_t bank_blk_t[64 * 1024];
#define BANK_FILL_WORD(b) (((bank_word_t)(b) << 16) | (bank_word_t)(b))
#ifdef EXAMPLE
/* theoretically the following examples should also work */
/* one flash chip in x8 mode with 128Kword sectors and 8bit bus */
typedef unsigned char bank_word_t;
typedef bank_word_t bank_blk_t[128 * 1024];
#define BANK_FILL_WORD(b) ((bank_word_t)(b))
/* four flash chips in x16 mode with 32Kword sectors and 64bit bus */
typedef unsigned long long bank_word_t;
typedef bank_word_t bank_blk_t[32 * 1024];
#define BANK_FILL_WORD(b) ( \
((bank_word_t)(b) << 48) \
((bank_word_t)(b) << 32) \
((bank_word_t)(b) << 16) \
((bank_word_t)(b) << 0) \
)
#endif /* EXAMPLE */
/* the sizes of these two types should probably be the same */
typedef bank_word_t *bank_addr_t;
typedef unsigned long bank_size_t;
/* align bank addresses and sizes to bank word boundaries */
#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
& ~(sizeof (bank_word_t) - 1)))
#define BANK_SIZE_WORD_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_word_t) - 1) \
& ~(sizeof (bank_word_t) - 1))
/* align bank addresses and sizes to bank block boundaries */
#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
& ~(sizeof (bank_blk_t) - 1)))
#define BANK_SIZE_BLK_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_blk_t) - 1) \
& ~(sizeof (bank_blk_t) - 1))
/* add an offset to a bank address */
#define BANK_ADDR_OFFSET(a, o) ((bank_addr_t)((bank_size_t)(a) + \
(bank_size_t)(o)))
/* adjust a bank address to start of next word, block or bank */
#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
sizeof (bank_word_t))
#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
sizeof (bank_blk_t))
/* get bank address of register r given a bank base address a and block num b */
#define BANK_ADDR_REG(a, b, r) BANK_ADDR_OFFSET(BANK_ADDR_OFFSET((a), \
(bank_size_t)(b) * sizeof (bank_blk_t)), \
(bank_size_t)(r) * sizeof (bank_word_t))
/* make a bank word value for each StrataFlash value */
/* Commands */
#define BANK_CMD_RST BANK_FILL_WORD(ISF_CMD_RST)
#define BANK_CMD_RD_ID BANK_FILL_WORD(ISF_CMD_RD_ID)
#define BANK_CMD_RD_STAT BANK_FILL_WORD(ISF_CMD_RD_STAT)
#define BANK_CMD_CLR_STAT BANK_FILL_WORD(ISF_CMD_CLR_STAT)
#define BANK_CMD_ERASE1 BANK_FILL_WORD(ISF_CMD_ERASE1)
#define BANK_CMD_ERASE2 BANK_FILL_WORD(ISF_CMD_ERASE2)
#define BANK_CMD_PROG BANK_FILL_WORD(ISF_CMD_PROG)
#define BANK_CMD_LOCK BANK_FILL_WORD(ISF_CMD_LOCK)
#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(ISF_CMD_SET_LOCK_BLK)
#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(ISF_CMD_SET_LOCK_MSTR)
#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(ISF_CMD_CLR_LOCK_BLK)
/* status register bits */
#define BANK_STAT_DPS BANK_FILL_WORD(ISF_STAT_DPS)
#define BANK_STAT_PSS BANK_FILL_WORD(ISF_STAT_PSS)
#define BANK_STAT_VPPS BANK_FILL_WORD(ISF_STAT_VPPS)
#define BANK_STAT_PSLBS BANK_FILL_WORD(ISF_STAT_PSLBS)
#define BANK_STAT_ECLBS BANK_FILL_WORD(ISF_STAT_ECLBS)
#define BANK_STAT_ESS BANK_FILL_WORD(ISF_STAT_ESS)
#define BANK_STAT_RDY BANK_FILL_WORD(ISF_STAT_RDY)
#define BANK_STAT_ERR BANK_FILL_WORD(ISF_STAT_ERR)
/* make a bank register address for each StrataFlash register address */
#define BANK_REG_MAN_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_MAN_CODE)
#define BANK_REG_DEV_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_DEV_CODE)
#define BANK_REG_BLK_LCK(a, b) BANK_ADDR_REG((a), (b), ISF_REG_BLK_LCK)
#define BANK_REG_MST_LCK(a) BANK_ADDR_REG((a), 0, ISF_REG_MST_LCK)

145
board/hymod/global_env
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@ -1,145 +0,0 @@
# DONT FORGET TO CHANGE THE "version" VAR BELOW IF YOU MAKE CHANGES TO THIS FILE
# (C) Copyright 2001
# Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
#
# SPDX-License-Identifier: GPL-2.0+
#
# global_env
#
# file used by Hymod boards to initialise the u-boot non-volatile
# environment when u-boot is first run (it determines this by the
# absence of the environment variable "global_env_loaded")
#
# format of this file is:
#
# 1. blank lines and lines beginning with '#' are ignored
# 2. all other lines must have the form <name>=<value>
# 3. if a percent appears anywhere, it is replaced like so:
#
# %s serial number of the main board (10 digit zero filled)
# %S serial number of the main board (plain number)
# %% a percentage character
# ... otherwise the %x is discarded
#
# if first character in <name> is a dash ('-'), then an existing env var
# will not be overwritten (the dash is removed). i.e. it is only set if
# it does not exist
#
# if last character in <name> is a plus ('+'), then <value> will be appended
# to any existing env var (the plus is ignored). Duplicates of <value> are
# removed.
#
# similarly, if the last character in <name> is a minus ('-'), then any
# occurences of <value> in the current value of <name> will removed (the
# minus is ignored).
#
# leading and trailing whitespace is removed in both <name> and <value>
# (after processing any initial or final plus/minus in <name>).
#
# MISCELLANEOUS PARAMETERS
# version must always come first
version=4
# set the ip address based on the main board serial number
ipaddr=192.168.1.%S
serverip=192.168.1.254
# stop auto execute after tftp (not a very good name really)
autostart=no
# setting this to "yes" forces the global_env file to be loaded and processed
# if the current version is different to the version in the file
always_check_env=no
# BOOTING COMMANDS AND PARAMETERS
# command to run when "auto-booting"
bootcmd=bootm 40080000
# how long the "countdown" to automatically running "bootcmd" is
bootdelay=2
# how long before it "times out" console input and attempts to run "bootcmd"
bootretry=5
# arguments passed to the boot program (i.e. linux kernel) via register 6
# the linux kernel (v2.4) uses the following registers:
# r3 - address of board information structure
# r4 - address of initial ramdisk image (0 means no initrd)
# r5 - size of initial ramdisk image
# r6 - address of command line string
-bootargs=root=/dev/mtdblock5 rootfstype=squashfs ro
# these four are for hymod linux integrated into our Sun network
bootargs+=serialno=%S
bootargs+=nisclient nisdomain=mlb.dmt.csiro.au nissrvadr=138.194.112.4
bootargs+=nfsclient
bootargs+=automount
# start a web server by default
bootargs+=webserver
# give negotiation time to finish
bootargs+=netsleep=5
# then our ciscos don't pass packets for 25-30 secs after that, so
# pinging the server until it responds prevents network connections
# from failing...
bootargs+=netping
# these are old bootargs - we don't need them anymore
bootargs-=preload=unix,i2c-cpm,i2c-dev
bootargs-=ramdisk_size=32768
bootargs-=ramdisk_size=24576
# FLASH MANIPULATION COMMANDS
#
# 16M flash, 64 x 256K sectors, mapped at address 0x40000000
#
# Sector(s) Address Size Description
#
# 0 - 0 0x40000000 256K boot code
# 1 - 1 0x40040000 256K non volatile environment
# 2 - 4 0x40080000 768K linux kernel image
# 5 - 7 0x40140000 768K alternate linux kernel image
# 8 - 47 0x40200000 10M linux initial ramdisk image
# 48 - 63 0x40c00000 4M ramdisk image for applications
#
fetchboot=tftp 100000 /hymod/u-boot.bin
eraseboot=protect off 1:0 ; erase 1:0 ; protect on 1:0
copyboot=protect off 1:0 ; cp.b 100000 40000000 40000 ; protect on 1:0
cmpboot=cmp.b 100000 40000000 40000
newboot=run fetchboot eraseboot copyboot cmpboot
fetchlinux=tftp 100000 /hymod/linux.bin
eraselinux=erase 1:2-4
copylinux=cp.b 100000 40080000 ${filesize}
cmplinux=cmp.b 100000 40080000 ${filesize}
newlinux=run fetchlinux eraselinux copylinux cmplinux
fetchaltlinux=tftp 100000 /hymod/altlinux.bin
erasealtlinux=erase 1:5-7
copyaltlinux=cp.b 100000 40140000 ${filesize}
cmpaltlinux=cmp.b 100000 40140000 ${filesize}
newaltlinux=run fetchaltlinux erasealtlinux copyaltlinux cmpaltlinux
fetchroot=tftp 100000 /hymod/root.bin
eraseroot=erase 1:8-47
copyroot=cp.b 100000 40200000 ${filesize}
cmproot=cmp.b 100000 40200000 ${filesize}
newroot=run fetchroot eraseroot copyroot cmproot
fetchard=tftp 100000 /hymod/apprd.bin
eraseard=erase 1:48-63
copyard=cp.b 100000 40c00000 ${filesize}
cmpard=cmp.b 100000 40c00000 ${filesize}
newapprd=run fetchard eraseard copyard cmpard
# pass above map to linux mtd driver
bootargs+=mtdparts=phys:256k(u-boot),256k(u-boot-env),768k(linux),768k(altlinux),10m(root),4m(hymod)

521
board/hymod/hymod.c
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@ -1,521 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
*/
#include <common.h>
#include <bootretry.h>
#include <cli.h>
#include <mpc8260.h>
#include <mpc8260_irq.h>
#include <ioports.h>
#include <i2c.h>
#include <asm/iopin_8260.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/* imports from eeprom.c */
extern int hymod_eeprom_read (int, hymod_eeprom_t *);
extern void hymod_eeprom_print (hymod_eeprom_t *);
/* imports from env.c */
extern void hymod_check_env (void);
/* ------------------------------------------------------------------------- */
/*
* I/O Port configuration table
*
* if conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{
/* cnf par sor dir odr dat */
{ 1, 1, 1, 0, 0, 0 }, /* PA31: FCC1 MII COL */
{ 1, 1, 1, 0, 0, 0 }, /* PA30: FCC1 MII CRS */
{ 1, 1, 1, 1, 0, 0 }, /* PA29: FCC1 MII TX_ER */
{ 1, 1, 1, 1, 0, 0 }, /* PA28: FCC1 MII TX_EN */
{ 1, 1, 1, 0, 0, 0 }, /* PA27: FCC1 MII RX_DV */
{ 1, 1, 1, 0, 0, 0 }, /* PA26: FCC1 MII RX_ER */
{ 1, 0, 0, 1, 0, 0 }, /* PA25: FCC2 MII MDIO */
{ 1, 0, 0, 1, 0, 0 }, /* PA24: FCC2 MII MDC */
{ 1, 0, 0, 1, 0, 0 }, /* PA23: FCC3 MII MDIO */
{ 1, 0, 0, 1, 0, 0 }, /* PA22: FCC3 MII MDC */
{ 1, 1, 0, 1, 0, 0 }, /* PA21: FCC1 MII TxD[3] */
{ 1, 1, 0, 1, 0, 0 }, /* PA20: FCC1 MII TxD[2] */
{ 1, 1, 0, 1, 0, 0 }, /* PA19: FCC1 MII TxD[1] */
{ 1, 1, 0, 1, 0, 0 }, /* PA18: FCC1 MII TxD[0] */
{ 1, 1, 0, 0, 0, 0 }, /* PA17: FCC1 MII RxD[3] */
{ 1, 1, 0, 0, 0, 0 }, /* PA16: FCC1 MII RxD[2] */
{ 1, 1, 0, 0, 0, 0 }, /* PA15: FCC1 MII RxD[1] */
{ 1, 1, 0, 0, 0, 0 }, /* PA14: FCC1 MII RxD[0] */
{ 1, 0, 0, 1, 0, 0 }, /* PA13: FCC1 MII MDIO */
{ 1, 0, 0, 1, 0, 0 }, /* PA12: FCC1 MII MDC */
{ 1, 0, 0, 1, 0, 0 }, /* PA11: SEL_CD */
{ 1, 0, 0, 0, 0, 0 }, /* PA10: FLASH STS1 */
{ 1, 0, 0, 0, 0, 0 }, /* PA09: FLASH STS0 */
{ 1, 0, 0, 0, 0, 0 }, /* PA08: FLASH ~PE */
{ 1, 0, 0, 0, 0, 0 }, /* PA07: WATCH ~HRESET */
{ 1, 0, 0, 0, 1, 0 }, /* PA06: VC DONE */
{ 1, 0, 0, 1, 1, 0 }, /* PA05: VC INIT */
{ 1, 0, 0, 1, 0, 0 }, /* PA04: VC ~PROG */
{ 1, 0, 0, 1, 0, 0 }, /* PA03: VM ENABLE */
{ 1, 0, 0, 0, 1, 0 }, /* PA02: VM DONE */
{ 1, 0, 0, 1, 1, 0 }, /* PA01: VM INIT */
{ 1, 0, 0, 1, 0, 0 } /* PA00: VM ~PROG */
},
/* Port B configuration */
{
/* cnf par sor dir odr dat */
{ 1, 1, 0, 1, 0, 0 }, /* PB31: FCC2 MII TX_ER */
{ 1, 1, 0, 0, 0, 0 }, /* PB30: FCC2 MII RX_DV */
{ 1, 1, 1, 1, 0, 0 }, /* PB29: FCC2 MII TX_EN */
{ 1, 1, 0, 0, 0, 0 }, /* PB28: FCC2 MII RX_ER */
{ 1, 1, 0, 0, 0, 0 }, /* PB27: FCC2 MII COL */
{ 1, 1, 0, 0, 0, 0 }, /* PB26: FCC2 MII CRS */
{ 1, 1, 0, 1, 0, 0 }, /* PB25: FCC2 MII TxD[3] */
{ 1, 1, 0, 1, 0, 0 }, /* PB24: FCC2 MII TxD[2] */
{ 1, 1, 0, 1, 0, 0 }, /* PB23: FCC2 MII TxD[1] */
{ 1, 1, 0, 1, 0, 0 }, /* PB22: FCC2 MII TxD[0] */
{ 1, 1, 0, 0, 0, 0 }, /* PB21: FCC2 MII RxD[0] */
{ 1, 1, 0, 0, 0, 0 }, /* PB20: FCC2 MII RxD[1] */
{ 1, 1, 0, 0, 0, 0 }, /* PB19: FCC2 MII RxD[2] */
{ 1, 1, 0, 0, 0, 0 }, /* PB18: FCC2 MII RxD[3] */
{ 1, 1, 0, 0, 0, 0 }, /* PB17: FCC3 MII RX_DV */
{ 1, 1, 0, 0, 0, 0 }, /* PB16: FCC3 MII RX_ER */
{ 1, 1, 0, 1, 0, 0 }, /* PB15: FCC3 MII TX_ER */
{ 1, 1, 0, 1, 0, 0 }, /* PB14: FCC3 MII TX_EN */
{ 1, 1, 0, 0, 0, 0 }, /* PB13: FCC3 MII COL */
{ 1, 1, 0, 0, 0, 0 }, /* PB12: FCC3 MII CRS */
{ 1, 1, 0, 0, 0, 0 }, /* PB11: FCC3 MII RxD[3] */
{ 1, 1, 0, 0, 0, 0 }, /* PB10: FCC3 MII RxD[2] */
{ 1, 1, 0, 0, 0, 0 }, /* PB09: FCC3 MII RxD[1] */
{ 1, 1, 0, 0, 0, 0 }, /* PB08: FCC3 MII RxD[0] */
{ 1, 1, 0, 1, 0, 0 }, /* PB07: FCC3 MII TxD[3] */
{ 1, 1, 0, 1, 0, 0 }, /* PB06: FCC3 MII TxD[2] */
{ 1, 1, 0, 1, 0, 0 }, /* PB05: FCC3 MII TxD[1] */
{ 1, 1, 0, 1, 0, 0 }, /* PB04: FCC3 MII TxD[0] */
{ 0, 0, 0, 0, 0, 0 }, /* PB03: pin doesn't exist */
{ 0, 0, 0, 0, 0, 0 }, /* PB02: pin doesn't exist */
{ 0, 0, 0, 0, 0, 0 }, /* PB01: pin doesn't exist */
{ 0, 0, 0, 0, 0, 0 } /* PB00: pin doesn't exist */
},
/* Port C configuration */
{
/* cnf par sor dir odr dat */
{ 1, 0, 0, 0, 0, 0 }, /* PC31: MEZ ~IACK */
{ 0, 0, 0, 0, 0, 0 }, /* PC30: ? */
{ 1, 1, 0, 0, 0, 0 }, /* PC29: CLK SCCx */
{ 1, 1, 0, 0, 0, 0 }, /* PC28: CLK4 */
{ 1, 1, 0, 0, 0, 0 }, /* PC27: CLK SCCF */
{ 1, 1, 0, 0, 0, 0 }, /* PC26: CLK 32K */
{ 1, 1, 0, 0, 0, 0 }, /* PC25: BRG4/CLK7 */
{ 0, 0, 0, 0, 0, 0 }, /* PC24: ? */
{ 1, 1, 0, 0, 0, 0 }, /* PC23: CLK SCCx */
{ 1, 1, 0, 0, 0, 0 }, /* PC22: FCC1 MII RX_CLK */
{ 1, 1, 0, 0, 0, 0 }, /* PC21: FCC1 MII TX_CLK */
{ 1, 1, 0, 0, 0, 0 }, /* PC20: CLK SCCF */
{ 1, 1, 0, 0, 0, 0 }, /* PC19: FCC2 MII RX_CLK */
{ 1, 1, 0, 0, 0, 0 }, /* PC18: FCC2 MII TX_CLK */
{ 1, 1, 0, 0, 0, 0 }, /* PC17: FCC3 MII RX_CLK */
{ 1, 1, 0, 0, 0, 0 }, /* PC16: FCC3 MII TX_CLK */
{ 1, 0, 0, 0, 0, 0 }, /* PC15: SCC1 UART ~CTS */
{ 1, 0, 0, 0, 0, 0 }, /* PC14: SCC1 UART ~CD */
{ 1, 0, 0, 0, 0, 0 }, /* PC13: SCC2 UART ~CTS */
{ 1, 0, 0, 0, 0, 0 }, /* PC12: SCC2 UART ~CD */
{ 1, 0, 0, 1, 0, 0 }, /* PC11: SCC1 UART ~DTR */
{ 1, 0, 0, 1, 0, 0 }, /* PC10: SCC1 UART ~DSR */
{ 1, 0, 0, 1, 0, 0 }, /* PC09: SCC2 UART ~DTR */
{ 1, 0, 0, 1, 0, 0 }, /* PC08: SCC2 UART ~DSR */
{ 1, 0, 0, 0, 0, 0 }, /* PC07: TEMP ~ALERT */
{ 1, 0, 0, 0, 0, 0 }, /* PC06: FCC3 INT */
{ 1, 0, 0, 0, 0, 0 }, /* PC05: FCC2 INT */
{ 1, 0, 0, 0, 0, 0 }, /* PC04: FCC1 INT */
{ 0, 1, 1, 1, 0, 0 }, /* PC03: SDMA IDMA2 ~DACK */
{ 0, 1, 1, 0, 0, 0 }, /* PC02: SDMA IDMA2 ~DONE */
{ 0, 1, 0, 0, 0, 0 }, /* PC01: SDMA IDMA2 ~DREQ */
{ 1, 1, 0, 1, 0, 0 } /* PC00: BRG7 */
},
/* Port D configuration */
{
/* cnf par sor dir odr dat */
{ 1, 1, 0, 0, 0, 0 }, /* PD31: SCC1 UART RxD */
{ 1, 1, 1, 1, 0, 0 }, /* PD30: SCC1 UART TxD */
{ 1, 0, 0, 1, 0, 0 }, /* PD29: SCC1 UART ~RTS */
{ 1, 1, 0, 0, 0, 0 }, /* PD28: SCC2 UART RxD */
{ 1, 1, 0, 1, 0, 0 }, /* PD27: SCC2 UART TxD */
{ 1, 0, 0, 1, 0, 0 }, /* PD26: SCC2 UART ~RTS */
{ 1, 0, 0, 0, 0, 0 }, /* PD25: SCC1 UART ~RI */
{ 1, 0, 0, 0, 0, 0 }, /* PD24: SCC2 UART ~RI */
{ 1, 0, 0, 1, 0, 0 }, /* PD23: CLKGEN PD */
{ 1, 0, 0, 0, 0, 0 }, /* PD22: USER3 */
{ 1, 0, 0, 0, 0, 0 }, /* PD21: USER2 */
{ 1, 0, 0, 0, 0, 0 }, /* PD20: USER1 */
{ 1, 1, 1, 0, 0, 0 }, /* PD19: SPI ~SEL */
{ 1, 1, 1, 0, 0, 0 }, /* PD18: SPI CLK */
{ 1, 1, 1, 0, 0, 0 }, /* PD17: SPI MOSI */
{ 1, 1, 1, 0, 0, 0 }, /* PD16: SPI MISO */
{ 1, 1, 1, 0, 1, 0 }, /* PD15: I2C SDA */
{ 1, 1, 1, 0, 1, 0 }, /* PD14: I2C SCL */
{ 1, 0, 0, 1, 0, 1 }, /* PD13: TEMP ~STDBY */
{ 1, 0, 0, 1, 0, 1 }, /* PD12: FCC3 ~RESET */
{ 1, 0, 0, 1, 0, 1 }, /* PD11: FCC2 ~RESET */
{ 1, 0, 0, 1, 0, 1 }, /* PD10: FCC1 ~RESET */
{ 1, 0, 0, 0, 0, 0 }, /* PD09: PD9 */
{ 1, 0, 0, 0, 0, 0 }, /* PD08: PD8 */
{ 1, 0, 0, 1, 0, 1 }, /* PD07: PD7 */
{ 1, 0, 0, 1, 0, 1 }, /* PD06: PD6 */
{ 1, 0, 0, 1, 0, 1 }, /* PD05: PD5 */
{ 1, 0, 0, 1, 0, 1 }, /* PD04: PD4 */
{ 0, 0, 0, 0, 0, 0 }, /* PD03: pin doesn't exist */
{ 0, 0, 0, 0, 0, 0 }, /* PD02: pin doesn't exist */
{ 0, 0, 0, 0, 0, 0 }, /* PD01: pin doesn't exist */
{ 0, 0, 0, 0, 0, 0 } /* PD00: pin doesn't exist */
}
};
/* ------------------------------------------------------------------------- */
/*
* AMI FS6377 Clock Generator configuration table
*
* the "fs6377_regs[]" table entries correspond to FS6377 registers
* 0 - 15 (total of 16 bytes).
*
* the data is written to the FS6377 via the i2c bus using address in
* "fs6377_addr" (address is 7 bits - R/W bit not included).
*
* The fs6377 has four clock outputs: A, B, C and D.
*
* Outputs C and D can each provide two different clock outputs C1/D1 or
* C2/D2 depending on the state of the SEL_CD input which is connected to
* the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0)
* selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2.
*
* PA11 defaults to output low (or 0) in the i/o port config table above.
*
* Output A provides a 100MHz for the High Speed Serial chips. Output B
* provides a 3.6864MHz clock for more accurate asynchronous serial bit
* rates. Output C is routed to the mezzanine connector but is currently
* unused - both C1 and C2 are set to 16MHz. Output D is used by both the
* alt-input and display mezzanine boards for their video chips. The
* alt-input board requires a clock of 24.576MHz and this is available on
* D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this
* is available on D2 (PA11=SEL_CD=1).
*
* So the default is a clock suitable for the alt-input board. PA11 is toggled
* later in misc_init_r(), if a display board is detected.
*/
uchar fs6377_addr = 0x5c;
uchar fs6377_regs[16] = {
12, 75, 64, 25, 144, 128, 25, 192,
0, 16, 135, 192, 224, 64, 64, 192
};
/* ------------------------------------------------------------------------- */
/*
* special board initialisation, after clocks and timebase have been
* set up but before environment and serial are initialised.
*
* added so that very early initialisations can be done using the i2c
* driver (which requires the clocks, to calculate the dividers, and
* the timebase, for udelay())
*/
int
board_postclk_init (void)
{
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
/*
* Initialise the FS6377 clock chip
*
* the secondary address is the register number from where to
* start the write - I want to write all the registers
*
* don't bother checking return status - we have no console yet
* to print it on, nor any RAM to store it in - it will be obvious
* if this doesn't work
*/
(void) i2c_write (fs6377_addr, 0, 1, fs6377_regs,
sizeof (fs6377_regs));
return (0);
}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity: Hardwired to HYMOD
*/
int
checkboard (void)
{
puts ("Board: HYMOD\n");
return (0);
}
/* ------------------------------------------------------------------------- */
/*
* miscellaneous (early - while running in flash) initialisations.
*/
#define _NOT_USED_ 0xFFFFFFFF
uint upmb_table[] = {
/* Read Single Beat (RSS) - offset 0x00 */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Read Burst (RBS) - offset 0x08 */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Write Single Beat (WSS) - offset 0x18 */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Write Burst (WSS) - offset 0x20 */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Refresh Timer (PTS) - offset 0x30 */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Exception Condition (EXS) - offset 0x3c */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
};
uint upmc_table[] = {
/* Read Single Beat (RSS) - offset 0x00 */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Read Burst (RBS) - offset 0x08 */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Write Single Beat (WSS) - offset 0x18 */
0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000,
0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Write Burst (WSS) - offset 0x20 */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Refresh Timer (PTS) - offset 0x30 */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Exception Condition (EXS) - offset 0x3c */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
};
int
misc_init_f (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
printf ("UPMs: ");
upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
memctl->memc_mbmr = CONFIG_SYS_MBMR;
upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
memctl->memc_mcmr = CONFIG_SYS_MCMR;
printf ("configured\n");
return (0);
}
/* ------------------------------------------------------------------------- */
phys_size_t
initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
ulong psdmr = CONFIG_SYS_PSDMR;
int i;
/*
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
*
* "At system reset, initialization software must set up the
* programmable parameters in the memory controller banks registers
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
* system software should execute the following initialization sequence
* for each SDRAM device.
*
* 1. Issue a PRECHARGE-ALL-BANKS command
* 2. Issue eight CBR REFRESH commands
* 3. Issue a MODE-SET command to initialize the mode register
*
* The initial commands are executed by setting P/LSDMR[OP] and
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
*/
memctl->memc_psrt = CONFIG_SYS_PSRT;
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
*ramaddr = c;
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++)
*ramaddr = c;
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
*ramaddr = c;
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*ramaddr = c;
return (CONFIG_SYS_SDRAM_SIZE << 20);
}
/* ------------------------------------------------------------------------- */
/* miscellaneous initialisations after relocation into ram (misc_init_r) */
/* */
/* loads the data in the main board and mezzanine board eeproms into */
/* the hymod configuration struct stored in the board information area. */
/* */
/* if the contents of either eeprom is invalid, prompts for a serial */
/* number (and an ethernet address if required) then fetches a file */
/* containing information to be stored in the eeprom from the tftp server */
/* (the file name is based on the serial number and a built-in path) */
int
last_stage_init (void)
{
hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
int rc;
/*
* we use the cli_readline() function, but we also want
* command timeout enabled
*/
bootretry_init_cmd_timeout();
memset ((void *) cp, 0, sizeof (*cp));
/* set up main board config info */
rc = hymod_eeprom_read (0, &cp->main.eeprom);
puts ("EEPROM:main...");
if (rc < 0)
puts ("NOT PRESENT\n");
else if (rc == 0)
puts ("INVALID\n");
else {
cp->main.eeprom.valid = 1;
printf ("OK (ver %u)\n", cp->main.eeprom.ver);
hymod_eeprom_print (&cp->main.eeprom);
/*
* hard-wired assumption here: all hymod main boards will have
* one xilinx fpga, with the interrupt line connected to IRQ2
*
* One day, this might be based on the board type
*/
cp->main.xlx[0].mmap.prog.exists = 1;
cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE;
cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE;
cp->main.xlx[0].mmap.reg.exists = 1;
cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE;
cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE;
cp->main.xlx[0].mmap.port.exists = 1;
cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE;
cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE;
cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT;
cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN;
cp->main.xlx[0].iopins.prog_pin.flag = 1;
cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT;
cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN;
cp->main.xlx[0].iopins.init_pin.flag = 1;
cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT;
cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN;
cp->main.xlx[0].iopins.done_pin.flag = 1;
#ifdef FPGA_MAIN_ENABLE_PORT
cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT;
cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN;
cp->main.xlx[0].iopins.enable_pin.flag = 1;
#endif
cp->main.xlx[0].irq = FPGA_MAIN_IRQ;
}
/* set up mezzanine board config info */
rc = hymod_eeprom_read (1, &cp->mezz.eeprom);
puts ("EEPROM:mezz...");
if (rc < 0)
puts ("NOT PRESENT\n");
else if (rc == 0)
puts ("INVALID\n");
else {
cp->main.eeprom.valid = 1;
printf ("OK (ver %u)\n", cp->mezz.eeprom.ver);
hymod_eeprom_print (&cp->mezz.eeprom);
}
cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc));
hymod_check_env ();
return (0);
}
#ifdef CONFIG_SHOW_ACTIVITY
void board_show_activity (ulong timebase)
{
#ifdef CONFIG_SYS_HYMOD_DBLEDS
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile iop8260_t *iop = &immr->im_ioport;
static int shift = 0;
if ((timestamp % CONFIG_SYS_HZ) == 0) {
if (++shift > 3)
shift = 0;
iop->iop_pdatd =
(iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
}
#endif /* CONFIG_SYS_HYMOD_DBLEDS */
}
void show_activity(int arg)
{
}
#endif /* CONFIG_SHOW_ACTIVITY */

305
board/hymod/hymod.h
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@ -1,305 +0,0 @@
/*
* (C) Copyright 2001
* Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _HYMOD_H_
#define _HYMOD_H_
#ifdef CONFIG_MPC8260
#include <asm/iopin_8260.h>
#endif
/*
* hymod configuration data - passed by boot code via the board information
* structure (only U-Boot has support for this at the moment)
*
* there are three types of data passed up from the boot monitor. the first
* (type hymod_eeprom_t) is the eeprom data that was read off both the main
* (or mother) board and the mezzanine board (if any). this data defines how
* many Xilinx fpgas are on each board, and their types (among other things).
* the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where
* in the physical address space the various Xilinx fpga access regions have
* been mapped by the boot rom. the third type of data (type xlx_iopins_t,
* one per Xilinx fpga) defines which io port pins are connected to the various
* signals required to program a Xilinx fpga.
*
* A ram/flash "bank" refers to memory controlled by the same chip select.
*
* the eeprom contents are defined as in technical note #2 - basically,
* a header, zero or more records in no particular order, and a 32 bit crc
* a record is 1 or more type bytes, a length byte and "length" bytes.
*/
#define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */
#define HYMOD_EEPROM_VER 1 /* eeprom contents version (0-127) */
#define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */
/* eeprom header */
typedef
struct {
unsigned char id; /* eeprom id byte */
unsigned char :1;
unsigned char ver:7; /* eeprom contents version number */
unsigned long len; /* total # of bytes btw hdr and crc */
}
hymod_eehdr_t;
/* maximum number of bytes available for eeprom data records */
#define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \
- sizeof (hymod_eehdr_t) \
- sizeof (unsigned long))
/* eeprom data record */
typedef
union {
struct {
unsigned char topbit:1;
unsigned char type:7;
unsigned char len;
unsigned char data[1]; /* variable length */
} small;
struct {
unsigned short topbit:1;
unsigned short nxtbit:1;
unsigned short type:14;
unsigned short len;
unsigned char data[1]; /* variable length */
} medium;
struct {
unsigned long topbit:1;
unsigned long nxtbit:1;
unsigned long type:30;
unsigned long len;
unsigned char data[1]; /* variable length */
} large;
}
hymod_eerec_t;
#define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */
#define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */
/* eeprom record types */
#define HYMOD_EEREC_SERNO 1 /* serial number */
#define HYMOD_EEREC_DATE 2 /* date */
#define HYMOD_EEREC_BATCH 3 /* batch id */
#define HYMOD_EEREC_TYPE 4 /* board type */
#define HYMOD_EEREC_REV 5 /* revision number */
#define HYMOD_EEREC_SDRAM 6 /* sdram sizes */
#define HYMOD_EEREC_FLASH 7 /* flash sizes */
#define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */
#define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */
#define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */
#define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */
#define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */
#define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */
#define HYMOD_EEREC_CPUSPD 14 /* CPU speed */
#define HYMOD_EEREC_BUSSPD 15 /* bus speed */
#define HYMOD_EEREC_CPMSPD 16 /* CPM speed */
#define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */
#define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */
#define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */
/* some dimensions */
#define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */
#define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */
#define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */
#define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */
#define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */
#define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */
/* board types */
#define HYMOD_BDTYPE_NONE 0 /* information not present */
#define HYMOD_BDTYPE_IO 1 /* I/O main board */
#define HYMOD_BDTYPE_CLP 2 /* CLP main board */
#define HYMOD_BDTYPE_DSP 3 /* DSP main board */
#define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */
#define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */
#define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */
#define HYMOD_BDTYPE_MAX 7 /* first invalid value */
/* Xilinx fpga types */
#define HYMOD_XTYP_NONE 0 /* information not present */
#define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */
#define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */
#define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */
#define HYMOD_XTYP_MAX 4 /* first invalid value */
/* Xilinx fpga speeds */
#define HYMOD_XSPD_NONE 0 /* information not present */
#define HYMOD_XSPD_SIX 1
#define HYMOD_XSPD_SEVEN 2
#define HYMOD_XSPD_EIGHT 3
#define HYMOD_XSPD_MAX 4 /* first invalid value */
/* Xilinx fpga temperatures */
#define HYMOD_XTMP_NONE 0 /* information not present */
#define HYMOD_XTMP_COM 1
#define HYMOD_XTMP_IND 2
#define HYMOD_XTMP_MAX 3 /* first invalid value */
/* Xilinx fpga grades */
#define HYMOD_XTMP_NONE 0 /* information not present */
#define HYMOD_XTMP_NORMAL 1
#define HYMOD_XTMP_ENGSAMP 2
#define HYMOD_XTMP_MAX 3 /* first invalid value */
/* CPU types */
#define HYMOD_CPUTYPE_NONE 0 /* information not present */
#define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */
#define HYMOD_CPUTYPE_MAX 2 /* first invalid value */
/* CPU/BUS/CPM clock speeds */
#define HYMOD_CLKSPD_NONE 0 /* information not present */
#define HYMOD_CLKSPD_33MHZ 1
#define HYMOD_CLKSPD_66MHZ 2
#define HYMOD_CLKSPD_100MHZ 3
#define HYMOD_CLKSPD_133MHZ 4
#define HYMOD_CLKSPD_166MHZ 5
#define HYMOD_CLKSPD_200MHZ 6
#define HYMOD_CLKSPD_MAX 7 /* first invalid value */
/* high speed serial chip types */
#define HYMOD_HSSTYPE_NONE 0 /* information not present */
#define HYMOD_HSSTYPE_AMCC52064 1
#define HYMOD_HSSTYPE_MAX 2 /* first invalid value */
/* a date (yyyy-mm-dd) */
typedef
struct {
unsigned short year;
unsigned char month;
unsigned char day;
}
hymod_date_t;
/* describes a Xilinx fpga */
typedef
struct {
unsigned char type; /* chip type */
unsigned char speed; /* chip speed rating */
unsigned char temp; /* chip temperature rating */
unsigned char grade; /* chip grade */
}
hymod_xlx_t;
/* describes a Motorola embedded processor */
typedef
struct {
unsigned char type; /* CPU type */
unsigned char cpuspd; /* speed of the PowerPC core */
unsigned char busspd; /* speed of the system and 60x bus */
unsigned char cpmspd; /* speed of the CPM co-processor */
}
hymod_mpc_t;
/* info about high-speed (1Gbit) serial interface */
typedef
struct {
unsigned char type; /* high-speed serial chip type */
unsigned char nchin; /* number of input channels mounted */
unsigned char nchout; /* number of output channels mounted */
}
hymod_hss_t;
/*
* this defines the contents of the serial eeprom that exists on every
* hymod board, including mezzanine boards (the serial eeprom will be
* faked for early development boards that don't have one)
*/
typedef
struct {
unsigned char valid:1; /* contents of this struct is valid */
unsigned char ver:7; /* eeprom contents version */
unsigned char bdtype; /* board type */
unsigned char bdrev; /* board revision */
unsigned char batchlen; /* length of batch string below */
unsigned long serno; /* serial number */
hymod_date_t date; /* manufacture date */
unsigned char batch[32]; /* manufacturer specific batch id */
unsigned char nsdram; /* # of ram "banks" */
unsigned char nflash; /* # of flash "banks" */
unsigned char nzbt; /* # of ZBT rams */
unsigned char nxlx; /* # of Xilinx fpgas */
unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */
unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */
unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */
hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */
hymod_mpc_t mpc; /* Motorola MPC CPU info */
hymod_hss_t hss; /* high-speed serial info */
}
hymod_eeprom_t;
/*
* this defines a region in the processor's physical address space
*/
typedef
struct {
unsigned long exists:1; /* 1 if the region exists, 0 if not */
unsigned long size:31; /* size in bytes */
unsigned long base; /* base address */
}
xlx_prgn_t;
/*
* this defines where the various Xilinx fpga access regions are mapped
* into the physical address space of the processor
*/
typedef
struct {
xlx_prgn_t prog; /* program access region */
xlx_prgn_t reg; /* register access region */
xlx_prgn_t port; /* port access region */
}
xlx_mmap_t;
/*
* this defines which 8260 i/o port pins are connected to the various
* signals required for programming a Xilinx fpga
*/
typedef
struct {
iopin_t prog_pin; /* assert for >= 300ns to program */
iopin_t init_pin; /* goes high when fpga is cleared */
iopin_t done_pin; /* goes high when program is done */
iopin_t enable_pin; /* some fpgas need enabling */
}
xlx_iopins_t;
/* all info about one Xilinx chip */
typedef
struct {
xlx_mmap_t mmap;
xlx_iopins_t iopins;
unsigned long irq:8; /* h/w intr req number for this fpga */
}
xlx_info_t;
/* all info about one hymod board */
typedef
struct {
hymod_eeprom_t eeprom;
xlx_info_t xlx[HYMOD_MAX_XLX];
}
hymod_board_t;
/*
* this defines the configuration information of a hymod board-set
* (main board + possible mezzanine board). In future, there may be
* more than one mezzanine board (stackable?) - if so, add a "mezz2"
* field, and so on... or make mezz an array?
*/
typedef
struct {
unsigned long ver:8; /* version control */
hymod_board_t main; /* main board info */
hymod_board_t mezz; /* mezzanine board info */
unsigned long crc; /* ensures kernel and boot prom agree */
}
hymod_conf_t;
#endif /* _HYMOD_H_ */

91
board/hymod/input.c
View File

@ -1,91 +0,0 @@
/*
* (C) Copyright 2003
* Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <bootretry.h>
#include <cli.h>
int
hymod_get_serno (const char *prompt)
{
for (;;) {
int n, serno;
char *p;
bootretry_reset_cmd_timeout();
n = cli_readline(prompt);
if (n < 0)
return (n);
if (n == 0)
continue;
serno = (int) simple_strtol (console_buffer, &p, 10);
if (p > console_buffer && *p == '\0' && serno > 0)
return (serno);
printf ("Invalid number (%s) - please re-enter\n",
console_buffer);
}
}
int
hymod_get_ethaddr (void)
{
for (;;) {
int n;
bootretry_reset_cmd_timeout();
n = cli_readline("Enter board ethernet address: ");
if (n < 0)
return (n);
if (n == 0)
continue;
if (n == 17) {
int i;
char *p, *q;
/* see if it looks like an ethernet address */
p = console_buffer;
for (i = 0; i < 6; i++) {
char term = (i == 5 ? '\0' : ':');
(void)simple_strtol (p, &q, 16);
if ((q - p) != 2 || *q++ != term)
break;
p = q;
}
if (i == 6) {
/* it looks ok - set it */
printf ("Setting ethernet addr to %s\n",
console_buffer);
setenv ("ethaddr", console_buffer);
puts ("Remember to do a 'saveenv' to "
"make it permanent\n");
return (0);
}
}
printf ("Invalid ethernet addr (%s) - please re-enter\n",
console_buffer);
}
}

132
board/hymod/u-boot.lds
View File

@ -1,132 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8260/start.o (.text)
/*
common/dlmalloc.o (.text)
arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
. = env_offset;
*/
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
. = ALIGN(256 * 1024);
.ppcenv :
{
common/env_embedded.o (.ppcenv)
}
. = ALIGN(4);
__bss_end = . ;
PROVIDE (end = .);
}

121
board/hymod/u-boot.lds.debug
View File

@ -1,121 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
__bss_end = . ;
PROVIDE (end = .);
}

9
board/icu862/Kconfig
View File

@ -1,9 +0,0 @@
if TARGET_ICU862
config SYS_BOARD
default "icu862"
config SYS_CONFIG_NAME
default "ICU862"
endif

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