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https://github.com/u-boot/u-boot.git
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arm: Remove tt01 board
This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Tom Rini
parent
f73db66d62
commit
0c81f37d9a
@ -244,10 +244,6 @@ config TARGET_MX31PDK
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select CPU_ARM1136
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select SUPPORT_SPL
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config TARGET_TT01
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bool "Support tt01"
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select CPU_ARM1136
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config TARGET_WOODBURN
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bool "Support woodburn"
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select CPU_ARM1136
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@ -764,7 +760,6 @@ source "board/freescale/mx53smd/Kconfig"
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source "board/freescale/vf610twr/Kconfig"
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source "board/gumstix/pepper/Kconfig"
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source "board/h2200/Kconfig"
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source "board/hale/tt01/Kconfig"
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source "board/hisilicon/hikey/Kconfig"
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source "board/imx31_phycore/Kconfig"
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source "board/isee/igep0033/Kconfig"
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@ -1,15 +0,0 @@
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if TARGET_TT01
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config SYS_BOARD
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default "tt01"
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config SYS_VENDOR
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default "hale"
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config SYS_SOC
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default "mx31"
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config SYS_CONFIG_NAME
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default "tt01"
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endif
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@ -1,6 +0,0 @@
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TT01 BOARD
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M: Helmut Raiger <helmut.raiger@hale.at>
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S: Maintained
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F: board/hale/tt01/
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F: include/configs/tt01.h
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F: configs/tt01_defconfig
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@ -1,10 +0,0 @@
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#
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# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at>
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := tt01.o
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obj-y += lowlevel_init.o
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@ -1,16 +0,0 @@
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/*
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* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
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* (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/macro.h>
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.globl lowlevel_init
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lowlevel_init:
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/* Also setup the Peripheral Port Remap register inside the core */
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ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
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mcr p15, 0, r0, c15, c2, 4
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mov pc, lr
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@ -1,243 +0,0 @@
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/*
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* (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
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* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <command.h>
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#include <power/pmic.h>
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#include <fsl_pmic.h>
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#include <mc13783.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define BOARD_STRING "Board: HALE TT-01"
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/* Clock configuration */
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#define CCM_CCMR_SETUP 0x074B0BF5
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static void board_setup_clocks(void)
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{
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struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
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volatile int wait = 0x10000;
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writel(CCM_CCMR_SETUP, &ccm->ccmr);
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while (wait--)
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;
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writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr);
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writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
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/* Set up clock to 532MHz */
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writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
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PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
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PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
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PDR0_MCU_PODF(0), &ccm->pdr0);
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writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12),
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&ccm->mpctl);
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writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1),
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&ccm->spctl);
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}
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/* DRAM configuration */
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#define ESDMISC_MDDR_SETUP 0x00000004
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#define ESDMISC_MDDR_RESET_DL 0x0000000c
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/*
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* decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below:
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* tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
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* tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
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* tRCD = 011, tRC = 010
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* note: all but tWTR (1), tRC (111) are reset defaults,
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* the same values work in the jtag configuration
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*
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* Bluetechnix setup has 0x75e73a (for 128MB) =
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* 0b 0111 0101 1110 0111 0011 1010
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* tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
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* tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
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* tRCD = 011, tRC = 010
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*/
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#define ESDCFG0_MDDR_SETUP 0x006ac73a
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#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
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#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
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ESDCTL_DSIZ(2) | ESDCTL_BL(1))
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#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
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#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
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#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
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#define ESDCTL_RW ESDCTL_SETTINGS
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static void board_setup_sdram(void)
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{
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u32 *pad;
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struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
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/*
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* setup pad control for the controller pins
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* no loopback, no pull, no keeper, no open drain,
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* standard input, standard drive, slow slew rate
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*/
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for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
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pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
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*pad = 0;
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/* set up MX31 DDR Memory Controller */
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writel(ESDMISC_MDDR_SETUP, &esdc->misc);
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writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
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/* perform DDR init sequence for CSD0 */
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writel(ESDCTL_PRECHARGE, &esdc->ctl0);
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writel(0x12344321, CSD0_BASE+0x0f00);
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writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
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writel(0x12344321, CSD0_BASE);
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writel(0x12344321, CSD0_BASE);
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writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
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writeb(0xda, CSD0_BASE+0x33);
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writeb(0xff, CSD0_BASE+0x1000000);
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writel(ESDCTL_RW, &esdc->ctl0);
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writel(0xDEADBEEF, CSD0_BASE);
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writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
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}
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static void tt01_spi3_hw_init(void)
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{
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/* CSPI3 */
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
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/* CSPI3, SS0 = Atlas */
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));
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/* start CSPI3 clock (3 = always on except if PLL off) */
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setbits_le32(CCM_CGR0, 3 << 16);
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}
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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int board_early_init_f(void)
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{
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/* CS4: FPGA incl. network controller */
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struct mxc_weimcs cs4 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
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};
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/* this seems essential, won't start without, but why? */
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writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);
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board_setup_clocks();
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board_setup_sdram();
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mxc_setup_weimcs(4, &cs4);
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/* Setup UART2 and SPI3 pins */
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mx31_uart2_hw_init();
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tt01_spi3_hw_init();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_HW_WATCHDOG
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hw_watchdog_init();
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#endif
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return 0;
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}
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int checkboard(void)
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{
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puts(BOARD_STRING "\n");
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return 0;
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}
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#ifdef CONFIG_MXC_MMC
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int board_mmc_init(bd_t *bis)
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{
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u32 val;
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struct pmic *p;
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int ret;
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/*
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* this is the first driver to use the pmic, so call
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* pmic_init() here. board_late_init() is too late for
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* the MMC driver.
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*/
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ret = pmic_init(I2C_PMIC);
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if (ret)
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return ret;
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p = pmic_get("FSL_PMIC");
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if (!p)
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return -ENODEV;
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/* configure pins for SDHC1 only */
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CMD, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA0, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA1, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA2, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA3, MUX_CTL_FUNC));
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/* turn on power V_MMC1 */
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if (pmic_reg_read(p, REG_MODE_1, &val) < 0)
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pmic_reg_write(p, REG_MODE_1, val | VMMC1EN);
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return mxc_mmc_init(bis);
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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#ifdef CONFIG_CONSOLE_EXTRA_INFO
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void video_get_info_str(int line_number, char *info)
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{
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u32 srev = get_cpu_rev();
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switch (line_number) {
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case 2:
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sprintf(info, " CPU : Freescale i.MX31 rev %d.%d%s at %d MHz",
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(srev & 0xF0) >> 4, (srev & 0x0F),
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((srev & 0x8000) ? " unknown" : ""),
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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break;
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case 3:
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strcpy(info, " " BOARD_STRING);
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break;
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default:
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info[0] = 0;
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}
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}
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#endif
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@ -1,4 +0,0 @@
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CONFIG_ARM=y
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CONFIG_TARGET_TT01=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_SYS_PROMPT="TT01> "
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@ -1,266 +0,0 @@
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/*
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* (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
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* (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* Configuration settings for the HALE TT-01 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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/* High Level Configuration Options */
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#define CONFIG_MX31
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */
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#define CONFIG_SYS_TEXT_BASE 0xA0000000
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/*
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* Physical Memory Map:
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* CS settings are defined by i.MX31:
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* - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
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* - CS0 and CS1 are 128MB each, at A0000000 and A8000000
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* - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
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*
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* HALE set-up of the bluetechnix board for now is:
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* - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
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* - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
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* - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
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* the flash chip is a mirrorbit S29WS256N !
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* - the PSRAM is hooked to CS5 (0xB6000000)
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* - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
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* - 64Mbit = 8MByte (will go away in the production set-up)
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* - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
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* 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
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* - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
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*
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* u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
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* is not used right now. We should be able to reduce the SOM to NAND flash
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* only and boot from there.
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CSD0_BASE
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#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
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/* default load address, 1MB up the road */
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#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
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/* Size of malloc() pool, make sure possible frame buffer fits */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
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/* memtest works on all but the last 1MB (u-boot) and malloc area */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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#define CONFIG_SYS_MEMTEST_END \
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(PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
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/* CFI FLASH driver setup */
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#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
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#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
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#define CONFIG_FLASH_SPANSION_S29WS_N
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/*
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* TODO: Bluetechnix (the supplier of the SOM) did define these values
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* in their original version of u-boot (1.2 or so). This should be
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* reviewed.
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*
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* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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* #define CONFIG_SYS_FLASH_PROTECTION
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*/
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#define CONFIG_SYS_FLASH_BASE CS0_BASE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
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/*
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* FLASH and environment organization, only the Spansion chip is supported:
|
||||
* - it has 254 * 128kB + 8 * 32kB blocks
|
||||
* - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
|
||||
* and 2 sectors with 128k as environment =
|
||||
* A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
|
||||
* - this could be less, but this is only for developer versions of the board
|
||||
* and no-one is going to use the NOR flash anyway.
|
||||
*
|
||||
* Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
|
||||
* way to large, but it avoids ENV overwrite (when updating u-boot) in case
|
||||
* size breaks the next boundary (as it has with 128k).
|
||||
*/
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_SIZE (128 * 1024)
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
|
||||
/* Hardware drivers */
|
||||
|
||||
/*
|
||||
* on TT-01 UART1 pins are used by Audio, so we use UART2
|
||||
* TT-01 implements a hardware that turns off components depending on
|
||||
* the power level. In PL=1 the RS232 transceiver is usually off,
|
||||
* make sure that the transceiver is enabled during PL=1 for testing!
|
||||
*/
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART2_BASE
|
||||
|
||||
#define CONFIG_MXC_SPI
|
||||
#define CONFIG_MXC_GPIO
|
||||
|
||||
/* MC13783 connected to CSPI3 and SS0 */
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_SPI
|
||||
#define CONFIG_POWER_FSL
|
||||
|
||||
#define CONFIG_FSL_PMIC_BUS 2
|
||||
#define CONFIG_FSL_PMIC_CS 0
|
||||
#define CONFIG_FSL_PMIC_CLK 1000000
|
||||
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
|
||||
#define CONFIG_FSL_PMIC_BITLEN 32
|
||||
|
||||
#define CONFIG_RTC_MC13XXX
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
/* console is UART2 on TT-01 */
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* ethernet setup for the onboard smc9118 */
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_SMC911X
|
||||
/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
|
||||
#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000)
|
||||
#define CONFIG_SMC911X_16_BIT
|
||||
|
||||
/* mmc driver */
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_MXC_MMC
|
||||
#define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR
|
||||
|
||||
/* video support */
|
||||
#define CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_MX3
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
/* splash image won't work with NAND boot, use preboot script */
|
||||
#define CONFIG_VIDEO_SW_CURSOR
|
||||
#define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */
|
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */
|
||||
|
||||
/* allow stdin, stdout and stderr variables to redirect output */
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */
|
||||
#define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */
|
||||
#define CONFIG_PREBOOT
|
||||
|
||||
/* allow decompressing max. 4MB */
|
||||
#define CONFIG_VIDEO_BMP_GZIP
|
||||
/* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */
|
||||
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024)
|
||||
|
||||
/*
|
||||
* Command definition
|
||||
*/
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_NAND
|
||||
/*
|
||||
* #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
|
||||
* the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
|
||||
* a software locking scheme.
|
||||
*/
|
||||
#define CONFIG_CMD_BMP
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
/*
|
||||
* currently a default setting for booting via script is implemented
|
||||
* set user to login name and serverip to tftp host, define your
|
||||
* boot behaviour in bootscript.loginname
|
||||
*
|
||||
* TT-01 board specific TFT setup (used by drivers/video/mx3fb.c)
|
||||
*
|
||||
* This set-up is for the L5F30947T04 by Epson, which is
|
||||
* 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync
|
||||
* sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL
|
||||
*/
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"videomode=epson\0" \
|
||||
"epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \
|
||||
"le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \
|
||||
"bootcmd=dhcp bootscript.${user}; source\0"
|
||||
|
||||
#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
/* max number of command args */
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/* MMC boot support */
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
|
||||
#define CONFIG_NAND_MXC
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
|
||||
/*
|
||||
* actually this is nothing someone wants to configure!
|
||||
* CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
|
||||
* is not used by the driver.
|
||||
*/
|
||||
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
|
||||
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
|
||||
#define CONFIG_MXC_NAND_HWECC
|
||||
|
||||
/* the current u-boot driver does not use the nand flash setup! */
|
||||
#define CONFIG_SYS_NAND_LARGEPAGE
|
||||
/*
|
||||
* it's not 16 bit:
|
||||
* #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
|
||||
* the current u-boot mxc_nand.c tries to auto-detect, but this only
|
||||
* reads the boot settings during reset (which might be wrong)
|
||||
*/
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user