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mtd: nand: mxs: reset BCH earlier, too, to avoid NAND startup problems

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It could happen (1 out of 100 times) that NAND did not start up correctly after
warm rebooting, so we end up with various failures or DMA timed out due to a
stalled BCH. When resetting BCH together with GPMI, the issue could not be
observed anymore (after 10000+ reboots). We probably need the consistent state
already before sending commands to NAND. This behaviour was observed in barebox
and kernel, so I assume it affects U-Boot as well. I chose to keep the extra
reset for BCH when changing the flash layout to be on the safe side.

Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Wolfram Sang 2012-12-05 10:48:47 +00:00 committed by Scott Wood
parent ea40a05422
commit 0b38fffbe4
1 changed files with 3 additions and 0 deletions
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3
drivers/mtd/nand/mxs_nand.c
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@ -1058,6 +1058,8 @@ int mxs_nand_init(struct mxs_nand_info *info)
{ {
struct mxs_gpmi_regs *gpmi_regs = struct mxs_gpmi_regs *gpmi_regs =
(struct mxs_gpmi_regs *)MXS_GPMI_BASE; (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
struct mxs_bch_regs *bch_regs =
(struct mxs_bch_regs *)MXS_BCH_BASE;
int i = 0, j; int i = 0, j;
info->desc = malloc(sizeof(struct mxs_dma_desc *) * info->desc = malloc(sizeof(struct mxs_dma_desc *) *
@ -1081,6 +1083,7 @@ int mxs_nand_init(struct mxs_nand_info *info)
/* Reset the GPMI block. */ /* Reset the GPMI block. */
mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg); mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
/* /*
* Choose NAND mode, set IRQ polarity, disable write protection and * Choose NAND mode, set IRQ polarity, disable write protection and