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mtd: nand: atmel: prepare for nand spl boot support
Prepare for nand spl boot support. It supports nand software ECC and hardware PMECC. This patch is take <drivers/mtd/nand/nand_spl_simple.c> as reference. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Bo Shen
Andreas Bießmann
parent
8a45b0ba87
commit
0b0b4f5981
@ -31,6 +31,10 @@
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#ifdef CONFIG_ATMEL_NAND_HW_PMECC
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#ifdef CONFIG_SPL_BUILD
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#undef CONFIG_SYS_NAND_ONFI_DETECTION
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#endif
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struct atmel_nand_host {
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struct pmecc_regs __iomem *pmecc;
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struct pmecc_errloc_regs __iomem *pmerrloc;
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@ -1169,6 +1173,209 @@ static int at91_nand_ready(struct mtd_info *mtd)
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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/* The following code is for SPL */
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static nand_info_t mtd;
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static struct nand_chip nand_chip;
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static int nand_command(int block, int page, uint32_t offs, u8 cmd)
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{
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struct nand_chip *this = mtd.priv;
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int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
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void (*hwctrl)(struct mtd_info *mtd, int cmd,
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unsigned int ctrl) = this->cmd_ctrl;
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while (this->dev_ready(&mtd))
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;
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if (cmd == NAND_CMD_READOOB) {
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offs += CONFIG_SYS_NAND_PAGE_SIZE;
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cmd = NAND_CMD_READ0;
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}
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hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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if (this->options & NAND_BUSWIDTH_16)
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offs >>= 1;
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hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
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hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
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hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
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hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
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#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
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hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
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#endif
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hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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while (this->dev_ready(&mtd))
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;
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return 0;
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}
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static int nand_is_bad_block(int block)
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{
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struct nand_chip *this = mtd.priv;
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nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
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if (this->options & NAND_BUSWIDTH_16) {
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if (readw(this->IO_ADDR_R) != 0xffff)
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return 1;
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} else {
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if (readb(this->IO_ADDR_R) != 0xff)
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return 1;
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}
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return 0;
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}
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#ifdef CONFIG_SPL_NAND_ECC
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static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
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#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
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CONFIG_SYS_NAND_ECCSIZE)
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#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
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static int nand_read_page(int block, int page, void *dst)
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{
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struct nand_chip *this = mtd.priv;
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u_char ecc_calc[ECCTOTAL];
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u_char ecc_code[ECCTOTAL];
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u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
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int eccsize = CONFIG_SYS_NAND_ECCSIZE;
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int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
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int eccsteps = ECCSTEPS;
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int i;
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uint8_t *p = dst;
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nand_command(block, page, 0, NAND_CMD_READ0);
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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if (this->ecc.mode != NAND_ECC_SOFT)
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this->ecc.hwctl(&mtd, NAND_ECC_READ);
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this->read_buf(&mtd, p, eccsize);
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this->ecc.calculate(&mtd, p, &ecc_calc[i]);
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}
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this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
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for (i = 0; i < ECCTOTAL; i++)
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ecc_code[i] = oob_data[nand_ecc_pos[i]];
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eccsteps = ECCSTEPS;
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p = dst;
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
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this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
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return 0;
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}
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#else
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static int nand_read_page(int block, int page, void *dst)
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{
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struct nand_chip *this = mtd.priv;
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nand_command(block, page, 0, NAND_CMD_READ0);
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atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
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return 0;
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}
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#endif /* CONFIG_SPL_NAND_ECC */
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int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
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{
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unsigned int block, lastblock;
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unsigned int page;
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block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
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lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
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page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
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while (block <= lastblock) {
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if (!nand_is_bad_block(block)) {
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while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
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nand_read_page(block, page, dst);
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dst += CONFIG_SYS_NAND_PAGE_SIZE;
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page++;
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}
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page = 0;
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} else {
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lastblock++;
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}
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block++;
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}
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return 0;
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}
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int at91_nand_wait_ready(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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udelay(this->chip_delay);
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return 0;
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}
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int board_nand_init(struct nand_chip *nand)
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{
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int ret = 0;
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nand->ecc.mode = NAND_ECC_SOFT;
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#ifdef CONFIG_SYS_NAND_DBW_16
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nand->options = NAND_BUSWIDTH_16;
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nand->read_buf = nand_read_buf16;
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#else
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nand->read_buf = nand_read_buf;
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#endif
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nand->cmd_ctrl = at91_nand_hwcontrol;
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#ifdef CONFIG_SYS_NAND_READY_PIN
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nand->dev_ready = at91_nand_ready;
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#else
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nand->dev_ready = at91_nand_wait_ready;
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#endif
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nand->chip_delay = 20;
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#ifdef CONFIG_ATMEL_NAND_HWECC
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#ifdef CONFIG_ATMEL_NAND_HW_PMECC
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ret = atmel_pmecc_nand_init_params(nand, &mtd);
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#endif
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#endif
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return ret;
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}
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void nand_init(void)
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{
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mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
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mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
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mtd.priv = &nand_chip;
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nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
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nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
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board_nand_init(&nand_chip);
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#ifdef CONFIG_SPL_NAND_ECC
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if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
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nand_chip.ecc.calculate = nand_calculate_ecc;
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nand_chip.ecc.correct = nand_correct_data;
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}
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#endif
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if (nand_chip.select_chip)
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nand_chip.select_chip(&mtd, 0);
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}
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void nand_deselect(void)
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{
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if (nand_chip.select_chip)
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nand_chip.select_chip(&mtd, -1);
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}
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#else
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#ifndef CONFIG_SYS_NAND_BASE_LIST
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#endif
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@ -1227,3 +1434,4 @@ void board_nand_init(void)
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dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
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i);
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}
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#endif /* CONFIG_SPL_BUILD */
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@ -21,10 +21,16 @@
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* at the same time, so do it here. When all drivers are
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* converted, this will go away.
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*/
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#ifdef CONFIG_SPL_BUILD
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#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_FSL_IFC)
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#define CONFIG_SYS_NAND_SELF_INIT
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#endif
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#else
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#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\
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|| defined(CONFIG_NAND_FSL_IFC)
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#define CONFIG_SYS_NAND_SELF_INIT
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#endif
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#endif
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extern void nand_init(void);
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