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Merge tag 'u-boot-rockchip-20230509' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

Browse Source 
- Rockchip NFC driver update and dev addr pointer api update;
- use standard dr_mode for usb driver;
- rock pi boards dts update;
- Add rk3566 Anbernic boards;
- Misc fixes for drivers;
This commit is contained in:
Tom Rini 2023-05-09 12:45:49 -04:00
commit 0a9a4384c1
139 changed files with 3061 additions and 418 deletions
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8
Kconfig
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@ -397,11 +397,19 @@ endif # EXPERT
config PHYS_64BIT
bool "64bit physical address support"
select FDT_64BIT
help
Say Y here to support 64bit physical memory address.
This can be used not only for 64bit SoCs, but also for
large physical address extension on 32bit SoCs.
config FDT_64BIT
bool "64bit fdt address support"
help
Say Y here to support 64bit fdt addresses.
This can be used not only for 64bit SoCs, but also
for large address extensions on 32bit SoCs.
config HAS_ROM
bool
select BINMAN

6
arch/arm/dts/Makefile
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@ -123,6 +123,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-nanopi-r2c.dtb \
rk3328-nanopi-r2s.dtb \
rk3328-roc-cc.dtb \
rk3328-rock64.dtb \
@ -157,16 +158,17 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-puma-haikou.dtb \
rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \
rk3399-rock-4c-plus.dtb \
rk3399-rock-pi-4a.dtb \
rk3399-rock-pi-4b.dtb \
rk3399-rock-pi-4c.dtb \
rk3399-rock960.dtb \
rk3399-rockpro64.dtb \
rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-evb.dtb \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \

3
arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi Normal file
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@ -0,0 +1,3 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "rk3328-nanopi-r2s-u-boot.dtsi"

40
arch/arm/dts/rk3328-nanopi-r2c.dts Normal file
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@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*
* Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
*/
/dts-v1/;
#include "rk3328-nanopi-r2s.dts"
/ {
model = "FriendlyElec NanoPi R2C";
compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
};
&gmac2io {
phy-handle = <&yt8521s>;
tx_delay = <0x22>;
rx_delay = <0x12>;
mdio {
/delete-node/ ethernet-phy@1;
yt8521s: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
motorcomm,clk-out-frequency-hz = <125000000>;
motorcomm,keep-pll-enabled;
motorcomm,auto-sleep-disabled;
pinctrl-0 = <&eth_phy_reset_pin>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
};
};
};

5
arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi Normal file
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@ -0,0 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Radxa Limited
*/
#include "rk3399-rock-pi-4-u-boot.dtsi"

709
arch/arm/dts/rk3399-rock-4c-plus.dts Normal file
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@ -0,0 +1,709 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2019 Radxa Limited
* Copyright (c) 2022 Amarula Solutions(India)
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "rk3399.dtsi"
#include "rk3399-t-opp.dtsi"
/ {
model = "Radxa ROCK 4C+";
compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
chosen {
stdout-path = "serial2:1500000n8";
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&user_led1 &user_led2>;
/* USER_LED1 */
led-0 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
/* USER_LED2 */
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
vcc_3v3: vcc-3v3-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
};
vcc3v3_phy1: vcc3v3-phy1-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_phy1";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3>;
};
vcc5v0_host1: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host1";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_host0_s0>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_typec: vcc5v0-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec0_en>;
regulator-name = "vcc5v0_typec";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
vdd_log: vdd-log-regulator {
compatible = "regulator-fixed";
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
vin-supply = <&vcc5v0_sys>;
};
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc3v3_phy1>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x2a>;
rx_delay = <0x21>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vcc_0v9_s0>;
avdd-1v8-supply = <&vcc_1v8_s0>;
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
i2c-scl-falling-time-ns = <30>;
i2c-scl-rising-time-ns = <180>;
clock-frequency = <400000>;
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc_buck5_s3>;
vcc6-supply = <&vcc_buck5_s3>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
regulators {
vdd_center: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_center";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_cpu_l";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc3v3_sys: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <0x2>;
regulator-name = "vcc3v3_sys";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_buck5_s3: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_buck5_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_0v9_s3: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vcc_0v9_s3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s3: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_0v9_s0: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vcc_0v9_s0";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vcc_1v8_s0: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_mipi: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_mipi";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5_s0: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc_1v5_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0_s0: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_3v0_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_sdio_s0: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sdio_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_cam: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_cam";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc5v0_host0_s0: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc5v0_host0_s0";
regulator-state-mem {
regulator-on-in-suspend;
};
};
lcd_3v3: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "lcd_3v3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
regulator-compatible = "fan53555-reg";
pinctrl-0 = <&vsel1_gpio>;
vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
regulator-compatible = "fan53555-reg";
pinctrl-0 = <&vsel2_gpio>;
vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-initial-mode = <1>; /* 1:force PWM 2:auto */
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2s2 {
status = "okay";
};
&io_domains {
audio-supply = <&vcc_1v8_s0>;
bt656-supply = <&vcc_3v0_s0>;
gpio1830-supply = <&vcc_3v0_s0>;
sdmmc-supply = <&vcc_sdio_s0>;
status = "okay";
};
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
user_led1: user-led1 {
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
user_led2: user-led2 {
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_gpio: vsel1-gpio {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_gpio: vsel2-gpio {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdmmc {
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <4 8 1 &pcfg_pull_up_8ma>,
<4 9 1 &pcfg_pull_up_8ma>,
<4 10 1 &pcfg_pull_up_8ma>,
<4 11 1 &pcfg_pull_up_8ma>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins = <4 12 1 &pcfg_pull_none_18ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <4 13 1 &pcfg_pull_up_8ma>;
};
};
usb-typec {
vcc5v0_typec0_en: vcc5v0-typec-en {
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
wifi {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0_s0>;
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcc_1v8_s3>;
};
&sdhci {
max-frequency = <150000000>;
bus-width = <8>;
mmc-hs400-1_8v;
non-removable;
mmc-hs400-enhanced-strobe;
status = "okay";
};
&sdio0 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
clock-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <800>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
vqmmc-supply = <&vcc_sdio_s0>;
status = "okay";
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vcc5v0_host1>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host1>;
status = "okay";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm4345c5";
clocks = <&rk809 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
max-speed = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8_s3>;
};
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
extcon = <&u2phy0>;
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "host";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

239
arch/arm/dts/rk3399-rock-pi-4.dtsi
View File

@ -6,14 +6,15 @@
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
aliases {
mmc0 = &sdmmc;
mmc1 = &sdhci;
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
chosen {
@ -27,6 +28,20 @@
#clock-cells = <0>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&user_led2>;
/* USER_LED2 */
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
@ -36,6 +51,40 @@
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
sound: sound {
compatible = "audio-graph-card";
label = "Analog";
dais = <&i2s0_p0>;
};
sound-dit {
compatible = "audio-graph-card";
label = "SPDIF";
dais = <&spdif_p0>;
};
spdif-dit {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
port {
dit_p0_0: endpoint {
remote-endpoint = <&spdif_p0_0>;
};
};
};
vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec_en>;
regulator-name = "vbus_typec";
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
vcc12v_dcin: dc-12v {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@ -45,23 +94,13 @@
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc-sys {
vcc3v3_lan: vcc3v3-lan-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-name = "vcc3v3_lan";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc_0v9: vcc-0v9 {
compatible = "regulator-fixed";
regulator-name = "vcc_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
};
@ -98,35 +137,35 @@
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_typec: vcc5v0-typec-regulator {
vcc5v0_sys: vcc-sys {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec_en>;
regulator-name = "vcc5v0_typec";
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
vcc_lan: vcc3v3-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_lan";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc_0v9: vcc-0v9 {
compatible = "regulator-fixed";
regulator-name = "vcc_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc3v3_sys>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vcc5v0_sys>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
vin-supply = <&vcc5v0_sys>;
};
};
@ -162,7 +201,7 @@
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_lan>;
phy-supply = <&vcc3v3_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
@ -180,6 +219,8 @@
};
&hdmi {
avdd-0v9-supply = <&vcca0v9_hdmi>;
avdd-1v8-supply = <&vcca1v8_hdmi>;
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
@ -267,8 +308,8 @@
};
};
vcc1v8_codec: LDO_REG1 {
regulator-name = "vcc1v8_codec";
vcca1v8_codec: LDO_REG1 {
regulator-name = "vcca1v8_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
@ -278,8 +319,8 @@
};
};
vcc1v8_hdmi: LDO_REG2 {
regulator-name = "vcc1v8_hdmi";
vcca1v8_hdmi: LDO_REG2 {
regulator-name = "vcca1v8_hdmi";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
@ -336,8 +377,8 @@
};
};
vcc0v9_hdmi: LDO_REG7 {
regulator-name = "vcc0v9_hdmi";
vcca0v9_hdmi: LDO_REG7 {
regulator-name = "vcca0v9_hdmi";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
@ -422,6 +463,20 @@
i2c-scl-rising-time-ns = <300>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
es8316: codec@11 {
compatible = "everest,es8316";
reg = <0x11>;
clocks = <&cru SCLK_I2S_8CH_OUT>;
clock-names = "mclk";
#sound-dai-cells = <0>;
port {
es8316_p0_0: endpoint {
remote-endpoint = <&i2s0_p0_0>;
};
};
};
};
&i2c3 {
@ -441,12 +496,19 @@
rockchip,capture-channels = <2>;
rockchip,playback-channels = <2>;
status = "okay";
i2s0_p0: port {
i2s0_p0_0: endpoint {
dai-format = "i2s";
mclk-fs = <256>;
remote-endpoint = <&es8316_p0_0>;
};
};
};
&i2s1 {
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
};
&i2s2 {
@ -454,21 +516,10 @@
};
&io_domains {
status = "okay";
audio-supply = <&vcca1v8_codec>;
bt656-supply = <&vcc_3v0>;
audio-supply = <&vcc_3v0>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
};
&pmu_io_domains {
status = "okay";
pmu1830-supply = <&vcc_3v0>;
};
&pcie_phy {
sdmmc-supply = <&vcc_sdio>;
status = "okay";
};
@ -483,6 +534,10 @@
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
@ -498,12 +553,42 @@
};
};
es8316 {
hp_detect: hp-detect {
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
hp_int: hp-int {
rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
user_led2: user-led2 {
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio0 {
sdio0_bus4: sdio0-bus4 {
rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>,
@ -521,20 +606,6 @@
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb-typec {
vcc5v0_typec_en: vcc5v0-typec-en {
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
@ -558,6 +629,11 @@
};
};
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0>;
status = "okay";
};
&pwm2 {
status = "okay";
};
@ -568,6 +644,14 @@
vref-supply = <&vcc_1v8>;
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&sdio0 {
#address-cells = <1>;
#size-cells = <0>;
@ -595,12 +679,13 @@
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
&spdif {
spdif_p0: port {
spdif_p0_0: endpoint {
remote-endpoint = <&dit_p0_0>;
};
};
};
&tcphy0 {
@ -675,15 +760,15 @@
status = "okay";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "host";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";

0
arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi → arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi
View File

46
arch/arm/dts/rk3399-rock-pi-4b.dts
View File

@ -1,46 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
* Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
*/
/dts-v1/;
#include "rk3399-rock-pi-4.dtsi"
/ {
model = "Radxa ROCK Pi 4B";
compatible = "radxa,rockpi4b", "radxa,rockpi4", "rockchip,rk3399";
aliases {
mmc2 = &sdio0;
};
};
&sdio0 {
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&uart0 {
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "ext_clock";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
};
};

20
arch/arm/dts/rk3399-rock-pi-4c.dts
View File

@ -17,6 +17,13 @@
};
};
&es8316 {
pinctrl-0 = <&hp_detect &hp_int>;
pinctrl-names = "default";
interrupt-parent = <&gpio1>;
interrupts = <RK_PA1 IRQ_TYPE_LEVEL_HIGH>;
};
&sdio0 {
status = "okay";
@ -24,25 +31,32 @@
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sound {
hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
};
&uart0 {
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
compatible = "brcm,bcm4345c5";
clocks = <&rk808 1>;
clock-names = "ext_clock";
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
max-speed = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
};
};

114
arch/arm/dts/rk3399-t-opp.dtsi Normal file
View File

@ -0,0 +1,114 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2022 Radxa Limited
*/
/ {
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <875000 875000 1250000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <875000 875000 1250000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <900000 900000 1250000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <975000 975000 1250000>;
};
};
cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <875000 875000 1250000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <875000 875000 1250000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <875000 875000 1250000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <925000 925000 1250000>;
};
opp04 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1000000 1000000 1250000>;
};
opp05 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1075000 1075000 1250000>;
};
opp06 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <1150000 1150000 1250000>;
};
};
gpu_opp_table: opp-table-2 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <875000 875000 1150000>;
};
opp01 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <875000 875000 1150000>;
};
opp02 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <875000 875000 1150000>;
};
opp03 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <975000 975000 1150000>;
};
};
};
&cpu_l0 {
operating-points-v2 = <&cluster0_opp>;
};
&cpu_l1 {
operating-points-v2 = <&cluster0_opp>;
};
&cpu_l2 {
operating-points-v2 = <&cluster0_opp>;
};
&cpu_l3 {
operating-points-v2 = <&cluster0_opp>;
};
&cpu_b0 {
operating-points-v2 = <&cluster1_opp>;
};
&cpu_b1 {
operating-points-v2 = <&cluster1_opp>;
};
&gpu {
operating-points-v2 = <&gpu_opp_table>;
};

86
arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi Normal file
View File

@ -0,0 +1,86 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk356x-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = "same-as-spl", &sdmmc1, &sdmmc0;
};
rng: rng@fe388000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xfe388000 0x0 0x2000>;
status = "okay";
};
};
&cru {
assigned-clocks =
<&pmucru CLK_RTC_32K>,
<&pmucru PLL_PPLL>,
<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
<&cru PLL_GPLL>,
<&cru ACLK_BUS>, <&cru PCLK_BUS>,
<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
<&cru HCLK_TOP>, <&cru PCLK_TOP>,
<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
<&cru CPLL_500M>, <&cru CPLL_333M>,
<&cru CPLL_250M>, <&cru CPLL_125M>,
<&cru CPLL_100M>, <&cru CPLL_62P5M>,
<&cru CPLL_50M>, <&cru CPLL_25M>;
assigned-clock-rates =
<32768>,
<200000000>,
<100000000>, <1000000000>,
<1188000000>,
<150000000>, <100000000>,
<500000000>, <400000000>,
<150000000>, <100000000>,
<300000000>, <150000000>,
<500000000>, <333333333>,
<250000000>, <125000000>,
<100000000>, <62500000>,
<50000000>, <25000000>;
assigned-clock-parents =
<&pmucru CLK_RTC32K_FRAC>;
};
&i2c2 {
status = "okay";
};
&pmucru {
assigned-clocks = <&pmucru SCLK_32K_IOE>;
assigned-clock-parents = <&pmucru CLK_RTC_32K>;
};
/*
* We don't need the clocks, but if they are present they may cause
* probing to fail so we remove them for U-Boot.
*/
&rk817 {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ clocks;
/delete-property/ clock-names;
};
&sdhci {
pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
<&emmc_datastrobe>, <&emmc_rstnout>;
pinctrl-names = "default";
bus-width = <8>;
max-frequency = <200000000>;
mmc-hs200-1_8v;
non-removable;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&uart2 {
clock-frequency = <24000000>;
bootph-all;
status = "okay";
};

18
arch/arm/dts/rk3566-anbernic-rgxx3.dts Normal file
View File

@ -0,0 +1,18 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3566-anbernic-rgxx3.dtsi"
/ {
/*
* Note this is a pseudo-model that doesn't exist in mainline Linux.
* This model is used for all RGXX3 devices and the board.c file will
* set the correct dtb name for loading mainline Linux automatically.
*/
model = "RGXX3";
compatible = "anbernic,rg353m", "anbernic,rg353p",
"anbernic,rg353v", "anbernic,rg353vs",
"anbernic,rg503", "rockchip,rk3566";
};

786
arch/arm/dts/rk3566-anbernic-rgxx3.dtsi Normal file
View File

@ -0,0 +1,786 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3566.dtsi"
/ {
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
adc-joystick {
compatible = "adc-joystick";
io-channels = <&adc_mux 0>,
<&adc_mux 1>,
<&adc_mux 2>,
<&adc_mux 3>;
pinctrl-0 = <&joy_mux_en>;
pinctrl-names = "default";
poll-interval = <60>;
#address-cells = <1>;
#size-cells = <0>;
axis@0 {
reg = <0>;
abs-flat = <32>;
abs-fuzz = <32>;
abs-range = <1023 15>;
linux,code = <ABS_X>;
};
axis@1 {
reg = <1>;
abs-flat = <32>;
abs-fuzz = <32>;
abs-range = <15 1023>;
linux,code = <ABS_RX>;
};
axis@2 {
reg = <2>;
abs-flat = <32>;
abs-fuzz = <32>;
abs-range = <15 1023>;
linux,code = <ABS_Y>;
};
axis@3 {
reg = <3>;
abs-flat = <32>;
abs-fuzz = <32>;
abs-range = <1023 15>;
linux,code = <ABS_RY>;
};
};
adc_keys: adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <60>;
/*
* Button is mapped to F key in BSP kernel, but
* according to input guidelines it should be mode.
*/
button-mode {
label = "MODE";
linux,code = <BTN_MODE>;
press-threshold-microvolt = <1750>;
};
};
adc_mux: adc-mux {
compatible = "io-channel-mux";
channels = "left_x", "right_x", "left_y", "right_y";
#io-channel-cells = <1>;
io-channels = <&saradc 3>;
io-channel-names = "parent";
mux-controls = <&gpio_mux>;
settle-time-us = <100>;
};
gpio_keys_control: gpio-keys-control {
compatible = "gpio-keys";
pinctrl-0 = <&btn_pins_ctrl>;
pinctrl-names = "default";
button-b {
gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>;
label = "SOUTH";
linux,code = <BTN_SOUTH>;
};
button-down {
gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
label = "DPAD-DOWN";
linux,code = <BTN_DPAD_DOWN>;
};
button-l1 {
gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
label = "TL";
linux,code = <BTN_TL>;
};
button-l2 {
gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
label = "TL2";
linux,code = <BTN_TL2>;
};
button-select {
gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>;
label = "SELECT";
linux,code = <BTN_SELECT>;
};
button-start {
gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;
label = "START";
linux,code = <BTN_START>;
};
button-thumbl {
gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
label = "THUMBL";
linux,code = <BTN_THUMBL>;
};
button-thumbr {
gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
label = "THUMBR";
linux,code = <BTN_THUMBR>;
};
button-up {
gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
label = "DPAD-UP";
linux,code = <BTN_DPAD_UP>;
};
button-x {
gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
label = "NORTH";
linux,code = <BTN_NORTH>;
};
};
gpio_keys_vol: gpio-keys-vol {
compatible = "gpio-keys";
autorepeat;
pinctrl-0 = <&btn_pins_vol>;
pinctrl-names = "default";
button-vol-down {
gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
label = "VOLUMEDOWN";
linux,code = <KEY_VOLUMEDOWN>;
};
button-vol-up {
gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
label = "VOLUMEUP";
linux,code = <KEY_VOLUMEUP>;
};
};
gpio_mux: mux-controller {
compatible = "gpio-mux";
mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>,
<&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
#mux-control-cells = <0>;
};
hdmi-con {
compatible = "hdmi-connector";
ddc-i2c-bus = <&i2c5>;
type = "c";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds: gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
green_led: led-0 {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
function = LED_FUNCTION_POWER;
gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
};
amber_led: led-1 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_CHARGING;
gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
retain-state-suspended;
};
red_led: led-2 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk817 1>;
clock-names = "ext_clock";
pinctrl-0 = <&wifi_enable_h>;
pinctrl-names = "default";
post-power-on-delay-ms = <200>;
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
};
vcc3v3_lcd0_n: regulator-vcc3v3-lcd0 {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&vcc_lcd_h>;
pinctrl-names = "default";
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_lcd0_n";
vin-supply = <&vcc_3v3>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_sys: regulator-vcc-sys {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3800000>;
regulator-max-microvolt = <3800000>;
regulator-name = "vcc_sys";
};
vcc_wifi: regulator-vcc-wifi {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&vcc_wifi_h>;
pinctrl-names = "default";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_wifi";
};
vibrator: pwm-vibrator {
compatible = "pwm-vibrator";
pwm-names = "enable";
pwms = <&pwm5 0 1000000000 0>;
};
};
&combphy1 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c5>;
pinctrl-0 = <&hdmitxm0_cec>;
pinctrl-names = "default";
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
clock-names = "mclk";
clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
#clock-cells = <1>;
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_mclk>, <&pmic_int_l>;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc_sys>;
vcc9-supply = <&dcdc_boost>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_gpu: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_gpu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v3: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_3v3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca1v8_pmu: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdda_0v9: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda_0v9";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_1v8: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc1v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc2v8_dvp: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
dcdc_boost: BOOST {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <4700000>;
regulator-max-microvolt = <5400000>;
regulator-name = "boost";
regulator-state-mem {
regulator-off-in-suspend;
};
};
otg_switch: OTG_SWITCH {
regulator-name = "otg_switch";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu: regulator@40 {
compatible = "fcs,fan53555";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>;
regulator-init-microvolt = <900000>;
regulator-name = "vdd_cpu";
regulator-ramp-delay = <2300>;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c1 {
/* Unknown/unused device at 0x3c */
status = "disabled";
};
&i2c5 {
pinctrl-0 = <&i2c5m1_xfer>;
pinctrl-names = "default";
status = "okay";
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
pinctrl-0 = <&i2s1m0_sclktx
&i2s1m0_lrcktx
&i2s1m0_sdi0
&i2s1m0_sdo0>;
pinctrl-names = "default";
rockchip,trcm-sync-tx-only;
status = "okay";
};
&pinctrl {
gpio-btns {
btn_pins_ctrl: btn-pins-ctrl {
rockchip,pins =
<3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
};
btn_pins_vol: btn-pins-vol {
rockchip,pins =
<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
gpio-led {
led_pins: led-pins {
rockchip,pins =
<0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>,
<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>,
<0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
joy-mux {
joy_mux_en: joy-mux-en {
rockchip,pins =
<0 RK_PB5 RK_FUNC_GPIO &pcfg_output_low>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins =
<4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
vcc3v3-lcd {
vcc_lcd_h: vcc-lcd-h {
rockchip,pins =
<0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
vcc-wifi {
vcc_wifi_h: vcc-wifi-h {
rockchip,pins =
<0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
status = "okay";
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc1v8_dvp>;
vccio7-supply = <&vcc_3v3>;
};
&pwm5 {
status = "okay";
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
pinctrl-names = "default";
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&sdmmc1 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &sdmmc1_det>;
pinctrl-names = "default";
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc1v8_dvp>;
status = "okay";
};
&sdmmc2 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
pinctrl-names = "default";
vmmc-supply = <&vcc_wifi>;
vqmmc-supply = <&vcca1v8_pmu>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart1 {
pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt";
device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
};
};
&uart2 {
status = "okay";
};
/*
* Lack the schematics to verify, but port works as a peripheral
* (and not a host or OTG port).
*/
&usb_host0_xhci {
dr_mode = "peripheral";
phys = <&usb2phy0_otg>;
phy-names = "usb2-phy";
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
phy-names = "usb2-phy", "usb3-phy";
phys = <&usb2phy1_host>, <&combphy1 PHY_TYPE_USB3>;
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_otg {
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

1
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
View File

@ -9,7 +9,6 @@
/ {
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
};
};

2
arch/arm/mach-mvebu/cpu.c
View File

@ -630,7 +630,7 @@ int board_xhci_enable(fdt_addr_t base)
{
const struct mbus_dram_target_info *dram;
printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
printf("MVEBU XHCI INIT controller @ 0x%llx\n", (fdt64_t)base);
dram = mvebu_mbus_dram_info();
xhci_mvebu_mbus_config((void __iomem *)base, dram);

4
arch/arm/mach-mvebu/system-controller.c
View File

@ -71,8 +71,8 @@ static int mvebu_reset_of_to_plat(struct udevice *dev)
{
struct mvebu_reset_data *data = dev_get_priv(dev);
data->base = (void *)dev_read_addr(dev);
if ((fdt_addr_t)data->base == FDT_ADDR_T_NONE)
data->base = dev_read_addr_ptr(dev);
if (!data->base)
return -EINVAL;
return 0;

13
arch/arm/mach-rockchip/board.c
View File

@ -212,6 +212,7 @@ void enable_caches(void)
#include <usb.h>
#if defined(CONFIG_USB_GADGET_DWC2_OTG)
#include <linux/usb/otg.h>
#include <usb/dwc2_udc.h>
static struct dwc2_plat_otg_data otg_data = {
@ -223,18 +224,24 @@ static struct dwc2_plat_otg_data otg_data = {
int board_usb_init(int index, enum usb_init_type init)
{
ofnode node;
const char *mode;
bool matched = false;
/* find the usb_otg node */
node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
while (ofnode_valid(node)) {
mode = ofnode_read_string(node, "dr_mode");
if (mode && strcmp(mode, "otg") == 0) {
switch (usb_get_dr_mode(node)) {
case USB_DR_MODE_OTG:
case USB_DR_MODE_PERIPHERAL:
matched = true;
break;
default:
break;
}
if (matched)
break;
node = ofnode_by_compatible(node, "snps,dwc2");
}
if (!matched) {

121
arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
View File

@ -6,7 +6,10 @@
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
#include <log.h>
#include <malloc.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
@ -25,6 +28,103 @@ U_BOOT_DRIVER(syscon_rk3288) = {
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
#if IS_ENABLED(CONFIG_FDT_64BIT)
struct rockchip_rk3288_noc_plat {
struct dtd_rockchip_rk3288_noc dtplat;
};
struct rockchip_rk3288_grf_plat {
struct dtd_rockchip_rk3288_grf dtplat;
};
struct rockchip_rk3288_sgrf_plat {
struct dtd_rockchip_rk3288_sgrf dtplat;
};
struct rockchip_rk3288_pmu_plat {
struct dtd_rockchip_rk3288_pmu dtplat;
};
static int rk3288_noc_bind_of_plat(struct udevice *dev)
{
struct rockchip_rk3288_noc_plat *plat = dev_get_plat(dev);
struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
int size = dev->uclass->uc_drv->per_device_auto;
if (size && !priv) {
priv = calloc(1, size);
if (!priv)
return -ENOMEM;
dev_set_uclass_priv(dev, priv);
}
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
return regmap_init_mem_plat(dev, plat->dtplat.reg, sizeof(plat->dtplat.reg[0]),
ARRAY_SIZE(plat->dtplat.reg) / 2, &priv->regmap);
}
static int rk3288_grf_bind_of_plat(struct udevice *dev)
{
struct rockchip_rk3288_grf_plat *plat = dev_get_plat(dev);
struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
int size = dev->uclass->uc_drv->per_device_auto;
if (size && !priv) {
priv = calloc(1, size);
if (!priv)
return -ENOMEM;
dev_set_uclass_priv(dev, priv);
}
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
return regmap_init_mem_plat(dev, plat->dtplat.reg, sizeof(plat->dtplat.reg[0]),
ARRAY_SIZE(plat->dtplat.reg) / 2, &priv->regmap);
}
static int rk3288_sgrf_bind_of_plat(struct udevice *dev)
{
struct rockchip_rk3288_sgrf_plat *plat = dev_get_plat(dev);
struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
int size = dev->uclass->uc_drv->per_device_auto;
if (size && !priv) {
priv = calloc(1, size);
if (!priv)
return -ENOMEM;
dev_set_uclass_priv(dev, priv);
}
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
return regmap_init_mem_plat(dev, plat->dtplat.reg, sizeof(plat->dtplat.reg[0]),
ARRAY_SIZE(plat->dtplat.reg) / 2, &priv->regmap);
}
static int rk3288_pmu_bind_of_plat(struct udevice *dev)
{
struct rockchip_rk3288_pmu_plat *plat = dev_get_plat(dev);
struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
int size = dev->uclass->uc_drv->per_device_auto;
if (size && !priv) {
priv = calloc(1, size);
if (!priv)
return -ENOMEM;
dev_set_uclass_priv(dev, priv);
}
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
return regmap_init_mem_plat(dev, plat->dtplat.reg, sizeof(plat->dtplat.reg[0]),
ARRAY_SIZE(plat->dtplat.reg) / 2, &priv->regmap);
}
#else
static int rk3288_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
@ -32,32 +132,53 @@ static int rk3288_syscon_bind_of_plat(struct udevice *dev)
return 0;
}
#endif
U_BOOT_DRIVER(rockchip_rk3288_noc) = {
.name = "rockchip_rk3288_noc",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids,
#if IS_ENABLED(CONFIG_FDT_64BIT)
.bind = rk3288_noc_bind_of_plat,
.plat_auto = sizeof(struct rockchip_rk3288_noc_plat),
#else
.bind = rk3288_syscon_bind_of_plat,
#endif
};
U_BOOT_DRIVER(rockchip_rk3288_grf) = {
.name = "rockchip_rk3288_grf",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 1,
#if IS_ENABLED(CONFIG_FDT_64BIT)
.bind = rk3288_grf_bind_of_plat,
.plat_auto = sizeof(struct rockchip_rk3288_grf_plat),
#else
.bind = rk3288_syscon_bind_of_plat,
#endif
};
U_BOOT_DRIVER(rockchip_rk3288_sgrf) = {
.name = "rockchip_rk3288_sgrf",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 2,
#if IS_ENABLED(CONFIG_FDT_64BIT)
.bind = rk3288_sgrf_bind_of_plat,
.plat_auto = sizeof(struct rockchip_rk3288_sgrf_plat),
#else
.bind = rk3288_syscon_bind_of_plat,
#endif
};
U_BOOT_DRIVER(rockchip_rk3288_pmu) = {
.name = "rockchip_rk3288_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 3,
#if IS_ENABLED(CONFIG_FDT_64BIT)
.bind = rk3288_pmu_bind_of_plat,
.plat_auto = sizeof(struct rockchip_rk3288_pmu_plat),
#else
.bind = rk3288_syscon_bind_of_plat,
#endif
};
#endif

14
arch/arm/mach-rockchip/rk3568/Kconfig
View File

@ -1,11 +1,24 @@
if ROCKCHIP_RK3568
choice
prompt "RK3568/RK3566 board select"
config TARGET_EVB_RK3568
bool "RK3568 evaluation board"
select BOARD_LATE_INIT
help
RK3568 EVB is a evaluation board for Rockchp RK3568.
config TARGET_ANBERNIC_RGXX3_RK3566
bool "Anbernic RGXX3"
help
Anbernic RGXX3 gaming device with Rockchip RK3566. This
config can be used with the RG353M, RG353P, RG353V, RG353VS,
and RG503. The correct device tree name will automatically
be selected by the bootloader.
endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0xfdc20200
@ -19,5 +32,6 @@ config SYS_MALLOC_F_LEN
default 0x2000
source "board/rockchip/evb_rk3568/Kconfig"
source "board/anbernic/rgxx3_rk3566/Kconfig"
endif

2
arch/arm/mach-stm32mp/spl.c
View File

@ -112,7 +112,7 @@ uint32_t stm32mp_get_dram_size(void)
static int optee_get_reserved_memory(uint32_t *start, uint32_t *size)
{
phys_size_t fdt_mem_size;
fdt_addr_t fdt_mem_size;
fdt_addr_t fdt_start;
ofnode node;

15
board/anbernic/rgxx3_rk3566/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_ANBERNIC_RGXX3_RK3566
config SYS_BOARD
default "rgxx3_rk3566"
config SYS_VENDOR
default "anbernic"
config SYS_CONFIG_NAME
default "anbernic-rgxx3-rk3566"
config BOARD_SPECIFIC_OPTIONS
def_bool y
endif

6
board/anbernic/rgxx3_rk3566/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
RGXX3-RK3566
M: Chris Morgan <macromorgan@hotmail.com>
S: Maintained
F: board/anbernic/rgxx3-rk3566
F: include/configs/anbernic-rgxx3-rk3566
F: configs/anbernic-rgxx3_defconfig

6
board/anbernic/rgxx3_rk3566/Makefile Normal file
View File

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2023 Chris Morgan <macromorgan@hotmail.com>
#
obj-y += rgxx3-rk3566.o

203
board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c Normal file
View File

@ -0,0 +1,203 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2023 Chris Morgan <macromorgan@hotmail.com>
*/
#include <abuf.h>
#include <adc.h>
#include <asm/io.h>
#include <dm.h>
#include <linux/delay.h>
#include <pwm.h>
#include <rng.h>
#include <stdlib.h>
#include <mmc.h>
#include <env.h>
#define GPIO0_BASE 0xfdd60000
#define GPIO_SWPORT_DR_H 0x0004
#define GPIO_SWPORT_DDR_H 0x000c
#define GPIO_A5 BIT(5)
#define GPIO_A6 BIT(6)
#define GPIO_WRITEMASK(bits) ((bits) << 16)
#define DTB_DIR "rockchip/"
struct rg3xx_model {
const char *board;
const char *board_name;
const char *fdtfile;
};
enum rgxx3_device_id {
RG353M,
RG353P,
RG353V,
RG353VS,
RG503,
};
static const struct rg3xx_model rg3xx_model_details[] = {
[RG353M] = {
"rk3566-anbernic-rg353m",
"RG353M",
DTB_DIR "rk3566-anbernic-rg353m.dtb",
},
[RG353P] = {
"rk3566-anbernic-rg353p",
"RG353P",
DTB_DIR "rk3566-anbernic-rg353p.dtb",
},
[RG353V] = {
"rk3566-anbernic-rg353v",
"RG353V",
DTB_DIR "rk3566-anbernic-rg353v.dtb",
},
[RG353VS] = {
"rk3566-anbernic-rg353vs",
"RG353VS",
DTB_DIR "rk3566-anbernic-rg353vs.dtb",
},
[RG503] = {
"rk3566-anbernic-rg503",
"RG503",
DTB_DIR "rk3566-anbernic-rg503.dtb",
},
};
/*
* Start LED very early so user knows device is on. Set color
* to amber.
*/
void spl_board_init(void)
{
/* Set GPIO0_A5 and GPIO0_A6 to output. */
writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | (GPIO_A6 | GPIO_A5),
(GPIO0_BASE + GPIO_SWPORT_DDR_H));
/* Set GPIO0_A5 to 0 and GPIO0_A6 to 1. */
writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A6,
(GPIO0_BASE + GPIO_SWPORT_DR_H));
}
/* Use hardware rng to seed Linux random. */
int board_rng_seed(struct abuf *buf)
{
struct udevice *dev;
size_t len = 0x8;
u64 *data;
data = malloc(len);
if (!data) {
printf("Out of memory\n");
return -ENOMEM;
}
if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
printf("No RNG device\n");
return -ENODEV;
}
if (dm_rng_read(dev, data, len)) {
printf("Reading RNG failed\n");
return -EIO;
}
abuf_init_set(buf, data, len);
return 0;
}
/*
* Buzz the buzzer so the user knows something is going on. Make it
* optional in case PWM is disabled.
*/
void __maybe_unused startup_buzz(void)
{
struct udevice *dev;
int err;
err = uclass_get_device(UCLASS_PWM, 0, &dev);
if (err)
printf("pwm not found\n");
pwm_set_enable(dev, 0, 1);
mdelay(200);
pwm_set_enable(dev, 0, 0);
}
/* Detect which Anbernic RGXX3 device we are using so as to load the
* correct devicetree for Linux. Set an environment variable once
* found. The detection depends on the value of ADC channel 1, the
* presence of an eMMC on mmc0, and querying the DSI panel (TODO).
*/
int rgxx3_detect_device(void)
{
u32 adc_info;
int ret;
int board_id = -ENXIO;
struct mmc *mmc;
ret = adc_channel_single_shot("saradc@fe720000", 1, &adc_info);
if (ret) {
printf("Read SARADC failed with error %d\n", ret);
return ret;
}
/* Observed value 517. */
if (adc_info > 505 && adc_info < 530)
board_id = RG353M;
/* Observed value 695. */
if (adc_info > 680 && adc_info < 710)
board_id = RG353V;
/* Documented value 860. */
if (adc_info > 850 && adc_info < 870)
board_id = RG353P;
/* Observed value 1023. */
if (adc_info > 1010)
board_id = RG503;
/*
* Try to access the eMMC on an RG353V. If it's missing, it's
* an RG353VS. Note we could also check for a touchscreen at
* 0x1a on i2c2.
*/
if (board_id == RG353V) {
mmc = find_mmc_device(0);
if (mmc) {
ret = mmc_init(mmc);
if (ret)
board_id = RG353VS;
}
}
if (board_id < 0)
return board_id;
env_set("board", rg3xx_model_details[board_id].board);
env_set("board_name",
rg3xx_model_details[board_id].board_name);
env_set("fdtfile", rg3xx_model_details[board_id].fdtfile);
return 0;
}
int rk_board_late_init(void)
{
int ret;
/* Turn off orange LED and turn on green LED. */
writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A5,
(GPIO0_BASE + GPIO_SWPORT_DR_H));
ret = rgxx3_detect_device();
if (ret) {
printf("Unable to detect device type: %d\n", ret);
return ret;
}
if (IS_ENABLED(CONFIG_DM_PWM))
startup_buzz();
return 0;
}

6
board/rockchip/evb_rk3328/MAINTAINERS
View File

@ -5,6 +5,12 @@ F: board/rockchip/evb_rk3328
F: include/configs/evb_rk3328.h
F: configs/evb-rk3328_defconfig
NANOPI-R2C-RK3328
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
F: configs/nanopi-r2c-rk3328_defconfig
F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
NANOPI-R2S-RK3328
M: David Bauer <mail@david-bauer.net>
S: Maintained

78
configs/anbernic-rgxx3_defconfig Normal file
View File

@ -0,0 +1,78 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_ANBERNIC_RGXX3_RK3566=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_PWM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
# CONFIG_NET is not set
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ARM_SMCCC_FEATURES=y
CONFIG_SCMI_FIRMWARE=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_DM_REGULATOR_SCMI=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_REGEX=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set

112
configs/nanopi-r2c-rk3328_defconfig Normal file
View File

@ -0,0 +1,112 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSINFO=y
CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

4
configs/nanopi-r4s-rk3399_defconfig
View File

@ -78,3 +78,7 @@ CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_MISC=y
CONFIG_MISC_INIT_R=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_ROCKCHIP_OTP=y

97
configs/rock-4c-plus-rk3399_defconfig Normal file
View File

@ -0,0 +1,97 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y

4
configs/rock-pi-4-rk3399_defconfig
View File

@ -7,7 +7,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4b"
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
@ -19,7 +19,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4b.dtb"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000

9
doc/board/anbernic/index.rst Normal file
View File

@ -0,0 +1,9 @@
.. SPDX-License-Identifier: GPL-2.0+
Anbernic
========
.. toctree::
:maxdepth: 2
rgxx3.rst

47
doc/board/anbernic/rgxx3.rst Normal file
View File

@ -0,0 +1,47 @@
.. SPDX-License-Identifier: GPL-2.0+
U-Boot for Anbernic RGxx3 Devices
=================================
This allows U-Boot to boot the following Anbernic devices:
- Anbernic RG353M
- Anbernic RG353P
- Anbernic RG353V
- Anbernic RG353VS
- Anbernic RG503
The correct device is detected automatically by comparing ADC values
from ADC channel 1. In the event of an RG353V, an attempt is then made
to probe for an eMMC and if it fails the device is assumed to be an
RG353VS. Based on the detected device, the environment variables
"board", "board_name", and "fdtfile" are set to the correct values
corresponding to the board which can be read by a boot script to boot
with the correct device tree.
Please note that there are some versions of the RG353 devices with
different panels. Panel auto-detection is planned for a later date.
Building U-Boot
---------------
.. code-block:: bash
$ export CROSS_COMPILE=aarch64-none-elf-
$ export BL31=../rkbin/bin/rk35/rk3568_bl31_v1.34.elf
$ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3568_ddr_1056MHz_v1.13.bin
$ make anbernic-rgxx3_defconfig
$ make
This will build ``u-boot-rockchip.bin`` which can be written to an SD
card.
Image installation
------------------
Write the ``u-boot-rockchip.bin`` to an SD card offset 32kb from the
start.
.. code-block:: bash
$ dd if=u-boot-rockchip.bin of=/dev/mmcblk0 bs=512 seek=64

1
doc/board/index.rst
View File

@ -11,6 +11,7 @@ Board-specific doc
AndesTech/index
allwinner/index
amlogic/index
anbernic/index
apple/index
armltd/index
atmel/index

8
doc/board/rockchip/rockchip.rst
View File

@ -83,10 +83,16 @@ List of mainline supported Rockchip boards:
- Khadas Edge-V (hadas-edge-v-rk3399)
- Orange Pi RK3399 (orangepi-rk3399)
- Pine64 RockPro64 (rockpro64-rk3399)
- Radxa ROCK Pi 4 (rock-pi-4-rk3399)
- Radxa ROCK 4C+ (rock-4c-plus-rk3399)
- Radxa ROCK 4SE (rock-pi-4-rk3399)
- Radxa ROCK Pi 4A/B/A+/B+ (rock-pi-4-rk3399)
- Radxa ROCK Pi 4C (rock-pi-4c-rk3399)
- Rockchip Evb-RK3399 (evb_rk3399)
- Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
* rk3566
- Anbernic RGxx3 (rgxx3-rk3566)
* rk3568
- Rockchip Evb-RK3568 (evb-rk3568)

2
doc/develop/driver-model/livetree.rst
View File

@ -103,7 +103,7 @@ The new code is:
struct udevice *bus;
i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
i2c_bus->regs = dev_read_addr_ptr(dev);
plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 500000);
The dev_read\_...() interface is more convenient and works with both the

6
drivers/adc/rockchip-saradc.c
View File

@ -145,10 +145,10 @@ int rockchip_saradc_of_to_plat(struct udevice *dev)
struct rockchip_saradc_data *data;
data = (struct rockchip_saradc_data *)dev_get_driver_data(dev);
priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev);
if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) {
priv->regs = dev_read_addr_ptr(dev);
if (!priv->regs) {
pr_err("Dev: %s - can't get address!", dev->name);
return -ENODATA;
return -EINVAL;
}
priv->data = data;

2
drivers/ata/dwc_ahsata.c
View File

@ -912,7 +912,7 @@ int dwc_ahsata_probe(struct udevice *dev)
#endif
uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
uc_priv->mmio_base = dev_read_addr_ptr(dev);
/* initialize adapter */
ret = ahci_host_init(uc_priv);

2
drivers/cache/cache-l2x0.c vendored
View File

@ -13,7 +13,7 @@ static void l2c310_of_parse_and_init(struct udevice *dev)
{
u32 tag[3] = { 0, 0, 0 };
u32 saved_reg, prefetch;
struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
struct pl310_regs *regs = dev_read_addr_ptr(dev);
/* Disable the L2 Cache */
clrbits_le32(&regs->pl310_ctrl, L2X0_CTRL_EN);

2
drivers/cache/cache-v5l2.c vendored
View File

@ -119,7 +119,7 @@ static int v5l2_of_to_plat(struct udevice *dev)
struct v5l2_plat *plat = dev_get_plat(dev);
struct l2cache *regs;
regs = (struct l2cache *)(uintptr_t)dev_read_addr(dev);
regs = dev_read_addr_ptr(dev);
plat->regs = regs;
plat->iprefetch = -EINVAL;

2
drivers/clk/at91/sama7g5.c
View File

@ -1103,7 +1103,7 @@ static const struct pmc_clk_setup sama7g5_clk_setup[] = {
static int sama7g5_clk_probe(struct udevice *dev)
{
void __iomem *base = (void *)devfdt_get_addr(dev);
void __iomem *base = devfdt_get_addr_ptr(dev);
unsigned int *clkmuxallocs[SAMA7G5_MAX_MUX_ALLOCS];
unsigned int *muxallocs[SAMA7G5_MAX_MUX_ALLOCS];
const char *p[10];

2
drivers/clk/at91/sckc.c
View File

@ -123,7 +123,7 @@ U_BOOT_DRIVER(at91_sam9x60_td_slck) = {
static int at91_sam9x60_sckc_probe(struct udevice *dev)
{
struct sam9x60_sckc *sckc = dev_get_priv(dev);
void __iomem *base = (void *)devfdt_get_addr(dev);
void __iomem *base = devfdt_get_addr_ptr(dev);
const char *slow_rc_osc, *slow_osc;
const char *parents[2];
struct clk *clk, c;

4
drivers/clk/clk-hsdk-cgu.c
View File

@ -753,11 +753,11 @@ static int hsdk_cgu_clk_probe(struct udevice *dev)
else
hsdk_clk->map = hsdk_4xd_clk_map;
hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
hsdk_clk->cgu_regs = devfdt_get_addr_index_ptr(dev, 0);
if (!hsdk_clk->cgu_regs)
return -EINVAL;
hsdk_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
hsdk_clk->creg_regs = devfdt_get_addr_index_ptr(dev, 1);
if (!hsdk_clk->creg_regs)
return -EINVAL;

2
drivers/clk/rockchip/clk_px30.c
View File

@ -1508,7 +1508,7 @@ static int px30_clk_bind(struct udevice *dev)
ret = offsetof(struct px30_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 12);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;

2
drivers/clk/rockchip/clk_rk3036.c
View File

@ -361,7 +361,7 @@ static int rk3036_clk_bind(struct udevice *dev)
ret = offsetof(struct rk3036_cru, cru_softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 9);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;

2
drivers/clk/rockchip/clk_rk3188.c
View File

@ -600,7 +600,7 @@ static int rk3188_clk_bind(struct udevice *dev)
ret = offsetof(struct rk3188_cru, cru_softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 9);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;

2
drivers/clk/rockchip/clk_rk322x.c
View File

@ -518,7 +518,7 @@ static int rk322x_clk_bind(struct udevice *dev)
ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 9);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;

2
drivers/clk/rockchip/clk_rk3288.c
View File

@ -1027,7 +1027,7 @@ static int rk3288_clk_bind(struct udevice *dev)
ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 12);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;

2
drivers/clk/rockchip/clk_rk3308.c
View File

@ -1054,7 +1054,7 @@ static int rk3308_clk_bind(struct udevice *dev)
ret = offsetof(struct rk3308_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 12);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;

2
drivers/clk/rockchip/clk_rk3328.c
View File

@ -831,7 +831,7 @@ static int rk3328_clk_bind(struct udevice *dev)
ret = offsetof(struct rk3328_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 12);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return ret;

2
drivers/clk/rockchip/clk_rk3368.c
View File

@ -629,7 +629,7 @@ static int rk3368_clk_bind(struct udevice *dev)
ret = offsetof(struct rk3368_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 15);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return ret;

4
drivers/clk/rockchip/clk_rk3399.c
View File

@ -1455,7 +1455,7 @@ static int rk3399_clk_bind(struct udevice *dev)
ret = offsetof(struct rockchip_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 21);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;
@ -1652,7 +1652,7 @@ static int rk3399_pmuclk_bind(struct udevice *dev)
ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 2);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;
}

4
drivers/clk/rockchip/clk_rk3568.c
View File

@ -501,7 +501,7 @@ static int rk3568_pmuclk_bind(struct udevice *dev)
ret = offsetof(struct rk3568_pmucru, pmu_softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 1);
if (ret)
debug("Warning: pmucru software reset driver bind faile\n");
debug("Warning: pmucru software reset driver bind failed\n");
#endif
return 0;
@ -2950,7 +2950,7 @@ static int rk3568_clk_bind(struct udevice *dev)
ret = offsetof(struct rk3568_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 30);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;

24
drivers/clk/rockchip/clk_rk3588.c
View File

@ -1557,6 +1557,21 @@ static ulong rk3588_clk_get_rate(struct clk *clk)
case TCLK_WDT0:
rate = OSC_HZ;
break;
case PCLK_PMU0_ROOT:
rate = 100000000;
break;
case HCLK_PMU_CM0_ROOT:
rate = 200000000;
break;
case ACLK_BUS_ROOT:
rate = 375000000;
break;
case CLK_150M_SRC:
rate = 150000000;
break;
case CLK_GPU:
rate = 200000000;
break;
#ifndef CONFIG_SPL_BUILD
case CLK_AUX16M_0:
case CLK_AUX16M_1:
@ -1707,6 +1722,13 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)
case TCLK_WDT0:
ret = OSC_HZ;
break;
case PCLK_PMU0_ROOT:
case CLK_GPU:
case HCLK_PMU_CM0_ROOT:
case ACLK_BUS_ROOT:
case CLK_150M_SRC:
ret = 0;
break;
#ifndef CONFIG_SPL_BUILD
case CLK_AUX16M_0:
case CLK_AUX16M_1:
@ -1976,7 +1998,7 @@ static int rk3588_clk_bind(struct udevice *dev)
ret = offsetof(struct rk3588_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 49158);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;

2
drivers/clk/rockchip/clk_rv1108.c
View File

@ -706,7 +706,7 @@ static int rv1108_clk_bind(struct udevice *dev)
ret = offsetof(struct rv1108_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 13);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;

4
drivers/clk/rockchip/clk_rv1126.c
View File

@ -505,7 +505,7 @@ static int rv1126_pmuclk_bind(struct udevice *dev)
ret = offsetof(struct rv1126_pmucru, pmu_softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 2);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;
}
@ -1867,7 +1867,7 @@ static int rv1126_clk_bind(struct udevice *dev)
ret = offsetof(struct rv1126_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 15);
if (ret)
debug("Warning: software reset driver bind faile\n");
debug("Warning: software reset driver bind failed\n");
#endif
return 0;
}

9
drivers/clk/ti/clk-ctrl.c
View File

@ -44,7 +44,7 @@ static int clk_ti_ctrl_disable(struct clk *clk)
offs = priv->offs[0].start + clk->id;
err = clk_ti_ctrl_check_offs(clk, offs);
if (err) {
dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
dev_err(clk->dev, "invalid offset: 0x%llx\n", (fdt64_t)offs);
return err;
}
@ -64,7 +64,7 @@ static int clk_ti_ctrl_enable(struct clk *clk)
offs = priv->offs[0].start + clk->id;
err = clk_ti_ctrl_check_offs(clk, offs);
if (err) {
dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
dev_err(clk->dev, "invalid offset: 0x%llx\n", (fdt64_t)offs);
return err;
}
@ -125,8 +125,9 @@ static int clk_ti_ctrl_of_to_plat(struct udevice *dev)
}
priv->offs[i].end = priv->offs[i].start + fdt_size;
dev_dbg(dev, "start=0x%08lx, end=0x%08lx\n",
priv->offs[i].start, priv->offs[i].end);
dev_dbg(dev, "start=0x%016llx, end=0x%016llx\n",
(fdt64_t)priv->offs[i].start,
(fdt64_t)priv->offs[i].end);
}
return 0;

8
drivers/core/fdtaddr.c
View File

@ -126,6 +126,14 @@ fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index,
#endif
}
void *devfdt_get_addr_size_index_ptr(const struct udevice *dev, int index,
fdt_size_t *size)
{
fdt_addr_t addr = devfdt_get_addr_size_index(dev, index, size);
return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
}
fdt_addr_t devfdt_get_addr_name(const struct udevice *dev, const char *name)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)

15
drivers/core/read.c
View File

@ -131,6 +131,16 @@ fdt_addr_t dev_read_addr_index(const struct udevice *dev, int index)
return devfdt_get_addr_index(dev, index);
}
void *dev_read_addr_index_ptr(const struct udevice *dev, int index)
{
fdt_addr_t addr = dev_read_addr_index(dev, index);
if (addr == FDT_ADDR_T_NONE)
return NULL;
return map_sysmem(addr, 0);
}
fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index,
fdt_size_t *size)
{
@ -190,7 +200,10 @@ void *dev_read_addr_ptr(const struct udevice *dev)
{
fdt_addr_t addr = dev_read_addr(dev);
return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
if (addr == FDT_ADDR_T_NONE)
return NULL;
return map_sysmem(addr, 0);
}
void *dev_remap_addr(const struct udevice *dev)

23
drivers/core/regmap.c
View File

@ -79,7 +79,7 @@ static struct regmap *regmap_alloc(int count)
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
int regmap_init_mem_plat(struct udevice *dev, fdt_val_t *reg, int count,
int regmap_init_mem_plat(struct udevice *dev, void *reg, int size, int count,
struct regmap **mapp)
{
struct regmap_range *range;
@ -89,9 +89,24 @@ int regmap_init_mem_plat(struct udevice *dev, fdt_val_t *reg, int count,
if (!map)
return -ENOMEM;
for (range = map->ranges; count > 0; reg += 2, range++, count--) {
range->start = *reg;
range->size = reg[1];
if (size == sizeof(fdt32_t)) {
fdt32_t *ptr = (fdt32_t *)reg;
for (range = map->ranges; count > 0;
ptr += 2, range++, count--) {
range->start = *ptr;
range->size = ptr[1];
}
} else if (size == sizeof(fdt64_t)) {
fdt64_t *ptr = (fdt64_t *)reg;
for (range = map->ranges; count > 0;
ptr += 2, range++, count--) {
range->start = *ptr;
range->size = ptr[1];
}
} else {
return -EINVAL;
}
*mapp = map;

23
drivers/core/syscon-uclass.c
View File

@ -49,17 +49,30 @@ static int syscon_pre_probe(struct udevice *dev)
if (device_get_uclass_id(dev->parent) == UCLASS_PCI)
return 0;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/*
* With OF_PLATDATA we really have no way of knowing the format of
* the device-specific platform data. So we assume that it starts with
* a 'reg' member, and this holds a single address and size. Drivers
* using OF_PLATDATA will need to ensure that this is true.
* a 'reg' member that holds a single address and size. Drivers
* using OF_PLATDATA will need to ensure that this is true. In case of
* odd reg structures other then the syscon_base_plat structure
* below the regmap must be defined in the individual syscon driver.
*/
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct syscon_base_plat {
phys_addr_t reg[2];
};
struct syscon_base_plat *plat = dev_get_plat(dev);
return regmap_init_mem_plat(dev, plat->reg, ARRAY_SIZE(plat->reg),
&priv->regmap);
/*
* Return if the regmap is already defined in the individual
* syscon driver.
*/
if (priv->regmap)
return 0;
return regmap_init_mem_plat(dev, plat->reg, sizeof(plat->reg[0]),
ARRAY_SIZE(plat->reg) / 2, &priv->regmap);
#else
return regmap_init_mem(dev_ofnode(dev), &priv->regmap);
#endif

4
drivers/ddr/altera/sdram_gen5.c
View File

@ -567,9 +567,9 @@ static int altera_gen5_sdram_of_to_plat(struct udevice *dev)
{
struct altera_gen5_sdram_plat *plat = dev_get_plat(dev);
plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
plat->sdr = devfdt_get_addr_index_ptr(dev, 0);
if (!plat->sdr)
return -ENODEV;
return -EINVAL;
return 0;
}

2
drivers/gpio/mscc_sgpio.c
View File

@ -232,7 +232,7 @@ static int mscc_sgpio_probe(struct udevice *dev)
debug("probe: gpios = %d, bit-count = %d\n",
uc_priv->gpio_count, priv->bitcount);
priv->regs = (u32 __iomem *)dev_read_addr(dev);
priv->regs = dev_read_addr_ptr(dev);
uc_priv->bank_name = "sgpio";
sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,

4
drivers/gpio/tegra_gpio.c
View File

@ -339,8 +339,8 @@ static int gpio_tegra_bind(struct udevice *parent)
if (len < 0)
return len;
bank_count = len / 3 / sizeof(u32);
ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
if ((ulong)ctlr == FDT_ADDR_T_NONE)
ctlr = dev_read_addr_ptr(parent);
if (!ctlr)
return -EINVAL;
}
#endif

2
drivers/gpio/xilinx_gpio.c
View File

@ -268,7 +268,7 @@ static int xilinx_gpio_of_to_plat(struct udevice *dev)
struct xilinx_gpio_plat *plat = dev_get_plat(dev);
int is_dual;
plat->regs = (struct gpio_regs *)dev_read_addr(dev);
plat->regs = dev_read_addr_ptr(dev);
plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0);
plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0);

4
drivers/i2c/i2c-cdns.c
View File

@ -479,9 +479,9 @@ static int cdns_i2c_of_to_plat(struct udevice *dev)
struct clk clk;
int ret;
i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
i2c_bus->regs = dev_read_addr_ptr(dev);
if (!i2c_bus->regs)
return -ENOMEM;
return -EINVAL;
if (pdata)
i2c_bus->quirks = pdata->quirks;

4
drivers/i2c/tegra_i2c.c
View File

@ -364,8 +364,8 @@ static int tegra_i2c_probe(struct udevice *dev)
i2c_bus->id = dev_seq(dev);
i2c_bus->type = dev_get_driver_data(dev);
i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
i2c_bus->regs = dev_read_addr_ptr(dev);
if (!i2c_bus->regs) {
debug("%s: Cannot get regs address\n", __func__);
return -EINVAL;
}

2
drivers/mmc/am654_sdhci.c
View File

@ -584,7 +584,7 @@ static int am654_sdhci_of_to_plat(struct udevice *dev)
int ret;
host->name = dev->name;
host->ioaddr = (void *)dev_read_addr(dev);
host->ioaddr = dev_read_addr_ptr(dev);
plat->non_removable = dev_read_bool(dev, "non-removable");
if (plat->flags & DLL_PRESENT) {

2
drivers/mmc/davinci_mmc.c
View File

@ -506,7 +506,7 @@ static int davinci_mmc_of_to_plat(struct udevice *dev)
struct davinci_mmc_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg = &plat->cfg;
plat->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
plat->reg_base = dev_read_addr_ptr(dev);
cfg->f_min = 200000;
cfg->f_max = 25000000;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,

2
drivers/mmc/piton_mmc.c
View File

@ -74,7 +74,7 @@ static int piton_mmc_ofdata_to_platdata(struct udevice *dev)
struct mmc *mmc;
struct blk_desc *bdesc;
priv->base_addr = (void *)dev_read_addr(dev);
priv->base_addr = dev_read_addr_ptr(dev);
cfg = &plat->cfg;
cfg->name = "PITON MMC";
cfg->host_caps = MMC_MODE_8BIT;

2
drivers/mmc/tegra_mmc.c
View File

@ -708,7 +708,7 @@ static int tegra_mmc_probe(struct udevice *dev)
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
priv->reg = (void *)dev_read_addr(dev);
priv->reg = dev_read_addr_ptr(dev);
ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
if (ret) {

2
drivers/mmc/xenon_sdhci.c
View File

@ -537,7 +537,7 @@ static int xenon_sdhci_of_to_plat(struct udevice *dev)
host->ioaddr = dev_read_addr_ptr(dev);
if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1);
priv->pad_ctrl_reg = devfdt_get_addr_index_ptr(dev, 1);
name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
NULL);

6
drivers/mmc/zynq_sdhci.c
View File

@ -1196,9 +1196,9 @@ static int arasan_sdhci_of_to_plat(struct udevice *dev)
arasan_dt_parse_clk_phases(dev);
#endif
priv->host->ioaddr = (void *)dev_read_addr(dev);
if (IS_ERR(priv->host->ioaddr))
return PTR_ERR(priv->host->ioaddr);
priv->host->ioaddr = dev_read_addr_ptr(dev);
if (!priv->host->ioaddr)
return -EINVAL;
priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");

2
drivers/mtd/nand/raw/arasan_nfc.c
View File

@ -1233,7 +1233,7 @@ static int arasan_probe(struct udevice *dev)
ofnode child;
int err = -1;
info->reg = (struct nand_regs *)dev_read_addr(dev);
info->reg = dev_read_addr_ptr(dev);
mtd = nand_to_mtd(nand_chip);
nand_set_controller_data(nand_chip, &arasan->nand_ctrl);

6
drivers/mtd/nand/raw/cortina_nand.c
View File

@ -1174,9 +1174,9 @@ static int fdt_decode_nand(struct udevice *dev, struct nand_drv *info)
{
int ecc_strength;
info->reg = (struct nand_ctlr *)dev_read_addr(dev);
info->dma_glb = (struct dma_global *)dev_read_addr_index(dev, 1);
info->dma_nand = (struct dma_ssp *)dev_read_addr_index(dev, 2);
info->reg = dev_read_addr_ptr(dev);
info->dma_glb = dev_read_addr_index_ptr(dev, 1);
info->dma_nand = dev_read_addr_index_ptr(dev, 2);
info->config.enabled = dev_read_enabled(dev);
ecc_strength = dev_read_u32_default(dev, "nand-ecc-strength", 16);
info->flash_base =

2
drivers/mtd/nand/raw/mxic_nand.c
View File

@ -538,7 +538,7 @@ static int mxic_nfc_probe(struct udevice *dev)
ofnode child;
int err;
nfc->regs = (void *)dev_read_addr(dev);
nfc->regs = dev_read_addr_ptr(dev);
nfc->send_clk = devm_clk_get(dev, "send");
if (IS_ERR(nfc->send_clk))

3
drivers/mtd/nand/raw/nand_ids.c
View File

@ -48,6 +48,9 @@ struct nand_flash_dev nand_flash_ids[] = {
{"TC58NVG6D2 64G 3.3V 8-bit",
{ .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} },
SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
{"SDTNQGAMA 64G 3.3V 8-bit",
{ .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x57} },
SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
{"SDTNRGAMA 64G 3.3V 8-bit",
{ .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} },
SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },

78
drivers/mtd/nand/raw/rockchip_nfc.c
View File

@ -487,10 +487,10 @@ static int rk_nfc_write_page_raw(struct mtd_info *mtd,
*
* BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3
*
* The rk_nfc_ooblayout_free() function already has reserved
* these 4 bytes with:
* The oobfree structure already has reserved these 4 bytes
* together with 2 bytes for BBM by reducing it's length:
*
* oob_region->offset = NFC_SYS_DATA_SIZE + 2;
* oobfree[0].length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2;
*/
if (!i)
memcpy(rk_nfc_oob_ptr(chip, i),
@ -814,47 +814,9 @@ static void rk_nfc_disable_clks(struct rk_nfc *nfc)
clk_disable_unprepare(nfc->ahb_clk);
}
static int rk_nfc_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *oob_region)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
if (section)
return -ERANGE;
/*
* The beginning of the OOB area stores the reserved data for the NFC,
* the size of the reserved data is NFC_SYS_DATA_SIZE bytes.
*/
oob_region->length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2;
oob_region->offset = NFC_SYS_DATA_SIZE + 2;
return 0;
}
static int rk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *oob_region)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
if (section)
return -ERANGE;
oob_region->length = mtd->oobsize - rknand->metadata_size;
oob_region->offset = rknand->metadata_size;
return 0;
}
static const struct mtd_ooblayout_ops rk_nfc_ooblayout_ops = {
.rfree = rk_nfc_ooblayout_free,
.ecc = rk_nfc_ooblayout_ecc,
};
static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct nand_chip *chip)
{
struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
const u8 *strengths = nfc->cfg->ecc_strengths;
struct mtd_info *mtd = nand_to_mtd(chip);
struct nand_ecc_ctrl *ecc = &chip->ecc;
@ -892,6 +854,21 @@ static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct nand_chip *chip)
ecc->steps = mtd->writesize / ecc->size;
ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * chip->ecc.size), 8);
if (ecc->bytes * ecc->steps > mtd->oobsize - rknand->metadata_size)
return -EINVAL;
ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
if (!ecc->layout)
return -ENOMEM;
ecc->layout->eccbytes = ecc->bytes * ecc->steps;
for (i = 0; i < ecc->layout->eccbytes; i++)
ecc->layout->eccpos[i] = rknand->metadata_size + i;
ecc->layout->oobfree[0].length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2;
ecc->layout->oobfree[0].offset = 2;
return 0;
}
@ -957,6 +934,7 @@ static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum)
nand_set_controller_data(chip, nfc);
chip->flash_node = node;
chip->chip_delay = NFC_RB_DELAY_US;
chip->select_chip = rk_nfc_select_chip;
chip->cmd_ctrl = rk_nfc_cmd;
@ -969,7 +947,6 @@ static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum)
chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
mtd_set_ooblayout(mtd, &rk_nfc_ooblayout_ops);
rk_nfc_hw_init(nfc);
ret = nand_scan_ident(mtd, nsels, NULL);
if (ret)
@ -998,13 +975,16 @@ static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum)
if (!nfc->page_buf) {
nfc->page_buf = kzalloc(NFC_MAX_PAGE_SIZE, GFP_KERNEL);
if (!nfc->page_buf)
if (!nfc->page_buf) {
kfree(ecc->layout);
return -ENOMEM;
}
}
if (!nfc->oob_buf) {
nfc->oob_buf = kzalloc(NFC_MAX_OOB_SIZE, GFP_KERNEL);
if (!nfc->oob_buf) {
kfree(ecc->layout);
kfree(nfc->page_buf);
nfc->page_buf = NULL;
return -ENOMEM;
@ -1165,10 +1145,6 @@ static const struct udevice_id rk_nfc_id_table[] = {
.compatible = "rockchip,rv1108-nfc",
.data = (unsigned long)&nfc_v8_cfg
},
{
.compatible = "rockchip,rk3308-nfc",
.data = (unsigned long)&nfc_v8_cfg
},
{ /* sentinel */ }
};
@ -1180,9 +1156,9 @@ static int rk_nfc_probe(struct udevice *dev)
nfc->cfg = (void *)dev_get_driver_data(dev);
nfc->dev = dev;
nfc->regs = (void *)dev_read_addr(dev);
if (IS_ERR(nfc->regs)) {
ret = PTR_ERR(nfc->regs);
nfc->regs = dev_read_addr_ptr(dev);
if (!nfc->regs) {
ret = -EINVAL;
goto release_nfc;
}

2
drivers/mtd/nand/raw/tegra_nand.c
View File

@ -906,7 +906,7 @@ static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
{
int err;
config->reg = (struct nand_ctlr *)dev_read_addr(dev);
config->reg = dev_read_addr_ptr(dev);
config->enabled = dev_read_enabled(dev);
config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,

2
drivers/mtd/nand/raw/zynq_nand.c
View File

@ -1085,7 +1085,7 @@ static int zynq_nand_probe(struct udevice *dev)
int ondie_ecc_enabled = 0;
int is_16bit_bw;
smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev);
smc->reg = dev_read_addr_ptr(dev);
of_nand = dev_read_subnode(dev, "nand-controller@0,0");
if (!ofnode_valid(of_nand)) {
of_nand = dev_read_subnode(dev, "flash@e1000000");

2
drivers/net/dm9000x.c
View File

@ -651,7 +651,7 @@ static int dm9000_of_to_plat(struct udevice *dev)
pdata->iobase = dev_read_addr_index(dev, 0);
db->base_io = (void __iomem *)pdata->iobase;
db->base_data = (void __iomem *)dev_read_addr_index(dev, 1);
db->base_data = dev_read_addr_index_ptr(dev, 1);
return 0;
}

4
drivers/net/dwmac_meson8b.c
View File

@ -41,8 +41,8 @@ static int dwmac_meson8b_of_to_plat(struct udevice *dev)
{
struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);
pdata->regs = (void *)dev_read_addr_index(dev, 1);
if ((fdt_addr_t)pdata->regs == FDT_ADDR_T_NONE)
pdata->regs = dev_read_addr_index_ptr(dev, 1);
if (!pdata->regs)
return -EINVAL;
pdata->dwmac_setup = (void *)dev_get_driver_data(dev);

2
drivers/net/mvmdio.c
View File

@ -208,7 +208,7 @@ static int mvmdio_probe(struct udevice *dev)
{
struct mvmdio_priv *priv = dev_get_priv(dev);
priv->mdio_base = (void *)dev_read_addr(dev);
priv->mdio_base = dev_read_addr_ptr(dev);
priv->type = (enum mvmdio_bus_type)dev_get_driver_data(dev);
return 0;

24
drivers/net/mvpp2.c
View File

@ -5300,18 +5300,18 @@ static int mvpp2_base_probe(struct udevice *dev)
}
/* Save base addresses for later use */
priv->base = (void *)devfdt_get_addr_index(dev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
priv->base = devfdt_get_addr_index_ptr(dev, 0);
if (!priv->base)
return -EINVAL;
if (priv->hw_version == MVPP21) {
priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
if (IS_ERR(priv->lms_base))
return PTR_ERR(priv->lms_base);
priv->lms_base = devfdt_get_addr_index_ptr(dev, 1);
if (!priv->lms_base)
return -EINVAL;
} else {
priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
if (IS_ERR(priv->iface_base))
return PTR_ERR(priv->iface_base);
priv->iface_base = devfdt_get_addr_index_ptr(dev, 1);
if (!priv->iface_base)
return -EINVAL;
/* Store common base addresses for all ports */
priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
@ -5350,10 +5350,10 @@ static int mvpp2_probe(struct udevice *dev)
if (priv->hw_version == MVPP21) {
int priv_common_regs_num = 2;
port->base = (void __iomem *)devfdt_get_addr_index(
port->base = devfdt_get_addr_index_ptr(
dev->parent, priv_common_regs_num + port->id);
if (IS_ERR(port->base))
return PTR_ERR(port->base);
if (!port->base)
return -EINVAL;
} else {
port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"gop-port-id", -1);

2
drivers/net/qe/dm_qe_uec_phy.c
View File

@ -97,7 +97,7 @@ static int qe_uec_mdio_probe(struct udevice *dev)
u32 num = 0;
int ret = -ENODEV;
priv->base = (struct ucc_mii_mng *)dev_read_addr(dev);
priv->base = dev_read_addr_ptr(dev);
base = (fdt_size_t)priv->base;
/*

4
drivers/pci/pci-aardvark.c
View File

@ -983,8 +983,8 @@ static int pcie_advk_of_to_plat(struct udevice *dev)
struct pcie_advk *pcie = dev_get_priv(dev);
/* Get the register base address */
pcie->base = (void *)dev_read_addr(dev);
if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
pcie->base = dev_read_addr_ptr(dev);
if (!pcie->base)
return -EINVAL;
return 0;

8
drivers/pci/pcie_dw_meson.c
View File

@ -337,15 +337,15 @@ static int meson_pcie_parse_dt(struct udevice *dev)
struct meson_pcie *priv = dev_get_priv(dev);
int ret;
priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
priv->dw.dbi_base = dev_read_addr_index_ptr(dev, 0);
if (!priv->dw.dbi_base)
return -ENODEV;
return -EINVAL;
dev_dbg(dev, "ELBI address is 0x%p\n", priv->dw.dbi_base);
priv->meson_cfg_base = (void *)dev_read_addr_index(dev, 1);
priv->meson_cfg_base = dev_read_addr_index_ptr(dev, 1);
if (!priv->meson_cfg_base)
return -ENODEV;
return -EINVAL;
dev_dbg(dev, "CFG address is 0x%p\n", priv->meson_cfg_base);

10
drivers/pci/pcie_dw_mvebu.c
View File

@ -564,14 +564,14 @@ static int pcie_dw_mvebu_of_to_plat(struct udevice *dev)
struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
/* Get the controller base address */
pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0);
if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)
pcie->ctrl_base = devfdt_get_addr_index_ptr(dev, 0);
if (!pcie->ctrl_base)
return -EINVAL;
/* Get the config space base address and size */
pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1,
&pcie->cfg_size);
if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1,
&pcie->cfg_size);
if (!pcie->cfg_base)
return -EINVAL;
return 0;

49
drivers/pci/pcie_dw_rockchip.c
View File

@ -353,15 +353,15 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
struct rk_pcie *priv = dev_get_priv(dev);
int ret;
priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
priv->dw.dbi_base = dev_read_addr_index_ptr(dev, 0);
if (!priv->dw.dbi_base)
return -ENODEV;
return -EINVAL;
dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);
priv->apb_base = (void *)dev_read_addr_index(dev, 1);
priv->apb_base = dev_read_addr_index_ptr(dev, 1);
if (!priv->apb_base)
return -ENODEV;
return -EINVAL;
dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
@ -375,29 +375,39 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
ret = reset_get_bulk(dev, &priv->rsts);
if (ret) {
dev_err(dev, "Can't get reset: %d\n", ret);
return ret;
goto rockchip_pcie_parse_dt_err_reset_get_bulk;
}
ret = clk_get_bulk(dev, &priv->clks);
if (ret) {
dev_err(dev, "Can't get clock: %d\n", ret);
return ret;
goto rockchip_pcie_parse_dt_err_clk_get_bulk;
}
ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
&priv->vpcie3v3);
if (ret && ret != -ENOENT) {
dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);
return ret;
goto rockchip_pcie_parse_dt_err_supply_regulator;
}
ret = generic_phy_get_by_index(dev, 0, &priv->phy);
if (ret) {
dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret);
return ret;
goto rockchip_pcie_parse_dt_err_phy_get_by_index;
}
return 0;
rockchip_pcie_parse_dt_err_phy_get_by_index:
/* regulators don't need release */
rockchip_pcie_parse_dt_err_supply_regulator:
clk_release_bulk(&priv->clks);
rockchip_pcie_parse_dt_err_clk_get_bulk:
reset_release_bulk(&priv->rsts);
rockchip_pcie_parse_dt_err_reset_get_bulk:
dm_gpio_free(dev, &priv->rst_gpio);
return ret;
}
/**
@ -426,7 +436,7 @@ static int rockchip_pcie_probe(struct udevice *dev)
ret = rockchip_pcie_init_port(dev);
if (ret)
return ret;
goto rockchip_pcie_probe_err_init_port;
dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
dev_seq(dev), pcie_dw_get_link_speed(&priv->dw),
@ -434,12 +444,21 @@ static int rockchip_pcie_probe(struct udevice *dev)
hose->first_busno);
return pcie_dw_prog_outbound_atu_unroll(&priv->dw,
PCIE_ATU_REGION_INDEX0,
PCIE_ATU_TYPE_MEM,
priv->dw.mem.phys_start,
priv->dw.mem.bus_start,
priv->dw.mem.size);
ret = pcie_dw_prog_outbound_atu_unroll(&priv->dw,
PCIE_ATU_REGION_INDEX0,
PCIE_ATU_TYPE_MEM,
priv->dw.mem.phys_start,
priv->dw.mem.bus_start,
priv->dw.mem.size);
if (!ret)
return ret;
rockchip_pcie_probe_err_init_port:
clk_release_bulk(&priv->clks);
reset_release_bulk(&priv->rsts);
dm_gpio_free(dev, &priv->rst_gpio);
return ret;
}
static const struct dm_pci_ops rockchip_pcie_ops = {

4
drivers/pci/pcie_imx.c
View File

@ -751,8 +751,8 @@ static int imx_pcie_of_to_plat(struct udevice *dev)
{
struct imx_pcie_priv *priv = dev_get_priv(dev);
priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
priv->dbi_base = devfdt_get_addr_index_ptr(dev, 0);
priv->cfg_base = devfdt_get_addr_index_ptr(dev, 1);
if (!priv->dbi_base || !priv->cfg_base)
return -EINVAL;

8
drivers/pci/pcie_layerscape_ep.c
View File

@ -250,13 +250,13 @@ static int ls_pcie_ep_probe(struct udevice *dev)
pcie_ep->pcie = pcie;
pcie->dbi = (void __iomem *)devfdt_get_addr_index(dev, 0);
pcie->dbi = devfdt_get_addr_index_ptr(dev, 0);
if (!pcie->dbi)
return -ENOMEM;
return -EINVAL;
pcie->ctrl = (void __iomem *)devfdt_get_addr_index(dev, 1);
pcie->ctrl = devfdt_get_addr_index_ptr(dev, 1);
if (!pcie->ctrl)
return -ENOMEM;
return -EINVAL;
ret = fdt_get_named_resource(gd->fdt_blob, dev_of_offset(dev),
"reg", "reg-names",

6
drivers/phy/allwinner/phy-sun50i-usb3.c
View File

@ -149,9 +149,9 @@ static int sun50i_usb3_phy_probe(struct udevice *dev)
return ret;
}
priv->regs = (void __iomem *)dev_read_addr(dev);
if (IS_ERR(priv->regs))
return PTR_ERR(priv->regs);
priv->regs = dev_read_addr_ptr(dev);
if (!priv->regs)
return -EINVAL;
return 0;
}

12
drivers/phy/marvell/comphy_core.c
View File

@ -88,13 +88,13 @@ static int comphy_probe(struct udevice *dev)
int res;
/* Save base addresses for later use */
chip_cfg->comphy_base_addr = (void *)devfdt_get_addr_index(dev, 0);
if (IS_ERR(chip_cfg->comphy_base_addr))
return PTR_ERR(chip_cfg->comphy_base_addr);
chip_cfg->comphy_base_addr = devfdt_get_addr_index_ptr(dev, 0);
if (!chip_cfg->comphy_base_addr)
return -EINVAL;
chip_cfg->hpipe3_base_addr = (void *)devfdt_get_addr_index(dev, 1);
if (IS_ERR(chip_cfg->hpipe3_base_addr))
return PTR_ERR(chip_cfg->hpipe3_base_addr);
chip_cfg->hpipe3_base_addr = devfdt_get_addr_index_ptr(dev, 1);
if (!chip_cfg->hpipe3_base_addr)
return -EINVAL;
if (device_is_compatible(dev, "marvell,comphy-a3700")) {
chip_cfg->comphy_init_map = comphy_a3700_init_serdes_map;

4
drivers/phy/phy-stm32-usbphyc.c
View File

@ -583,8 +583,8 @@ static int stm32_usbphyc_probe(struct udevice *dev)
phy_id = ofnode_read_u32_default(node, "reg", FDT_ADDR_T_NONE);
if (phy_id >= MAX_PHYS) {
dev_err(dev, "invalid reg value %lx for %s\n",
phy_id, ofnode_get_name(node));
dev_err(dev, "invalid reg value %llx for %s\n",
(fdt64_t)phy_id, ofnode_get_name(node));
return -ENOENT;
}

4
drivers/phy/qcom/phy-qcom-usb-hs-28nm.c
View File

@ -184,8 +184,8 @@ static int hsphy_probe(struct udevice *dev)
struct hsphy_priv *priv = dev_get_priv(dev);
int ret;
priv->base = (void *)dev_read_addr(dev);
if ((ulong)priv->base == FDT_ADDR_T_NONE)
priv->base = dev_read_addr_ptr(dev);
if (!priv->base)
return -EINVAL;
ret = reset_get_by_name(dev, "phy", &priv->phy_rst);

4
drivers/phy/qcom/phy-qcom-usb-ss.c
View File

@ -115,8 +115,8 @@ static int ssphy_probe(struct udevice *dev)
struct ssphy_priv *priv = dev_get_priv(dev);
int ret;
priv->base = (void *)dev_read_addr(dev);
if ((ulong)priv->base == FDT_ADDR_T_NONE)
priv->base = dev_read_addr_ptr(dev);
if (!priv->base)
return -EINVAL;
ret = ssphy_clk_init(dev, priv);

4
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
View File

@ -93,8 +93,8 @@ static int rockchip_p3phy_probe(struct udevice *dev)
struct udevice *syscon;
int ret;
priv->mmio = (void __iomem *)dev_read_addr(dev);
if ((fdt_addr_t)priv->mmio == FDT_ADDR_T_NONE)
priv->mmio = dev_read_addr_ptr(dev);
if (!priv->mmio)
return -EINVAL;
ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,

6
drivers/phy/rockchip/phy-rockchip-typec.c
View File

@ -674,9 +674,9 @@ static int rockchip_tcphy_probe(struct udevice *dev)
unsigned int reg;
int index, ret;
priv->reg_base = (void __iomem *)dev_read_addr(dev);
if (IS_ERR(priv->reg_base))
return PTR_ERR(priv->reg_base);
priv->reg_base = dev_read_addr_ptr(dev);
if (!priv->reg_base)
return -EINVAL;
ret = dev_read_u32_index(dev, "reg", 1, &reg);
if (ret) {

2
drivers/pwm/rk_pwm.c
View File

@ -30,7 +30,7 @@ struct rockchip_pwm_data {
};
struct rk_pwm_priv {
fdt_addr_t base;
uintptr_t base;
ulong freq;
u32 conf_polarity;
const struct rockchip_pwm_data *data;

2
drivers/pwm/tegra_pwm.c
View File

@ -59,7 +59,7 @@ static int tegra_pwm_of_to_plat(struct udevice *dev)
{
struct tegra_pwm_priv *priv = dev_get_priv(dev);
priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
priv->regs = dev_read_addr_ptr(dev);
return 0;
}

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