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mx6: Remove duplication of iomuxc structure

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There is no need to keep iomuxc_base_regs structure as it serves the exact same
purpose of the iomuxc structure, which is to provide access to the GPR
registers.

The additional fields of iomuxc_base_regs are not used. Other advantage of
'iomuxc' is that it has a shorter name and the variable declarations can fit
into a single line.

So remove iomuxc_base_regs structure and use iomuxc instead.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Fabio Estevam 2014-07-09 17:59:54 -03:00 committed by Stefano Babic
parent fa8cf3176c
commit 0a11d6f29c
6 changed files with 5 additions and 19 deletions
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3
arch/arm/imx-common/sata.c
View File

@ -12,8 +12,7 @@
int setup_sata(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))

9
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -764,15 +764,6 @@ struct anatop_regs {
#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
struct iomuxc_base_regs {
u32 gpr[14]; /* 0x000 */
u32 obsrv[5]; /* 0x038 */
u32 swmux_ctl[197]; /* 0x04c */
u32 swpad_ctl[250]; /* 0x360 */
u32 swgrp[26]; /* 0x748 */
u32 daisy[104]; /* 0x7b0..94c */
};
struct wdog_regs {
u16 wcr; /* Control */
u16 wsr; /* Service */

3
board/boundary/nitrogen6x/nitrogen6x.c
View File

@ -644,8 +644,7 @@ int overwrite_console(void)
int board_init(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,

3
board/freescale/mx6slevk/mx6slevk.c
View File

@ -130,8 +130,7 @@ int board_eth_init(bd_t *bis)
static int setup_fec(void)
{
struct iomuxc_base_regs *iomuxc_regs =
(struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
/* clear gpr1[14], gpr1[18:17] to select anatop clock */

3
board/gateworks/gw_ventana/gw_ventana.c
View File

@ -1122,8 +1122,7 @@ int dram_init(void)
int board_init(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,

3
board/solidrun/hummingboard/hummingboard.c
View File

@ -144,8 +144,7 @@ int board_phy_config(struct phy_device *phydev)
int board_eth_init(bd_t *bis)
{
struct iomuxc_base_regs *const iomuxc_regs =
(struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret = enable_fec_anatop_clock(ENET_25MHz);
if (ret)