From 2871dee83336cdafc38140dc6edd517eb5cac4b7 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:44 +0100 Subject: [PATCH 01/91] rockchip: avoid out-of-bounds when computing cpuid The expected length of the cpuid, as passed with cpuid_length, determines the size of cpuid_str string. Therefore, care should be taken to make sure nothing is accessing data out-of-bounds. Instead of using hardcoded values, derive them from cpuid_length. Cc: Quentin Schulz Reviewed-by: Kever Yang Reviewed-by: Dragan Simic Signed-off-by: Quentin Schulz --- arch/arm/mach-rockchip/misc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c index 7d03f0c2b67..15397cff009 100644 --- a/arch/arm/mach-rockchip/misc.c +++ b/arch/arm/mach-rockchip/misc.c @@ -102,7 +102,7 @@ int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length) int i; memset(cpuid_str, 0, sizeof(cpuid_str)); - for (i = 0; i < 16; i++) + for (i = 0; i < cpuid_length; i++) sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); debug("cpuid: %s\n", cpuid_str); @@ -111,13 +111,13 @@ int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length) * Mix the cpuid bytes using the same rules as in * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c */ - for (i = 0; i < 8; i++) { + for (i = 0; i < cpuid_length / 2; i++) { low[i] = cpuid[1 + (i << 1)]; high[i] = cpuid[i << 1]; } - serialno = crc32_no_comp(0, low, 8); - serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; + serialno = crc32_no_comp(0, low, cpuid_length / 2); + serialno |= (u64)crc32_no_comp(serialno, high, cpuid_length / 2) << 32; snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); oldid = env_get("cpuid#"); From 7400ed6a1fb81a212aa7144f5caf461d7033ffbd Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:45 +0100 Subject: [PATCH 02/91] rockchip: add weak function symbol called at the beginning of misc_init_r Most Rockchip boards who override misc_init_r do it only to call another function and keep the rest unchanged. Therefore to allow for less duplication, let's just add a weak function symbol that is called inside misc_init_r. Cc: Quentin Schulz Reviewed-by: Kever Yang Reviewed-by: Dragan Simic Signed-off-by: Quentin Schulz --- arch/arm/mach-rockchip/board.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 2620530e03f..d5cb59c10fa 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -297,6 +297,11 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) #endif #ifdef CONFIG_MISC_INIT_R +__weak int rockchip_early_misc_init_r(void) +{ + return 0; +} + __weak int misc_init_r(void) { const u32 cpuid_offset = CFG_CPUID_OFFSET; @@ -304,6 +309,10 @@ __weak int misc_init_r(void) u8 cpuid[cpuid_length]; int ret; + ret = rockchip_early_misc_init_r(); + if (ret) + return ret; + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); if (ret) return ret; From d79a9ef4f7279ad67d221f6b5f9604e1b8a92271 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:46 +0100 Subject: [PATCH 03/91] rockchip: google: gru: migrate to rockchip_early_misc_init_r Only setup_iodomain() differs from the original misc_init_r from Rockchip mach code, so let's use rockchip_early_misc_init_r instead of reimplementing the whole misc_init_r from Rockchip. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- board/google/gru/gru.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c index fbcf845e87d..ecbf702b035 100644 --- a/board/google/gru/gru.c +++ b/board/google/gru/gru.c @@ -11,7 +11,6 @@ #include #include #include -#include #define GRF_IO_VSEL_BT656_SHIFT 0 #define GRF_IO_VSEL_AUDIO_SHIFT 1 @@ -85,24 +84,9 @@ static void setup_iodomain(void) 1 << PMUGRF_CON0_VOL_SHIFT)); } -int misc_init_r(void) +int rockchip_early_misc_init_r(void) { - const u32 cpuid_offset = 0x7; - const u32 cpuid_length = 0x10; - u8 cpuid[cpuid_length]; - int ret; - setup_iodomain(); - ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); - if (ret) - return ret; - - ret = rockchip_cpuid_set(cpuid, cpuid_length); - if (ret) - return ret; - - ret = rockchip_setup_macaddr(); - - return ret; + return 0; } From f4e626dda85779e477095c5dbe959724a43e5ecb Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:47 +0100 Subject: [PATCH 04/91] rockchip: pine64: pinebook-pro: migrate to rockchip_early_misc_init_r Compared to the original misc_init_r from Rockchip mach code, setup_iodomain() is added and rockchip_setup_macaddr() is not called. It is assumed adding rockchip_setup_macaddr() back is fine. Let's use rockchip_early_misc_init_r instead of reimplementing the whole misc_init_r from Rockchip (the side effect being that rockchip_setup_macaddr() is back). Cc: Quentin Schulz Reviewed-by: Kever Yang Reviewed-by: Dragan Simic Reviewed-by: Peter Robinson Signed-off-by: Quentin Schulz --- .../pinebook-pro-rk3399/pinebook-pro-rk3399.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c index 4ad780767ea..2408a367305 100644 --- a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c +++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include @@ -54,23 +53,10 @@ static void setup_iodomain(void) rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); } -int misc_init_r(void) +int rockchip_early_misc_init_r(void) { - const u32 cpuid_offset = 0x7; - const u32 cpuid_length = 0x10; - u8 cpuid[cpuid_length]; - int ret; - setup_iodomain(); - ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); - if (ret) - return ret; - - ret = rockchip_cpuid_set(cpuid, cpuid_length); - if (ret) - return ret; - - return ret; + return 0; } #endif From 0312072a5d56377060d51f314a6b62d8df6a7874 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:48 +0100 Subject: [PATCH 05/91] rockchip: pine64: pinephone-pro: migrate to rockchip_early_misc_init_r Compared to the original misc_init_r from Rockchip mach code, setup_iodomain() is added and rockchip_setup_macaddr() is not called. It is assumed adding rockchip_setup_macaddr() back is fine. Let's use rockchip_early_misc_init_r instead of reimplementing the whole misc_init_r from Rockchip (the side effect being that rockchip_setup_macaddr() is back). Cc: Quentin Schulz Reviewed-by: Kever Yang Reviewed-by: Dragan Simic Reviewed-by: Peter Robinson Signed-off-by: Quentin Schulz --- .../pinephone-pro-rk3399/pinephone-pro-rk3399.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c index b6ccbb9c1c4..de75ee329d8 100644 --- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c +++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #define GRF_IO_VSEL_BT565_GPIO2AB 1 @@ -56,23 +55,11 @@ static void setup_iodomain(void) rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); } -int misc_init_r(void) +int rockchip_early_misc_init_r(void) { - const u32 cpuid_offset = 0x7; - const u32 cpuid_length = 0x10; - u8 cpuid[cpuid_length]; - int ret; - setup_iodomain(); - ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); - if (ret) - return ret; + return 0; - ret = rockchip_cpuid_set(cpuid, cpuid_length); - if (ret) - return ret; - - return ret; } #endif From 7672355fe0016ab3697439cd24c0524f9fe32e34 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:49 +0100 Subject: [PATCH 06/91] rockchip: pine64: rockpro64: migrate to rockchip_early_misc_init_r Only setup_iodomain() differs from the original misc_init_r from Rockchip mach code, so let's use rockchip_early_misc_init_r instead of reimplementing the whole misc_init_r from Rockchip. Cc: Quentin Schulz Reviewed-by: Kever Yang Reviewed-by: Dragan Simic Reviewed-by: Peter Robinson Signed-off-by: Quentin Schulz --- .../rockpro64_rk3399/rockpro64-rk3399.c | 20 ++----------------- 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c b/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c index d79084614f1..d0a694ead1d 100644 --- a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c +++ b/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c @@ -11,7 +11,6 @@ #include #include #include -#include #define GRF_IO_VSEL_BT565_SHIFT 0 #define PMUGRF_CON0_VSEL_SHIFT 8 @@ -31,26 +30,11 @@ static void setup_iodomain(void) rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); } -int misc_init_r(void) +int rockchip_early_misc_init_r(void) { - const u32 cpuid_offset = 0x7; - const u32 cpuid_length = 0x10; - u8 cpuid[cpuid_length]; - int ret; - setup_iodomain(); - ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); - if (ret) - return ret; - - ret = rockchip_cpuid_set(cpuid, cpuid_length); - if (ret) - return ret; - - ret = rockchip_setup_macaddr(); - - return ret; + return 0; } #endif From 1624d1ecd50848e06cc2a5573ef935ab6fbc0f8f Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:50 +0100 Subject: [PATCH 07/91] rockchip: theobroma-systems: puma: migrate to rockchip_early_misc_init_r Only setup_iodomain() and setup_boottargets differ from the original misc_init_r from Rockchip mach code, so let's use rockchip_early_misc_init_r instead of reimplementing the whole misc_init_r from Rockchip. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- .../puma_rk3399/puma-rk3399.c | 20 +------------------ 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index a82f97b2d54..98a818b135d 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -10,7 +10,6 @@ #include #include #include -#include #include "../common/common.h" static void setup_iodomain(void) @@ -27,25 +26,8 @@ static void setup_iodomain(void) rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT); } -int misc_init_r(void) +int rockchip_early_misc_init_r(void) { - const u32 cpuid_offset = 0x7; - const u32 cpuid_length = 0x10; - u8 cpuid[cpuid_length]; - int ret; - - ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); - if (ret) - return ret; - - ret = rockchip_cpuid_set(cpuid, cpuid_length); - if (ret) - return ret; - - ret = rockchip_setup_macaddr(); - if (ret) - return ret; - setup_iodomain(); setup_boottargets(); From 80cc4bec0032e2b4aa618a433e57440be6190a8a Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:51 +0100 Subject: [PATCH 08/91] rockchip: theobroma-systems: ringneck: migrate to rockchip_early_misc_init_r Only setup_boottargets differs from the original misc_init_r from Rockchip mach code, so let's use rockchip_early_misc_init_r instead of reimplementing the whole misc_init_r from Rockchip. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- .../ringneck_px30/ringneck-px30.c | 20 +------------------ 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c index ff7e414303d..bfebfe5136d 100644 --- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c +++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c @@ -4,29 +4,11 @@ */ #include -#include #include #include "../common/common.h" -int misc_init_r(void) +int rockchip_early_misc_init_r(void) { - const u32 cpuid_offset = 0x7; - const u32 cpuid_length = 0x10; - u8 cpuid[cpuid_length]; - int ret; - - ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); - if (ret) - return ret; - - ret = rockchip_cpuid_set(cpuid, cpuid_length); - if (ret) - return ret; - - ret = rockchip_setup_macaddr(); - if (ret) - return ret; - setup_boottargets(); return 0; From 08d61f87051972d5159bb1ba9f8a6167be3da317 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:52 +0100 Subject: [PATCH 09/91] rockchip: merge misc.c into board.c The functions aren't used anywhere else than in board.c, therefore, let's not expose them anymore at all. This merges misc.c and board.c together and removes the functions from the misc.h header file. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- arch/arm/include/asm/arch-rockchip/misc.h | 5 - arch/arm/mach-rockchip/Makefile | 1 - arch/arm/mach-rockchip/board.c | 125 ++++++++++++++++++++ arch/arm/mach-rockchip/misc.c | 135 ---------------------- 4 files changed, 125 insertions(+), 141 deletions(-) delete mode 100644 arch/arm/mach-rockchip/misc.c diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h index 4155af8c3b0..ef37ff1661a 100644 --- a/arch/arm/include/asm/arch-rockchip/misc.h +++ b/arch/arm/include/asm/arch-rockchip/misc.h @@ -6,9 +6,4 @@ * Rohan Garg */ -int rockchip_cpuid_from_efuse(const u32 cpuid_offset, - const u32 cpuid_length, - u8 *cpuid); -int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length); -int rockchip_setup_macaddr(void); void rockchip_capsule_update_board_setup(void); diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 1dc92066bbf..c07bdaee4c3 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -23,7 +23,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # meaning "turn it off". obj-y += boot_mode.o obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o -obj-$(CONFIG_MISC_INIT_R) += misc.o endif ifeq ($(CONFIG_TPL_BUILD),) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index d5cb59c10fa..80b4514852f 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -1,20 +1,32 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2019 Rockchip Electronics Co., Ltd. + * + * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ + * Rohan Garg + * + * Based on puma-rk3399.c: + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ #include #include #include +#include #include #include #include +#include #include #include #include +#include +#include #include #include #include #include +#include +#include #include #include #include @@ -297,6 +309,119 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) #endif #ifdef CONFIG_MISC_INIT_R +int rockchip_setup_macaddr(void) +{ +#if CONFIG_IS_ENABLED(HASH) && CONFIG_IS_ENABLED(SHA256) + int ret; + const char *cpuid = env_get("cpuid#"); + u8 hash[SHA256_SUM_LEN]; + int size = sizeof(hash); + u8 mac_addr[6]; + + /* Only generate a MAC address, if none is set in the environment */ + if (env_get("ethaddr")) + return 0; + + if (!cpuid) { + debug("%s: could not retrieve 'cpuid#'\n", __func__); + return -1; + } + + ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); + if (ret) { + debug("%s: failed to calculate SHA256\n", __func__); + return -1; + } + + /* Copy 6 bytes of the hash to base the MAC address on */ + memcpy(mac_addr, hash, 6); + + /* Make this a valid MAC address and set it */ + mac_addr[0] &= 0xfe; /* clear multicast bit */ + mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + eth_env_set_enetaddr("ethaddr", mac_addr); + + /* Make a valid MAC address for ethernet1 */ + mac_addr[5] ^= 0x01; + eth_env_set_enetaddr("eth1addr", mac_addr); +#endif + return 0; +} + +int rockchip_cpuid_from_efuse(const u32 cpuid_offset, + const u32 cpuid_length, + u8 *cpuid) +{ +#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || IS_ENABLED(CONFIG_ROCKCHIP_OTP) + struct udevice *dev; + int ret; + + /* retrieve the device */ +#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_efuse), &dev); +#elif IS_ENABLED(CONFIG_ROCKCHIP_OTP) + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); +#endif + if (ret) { + debug("%s: could not find efuse device\n", __func__); + return -1; + } + + /* read the cpu_id range from the efuses */ + ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length); + if (ret < 0) { + debug("%s: reading cpuid from the efuses failed\n", + __func__); + return -1; + } +#endif + return 0; +} + +int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length) +{ + u8 low[cpuid_length / 2], high[cpuid_length / 2]; + char cpuid_str[cpuid_length * 2 + 1]; + u64 serialno; + char serialno_str[17]; + const char *oldid; + int i; + + memset(cpuid_str, 0, sizeof(cpuid_str)); + for (i = 0; i < cpuid_length; i++) + sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); + + debug("cpuid: %s\n", cpuid_str); + + /* + * Mix the cpuid bytes using the same rules as in + * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c + */ + for (i = 0; i < cpuid_length / 2; i++) { + low[i] = cpuid[1 + (i << 1)]; + high[i] = cpuid[i << 1]; + } + + serialno = crc32_no_comp(0, low, cpuid_length / 2); + serialno |= (u64)crc32_no_comp(serialno, high, cpuid_length / 2) << 32; + snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); + + oldid = env_get("cpuid#"); + if (oldid && strcmp(oldid, cpuid_str) != 0) + printf("cpuid: value %s present in env does not match hardware %s\n", + oldid, cpuid_str); + + env_set("cpuid#", cpuid_str); + + /* Only generate serial# when none is set yet */ + if (!env_get("serial#")) + env_set("serial#", serialno_str); + + return 0; +} + __weak int rockchip_early_misc_init_r(void) { return 0; diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c deleted file mode 100644 index 15397cff009..00000000000 --- a/arch/arm/mach-rockchip/misc.c +++ /dev/null @@ -1,135 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * RK3399: Architecture common definitions - * - * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ - * Rohan Garg - * - * Based on puma-rk3399.c: - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -int rockchip_setup_macaddr(void) -{ -#if CONFIG_IS_ENABLED(HASH) && CONFIG_IS_ENABLED(SHA256) - int ret; - const char *cpuid = env_get("cpuid#"); - u8 hash[SHA256_SUM_LEN]; - int size = sizeof(hash); - u8 mac_addr[6]; - - /* Only generate a MAC address, if none is set in the environment */ - if (env_get("ethaddr")) - return 0; - - if (!cpuid) { - debug("%s: could not retrieve 'cpuid#'\n", __func__); - return -1; - } - - ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); - if (ret) { - debug("%s: failed to calculate SHA256\n", __func__); - return -1; - } - - /* Copy 6 bytes of the hash to base the MAC address on */ - memcpy(mac_addr, hash, 6); - - /* Make this a valid MAC address and set it */ - mac_addr[0] &= 0xfe; /* clear multicast bit */ - mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ - eth_env_set_enetaddr("ethaddr", mac_addr); - - /* Make a valid MAC address for ethernet1 */ - mac_addr[5] ^= 0x01; - eth_env_set_enetaddr("eth1addr", mac_addr); -#endif - return 0; -} - -int rockchip_cpuid_from_efuse(const u32 cpuid_offset, - const u32 cpuid_length, - u8 *cpuid) -{ -#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || IS_ENABLED(CONFIG_ROCKCHIP_OTP) - struct udevice *dev; - int ret; - - /* retrieve the device */ -#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(rockchip_efuse), &dev); -#elif IS_ENABLED(CONFIG_ROCKCHIP_OTP) - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(rockchip_otp), &dev); -#endif - if (ret) { - debug("%s: could not find efuse device\n", __func__); - return -1; - } - - /* read the cpu_id range from the efuses */ - ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length); - if (ret < 0) { - debug("%s: reading cpuid from the efuses failed\n", - __func__); - return -1; - } -#endif - return 0; -} - -int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length) -{ - u8 low[cpuid_length / 2], high[cpuid_length / 2]; - char cpuid_str[cpuid_length * 2 + 1]; - u64 serialno; - char serialno_str[17]; - const char *oldid; - int i; - - memset(cpuid_str, 0, sizeof(cpuid_str)); - for (i = 0; i < cpuid_length; i++) - sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); - - debug("cpuid: %s\n", cpuid_str); - - /* - * Mix the cpuid bytes using the same rules as in - * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c - */ - for (i = 0; i < cpuid_length / 2; i++) { - low[i] = cpuid[1 + (i << 1)]; - high[i] = cpuid[i << 1]; - } - - serialno = crc32_no_comp(0, low, cpuid_length / 2); - serialno |= (u64)crc32_no_comp(serialno, high, cpuid_length / 2) << 32; - snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); - - oldid = env_get("cpuid#"); - if (oldid && strcmp(oldid, cpuid_str) != 0) - printf("cpuid: value %s present in env does not match hardware %s\n", - oldid, cpuid_str); - - env_set("cpuid#", cpuid_str); - - /* Only generate serial# when none is set yet */ - if (!env_get("serial#")) - env_set("serial#", serialno_str); - - return 0; -} From 74029381ccba1a1bc85cd05a1d108f92ffdd3716 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:53 +0100 Subject: [PATCH 10/91] rockchip: transform rockchip_capsule_update_board_setup into a weak function symbol There's only one user of rockchip_capsule_update_board_setup, which is in board.c, and only one board defines it, so instead of having a header only for one function symbol, let's just use a weak symbol instead. Cc: Quentin Schulz Reviewed-by: Kever Yang Reviewed-by: Dragan Simic Reviewed-by: Peter Robinson Signed-off-by: Quentin Schulz --- arch/arm/include/asm/arch-rockchip/misc.h | 9 --------- arch/arm/mach-rockchip/board.c | 5 ++++- 2 files changed, 4 insertions(+), 10 deletions(-) delete mode 100644 arch/arm/include/asm/arch-rockchip/misc.h diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h deleted file mode 100644 index ef37ff1661a..00000000000 --- a/arch/arm/include/asm/arch-rockchip/misc.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * RK3399: Architecture common definitions - * - * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ - * Rohan Garg - */ - -void rockchip_capsule_update_board_setup(void); diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 80b4514852f..4f666aee706 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) @@ -148,6 +147,10 @@ void set_dfu_alt_info(char *interface, char *devstr) env_set("dfu_alt_info", buf); } +__weak void rockchip_capsule_update_board_setup(void) +{ +} + static void gpt_capsule_update_setup(void) { int p, i, ret; From 5d710738bb1e0ff2bb93ce7baf4c9691ce919b53 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:54 +0100 Subject: [PATCH 11/91] rockchip: rk3588: disable force_jtag by default Rockchip SoCs can automatically switch between jtag and sdmmc based on the following rules: - all the SDMMC pins including SDMMC_DET set as SDMMC function in GRF, - force_jtag bit in GRF is 1, - SDMMC_DET is low (no card detected), Note that the BootROM may mux all SDMMC pins in their SDMMC function or not, depending on the boot medium that were tried. Because SDMMC_DET pin is not guaranteed to be used as an SD card card detect pin, it could be low at boot or even switch at runtime, which would enable the jtag function and render the SD card unusable. This is the case for RK3588 Jaguar for example which has an SD card connector without an SD card card detect signal and has SDMMC_DET connected to ground. Because enabling JTAG at runtime could be a security issue and also to make sure that we have a consistent behavior on all boards by default, let's disable this force_jtag feature. However, let's make it easy to reenable it for debugging purposes by hiding it behind a Kconfig symbol. Note that soc_con[0] is reserved. But considering that it's way more user-friendly to access soc_con1 from the TRM with soc_con[1] than soc_con[0], and that soc_con0 would actually be located at 4 bytes before soc_con1, let's just make soc_con0 part of the soc_con array. Cc: Quentin Schulz Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/grf_rk3588.h | 24 +++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 24 +++++++++++++++++++ arch/arm/mach-rockchip/rk3588/rk3588.c | 11 +++++++++ 3 files changed, 59 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h index e0694068bb1..f0ecff97f0b 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h @@ -32,4 +32,28 @@ struct rk3588_pmu1grf { check_member(rk3588_pmu1grf, sd_detect_cnt, 0x03b0); +#define SYS_GRF_BASE 0xfd58c000 + +struct rk3588_sysgrf { + unsigned int wdt_con0; + unsigned int reserved0[(0x0010 - 0x0000) / 4 - 1]; + unsigned int uart_con[2]; + unsigned int reserved1[(0x00c0 - 0x0014) / 4 - 1]; + unsigned int gic_con0; + unsigned int reserved2[(0x0200 - 0x00c0) / 4 - 1]; + unsigned int memcfg_con[32]; + unsigned int reserved3[(0x0300 - 0x027c) / 4 - 1]; + /* soc_con0 is reserved */ + unsigned int soc_con[14]; + unsigned int reserved4[(0x0380 - 0x0334) / 4 - 1]; + unsigned int soc_status[4]; + unsigned int reserved5[(0x0500 - 0x038c) / 4 - 1]; + unsigned int otp_key08; + unsigned int otp_key0d; + unsigned int otp_key0e; + unsigned int reserved6[(0x0600 - 0x0508) / 4 - 1]; + unsigned int chip_id; +}; + +check_member(rk3588_sysgrf, chip_id, 0x0600); #endif /*__SOC_ROCKCHIP_RK3588_GRF_H__ */ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 1bc7ee90427..343361a5327 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -501,6 +501,30 @@ config SPL_ROCKCHIP_EARLYRETURN_TO_BROM This enables support code in the BOOT0 hook for the SPL stage to allow multiple entries. +config ROCKCHIP_DISABLE_FORCE_JTAG + bool "Disable force_jtag feature" + default y + depends on SPL + help + Rockchip SoCs can automatically switch between jtag and sdmmc based + on the following rules: + - all the SDMMC pins including SDMMC_DET set as SDMMC function in + GRF, + - force_jtag bit in GRF is 1, + - SDMMC_DET is low (no card detected), + + Some HW design may not route the SD card card detect to SDMMC_DET + pin, thus breaking the SD card support in some cases because JTAG + would be auto-enabled by mistake. + + Also, enabling JTAG at runtime may be an undesired feature, e.g. + because it could be a security vulnerability. + + This disables force_jtag feature, which you may want for debugging + purposes. + + If unsure, say Y. + config TPL_ROCKCHIP_EARLYRETURN_TO_BROM bool "TPL requires early-return (for RK3188-style BROM) to BROM" depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 38e95a6e2b2..d18c4e4b411 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -35,6 +36,8 @@ #define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c #define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60 +#define SYS_GRF_FORCE_JTAG BIT(14) + /** * Boot-device identifiers used by the BROM on RK3588 when device is booted * from SPI flash. IOMUX used for SPI flash affect the value used by the BROM @@ -134,6 +137,9 @@ void rockchip_stimer_init(void) int arch_cpu_init(void) { #ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG + static struct rk3588_sysgrf * const sys_grf = (void *)SYS_GRF_BASE; +#endif int secure_reg; /* Set the SDMMC eMMC crypto_ns FSPI access secure area */ @@ -168,6 +174,11 @@ int arch_cpu_init(void) secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG); secure_reg &= 0xffff0000; writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG); + +#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG + /* Disable JTAG exposed on SDMMC */ + rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG); +#endif #endif return 0; From 8ed8517d9e54424df1966f862cb7620c5996722a Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:55 +0100 Subject: [PATCH 12/91] rockchip: rk3588: add constants for some register address spaces It's one thing to have the register mapped via a well-defined struct but it's another to be able to make use of it. For that to happen, one needs to cast the physical address memory of the beginning of the register address space with the struct. Since this cannot change, let's hardcode it in the include files so that users do not need to duplicate this line of code in their own implementation. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 ++ arch/arm/include/asm/arch-rockchip/ioc_rk3588.h | 6 ++++++ arch/arm/mach-rockchip/rk3588/rk3588.c | 4 ---- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h index 7f4a9085392..a4507e5fdd7 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h @@ -63,6 +63,8 @@ struct rk3588_pll { unsigned int reserved0[3]; }; +#define CRU_BASE 0xfd7c0000 + struct rk3588_cru { struct rk3588_pll pll[18]; unsigned int reserved0[16];/* Address Offset: 0x0240 */ diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h index 5a656f850c7..7ad98466c39 100644 --- a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h @@ -5,6 +5,8 @@ #ifndef _ASM_ARCH_IOC_RK3588_H #define _ASM_ARCH_IOC_RK3588_H +#define BUS_IOC_BASE 0xfd5f8000 + struct rk3588_bus_ioc { unsigned int reserved0000[3]; /* Address Offset: 0x0000 */ unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x000C */ @@ -48,6 +50,8 @@ struct rk3588_bus_ioc { check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C); +#define PMU1_IOC_BASE 0xfd5f0000 + struct rk3588_pmu1_ioc { unsigned int gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */ unsigned int gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */ @@ -70,6 +74,8 @@ struct rk3588_pmu1_ioc { check_member(rk3588_pmu1_ioc, xin_con, 0x0040); +#define PMU2_IOC_BASE 0xfd5f4000 + struct rk3588_pmu2_ioc { unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */ unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */ diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index d18c4e4b411..7a190e6aa18 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -26,10 +26,6 @@ #define FW_SYSM_MST26_REG 0xa8 #define FW_SYSM_MST27_REG 0xac -#define PMU1_IOC_BASE 0xfd5f0000 -#define PMU2_IOC_BASE 0xfd5f4000 - -#define BUS_IOC_BASE 0xfd5f8000 #define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40 #define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48 #define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58 From eda2c8736e63b0e0e308780663ef048cb918b847 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:56 +0100 Subject: [PATCH 13/91] rockchip: migrate hardware.h inclusion into appropriate files hardware.h is only defining macros which are "wrappers" around writel(). writel() is however not available in hardware.h, needs to be included. This means in order to use the wrappers in hardware.h, one also needs to include the header. However, this cannot be done currently because hardware.h is included in include/configs files, which are implicitly included by every code file by default, which makes the compilation of arch/arm/cpu/armv8/u-boot.lds fail because ALIGN (the ARM assembly directive) got redefined by some of the include files coming from . Because nothing in the include/configs file actually use hardware.h, let's remove the inclusion of hardware.h from the include/configs files and explicitly add it wherever it is required. This prepares for the next commit where will be included in hardware.h. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- arch/arm/mach-rockchip/rk3066/rk3066.c | 1 + drivers/ram/rockchip/dmc-rk3368.c | 1 + drivers/ram/rockchip/sdram_rk3188.c | 1 + drivers/ram/rockchip/sdram_rk3288.c | 1 + include/configs/rk3036_common.h | 1 - include/configs/rk3066_common.h | 1 - include/configs/rk3188_common.h | 1 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3368_common.h | 1 - include/configs/rv1108_common.h | 1 - 11 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c index 78c7d894f90..6661b788295 100644 --- a/arch/arm/mach-rockchip/rk3066/rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -7,6 +7,7 @@ #include #include #include +#include #define GRF_BASE 0x20008000 diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index f36be941a38..859fc47030f 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index ad9f936df55..d23d4231798 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index c99118fd612..3177051dd12 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index c2abd14e114..0bf9e8b9a2e 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RK3036_COMMON_H #define __CONFIG_RK3036_COMMON_H -#include #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index d70c8f77d48..6a3b6900463 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3066_COMMON_H #define __CONFIG_RK3066_COMMON_H -#include #include "rockchip-common.h" #define CFG_IRAM_BASE 0x10080000 diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index a8cee1e44d4..98f2c25f3cf 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3188_COMMON_H #define __CONFIG_RK3188_COMMON_H -#include #include "rockchip-common.h" #define CFG_IRAM_BASE 0x10080000 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 15f77df3e17..bab4ca015f7 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RK322X_COMMON_H #define __CONFIG_RK322X_COMMON_H -#include #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 3063076a97a..0c449e31099 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3288_COMMON_H #define __CONFIG_RK3288_COMMON_H -#include #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index ccb5369b901..d488f8d477a 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -8,7 +8,6 @@ #include "rockchip-common.h" -#include #include #define CFG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 3bf70a0e0ae..ff28236a21d 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RV1108_COMMON_H #define __CONFIG_RV1108_COMMON_H -#include #include "rockchip-common.h" #define CFG_IRAM_BASE 0x10080000 From 9f5df9a3ef6b7470cc7a74d712628b5d085e5314 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:57 +0100 Subject: [PATCH 14/91] rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.h The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- arch/arm/include/asm/arch-rockchip/hardware.h | 2 ++ arch/arm/mach-rockchip/cpu-info.c | 1 - arch/arm/mach-rockchip/px30/px30.c | 1 - arch/arm/mach-rockchip/rk3036/rk3036.c | 1 - arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 1 - arch/arm/mach-rockchip/rk3066/rk3066.c | 1 - arch/arm/mach-rockchip/rk3188/rk3188.c | 1 - arch/arm/mach-rockchip/rk322x/rk322x.c | 1 - arch/arm/mach-rockchip/rk3288/rk3288.c | 1 - arch/arm/mach-rockchip/rk3308/rk3308.c | 1 - arch/arm/mach-rockchip/rk3328/rk3328.c | 1 - arch/arm/mach-rockchip/rk3368/rk3368.c | 1 - arch/arm/mach-rockchip/rk3399/rk3399.c | 1 - arch/arm/mach-rockchip/rk3568/rk3568.c | 1 - arch/arm/mach-rockchip/rk3588/rk3588.c | 1 - arch/arm/mach-rockchip/rv1126/rv1126.c | 1 - board/elgin/elgin_rv1108/elgin_rv1108.c | 1 - board/firefly/firefly-rk3308/roc_cc_rk3308.c | 1 - board/google/gru/gru.c | 1 - board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c | 1 - board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c | 1 - board/pine64/rockpro64_rk3399/rockpro64-rk3399.c | 1 - board/rockchip/evb_rv1108/evb_rv1108.c | 1 - board/theobroma-systems/puma_rk3399/puma-rk3399.c | 1 - board/vamrs/rock960_rk3399/rock960-rk3399.c | 1 - drivers/clk/rockchip/clk_pll.c | 1 - drivers/clk/rockchip/clk_px30.c | 1 - drivers/clk/rockchip/clk_rk3036.c | 1 - drivers/clk/rockchip/clk_rk3066.c | 1 - drivers/clk/rockchip/clk_rk3128.c | 1 - drivers/clk/rockchip/clk_rk3188.c | 1 - drivers/clk/rockchip/clk_rk322x.c | 1 - drivers/clk/rockchip/clk_rk3288.c | 1 - drivers/clk/rockchip/clk_rk3308.c | 1 - drivers/clk/rockchip/clk_rk3328.c | 1 - drivers/clk/rockchip/clk_rk3368.c | 1 - drivers/clk/rockchip/clk_rk3399.c | 1 - drivers/clk/rockchip/clk_rk3568.c | 1 - drivers/clk/rockchip/clk_rk3588.c | 1 - drivers/clk/rockchip/clk_rv1108.c | 1 - drivers/clk/rockchip/clk_rv1126.c | 1 - drivers/gpio/rk_gpio.c | 1 - drivers/net/gmac_rockchip.c | 1 - drivers/ram/rockchip/dmc-rk3368.c | 1 - drivers/ram/rockchip/sdram_px30.c | 1 - drivers/ram/rockchip/sdram_rk3066.c | 1 - drivers/ram/rockchip/sdram_rk3188.c | 1 - drivers/ram/rockchip/sdram_rk322x.c | 1 - drivers/ram/rockchip/sdram_rk3288.c | 1 - drivers/ram/rockchip/sdram_rk3399.c | 1 - drivers/ram/rockchip/sdram_rv1126.c | 1 - drivers/rng/rockchip_rng.c | 1 - drivers/sysreset/sysreset_rockchip.c | 1 - drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 1 - drivers/video/rockchip/rk3288_hdmi.c | 1 - drivers/video/rockchip/rk3288_mipi.c | 1 - drivers/video/rockchip/rk3288_vop.c | 1 - drivers/video/rockchip/rk3399_hdmi.c | 1 - drivers/video/rockchip/rk3399_mipi.c | 1 - drivers/video/rockchip/rk3399_vop.c | 1 - drivers/video/rockchip/rk_edp.c | 1 - drivers/video/rockchip/rk_hdmi.c | 1 - drivers/video/rockchip/rk_lvds.c | 1 - 63 files changed, 2 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h index 62e8bed8f31..e4662a2d52d 100644 --- a/arch/arm/include/asm/arch-rockchip/hardware.h +++ b/arch/arm/include/asm/arch-rockchip/hardware.h @@ -6,6 +6,8 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H +#include + #define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | (set)) #define RK_SETBITS(set) RK_CLRSETBITS(0, set) #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index dac24910e0c..a62ff53c6a0 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index fc7456e680c..b4f655fa4b3 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c index 0a072cf03a8..e8130abdd77 100644 --- a/arch/arm/mach-rockchip/rk3036/rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/rk3036.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index fcae65b2e5a..07cd29a33e6 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -4,7 +4,6 @@ */ #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c index 6661b788295..9a95ff85041 100644 --- a/arch/arm/mach-rockchip/rk3066/rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index c807221f33f..ffdcaa49a1e 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c index a304795fec6..712c0524266 100644 --- a/arch/arm/mach-rockchip/rk322x/rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index d9f782e342b..c77c56c1dab 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index 6f121bf1304..27a748327e3 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index b591d38fe41..b8e657e9bf4 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -10,7 +10,6 @@ #include #include #include -#include #define CRU_BASE 0xFF440000 #define GRF_BASE 0xFF100000 diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index d009b8758e5..651ba109020 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index a1aa0e3e8b5..7fa1d7c7b7a 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 69ef19cc85a..b30ea04f737 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 7a190e6aa18..eb65dafe3a2 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c index b9b898756f7..8589c46f10a 100644 --- a/arch/arm/mach-rockchip/rv1126/rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c index eb7a322d847..10398e7f712 100644 --- a/board/elgin/elgin_rv1108/elgin_rv1108.c +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c b/board/firefly/firefly-rk3308/roc_cc_rk3308.c index bdf3cc03dc5..99a52a77116 100644 --- a/board/firefly/firefly-rk3308/roc_cc_rk3308.c +++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c index ecbf702b035..9cb3a525204 100644 --- a/board/google/gru/gru.c +++ b/board/google/gru/gru.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c index 2408a367305..5e758ea6cd9 100644 --- a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c +++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c index de75ee329d8..c9b0d5a061d 100644 --- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c +++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c b/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c index d0a694ead1d..fd78ad60d14 100644 --- a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c +++ b/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c index e6ac598648d..0d7a486bed7 100644 --- a/board/rockchip/evb_rv1108/evb_rv1108.c +++ b/board/rockchip/evb_rv1108/evb_rv1108.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 98a818b135d..8b998ef4556 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index a7fc38d42f8..876be8ed9e1 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 1bb31b3313b..66f8bb16695 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index 93b76538509..2875c152b20 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 6bc6d41ad61..6238b14c29e 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c index 2c12f6e0441..f83335df6db 100644 --- a/drivers/clk/rockchip/clk_rk3066.c +++ b/drivers/clk/rockchip/clk_rk3066.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c index 13e176cdad1..182754e7052 100644 --- a/drivers/clk/rockchip/clk_rk3128.c +++ b/drivers/clk/rockchip/clk_rk3128.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index ebdd1b3f99a..f98b46a0f73 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 28cdba75758..9371c4f63a4 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index e24c32c0a2a..0b7eefad15f 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index d0a3f654466..7755b016111 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index ef97381f0ed..cfec1d974ac 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 3406ff592e1..1c5dfaa3800 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index c37e8a53a26..80f65a237e8 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 68f5bbbb9e5..57ef27dda89 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index a995dd5591d..8f33843179b 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index b0c889ae156..fc442f7eebe 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c index 580c0b1b0cf..cfdfcbdb0f4 100644 --- a/drivers/clk/rockchip/clk_rv1126.c +++ b/drivers/clk/rockchip/clk_rv1126.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 4a6ae554bf7..c5e096bb1ad 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 04008d2b198..c1bae3f68bd 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index 859fc47030f..5279bf0a154 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c index 2728d93be32..21498e89570 100644 --- a/drivers/ram/rockchip/sdram_px30.c +++ b/drivers/ram/rockchip/sdram_px30.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3066.c b/drivers/ram/rockchip/sdram_rk3066.c index 39c0be56a6e..562cf544c90 100644 --- a/drivers/ram/rockchip/sdram_rk3066.c +++ b/drivers/ram/rockchip/sdram_rk3066.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index d23d4231798..e1b28c6e593 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index 892766a8b43..5fc23c11193 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index 3177051dd12..242d564a7d2 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 2bf8d48d25a..02cc4a38cf0 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rv1126.c b/drivers/ram/rockchip/sdram_rv1126.c index 0a78e18c732..849e15a9193 100644 --- a/drivers/ram/rockchip/sdram_rv1126.c +++ b/drivers/ram/rockchip/sdram_rv1126.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c index ce5cbee30ab..ce390864262 100644 --- a/drivers/rng/rockchip_rng.c +++ b/drivers/rng/rockchip_rng.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c index 0fc6b683f2b..f353f9b4c79 100644 --- a/drivers/sysreset/sysreset_rockchip.c +++ b/drivers/sysreset/sysreset_rockchip.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c index 5e75b6ec68c..fb784636e87 100644 --- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c +++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/video/rockchip/rk3288_hdmi.c b/drivers/video/rockchip/rk3288_hdmi.c index 8bedee55ad4..efa87540340 100644 --- a/drivers/video/rockchip/rk3288_hdmi.c +++ b/drivers/video/rockchip/rk3288_hdmi.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index c0dffa3cba2..9d42119c826 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -14,7 +14,6 @@ #include "rk_mipi.h" #include #include -#include #include #include #include diff --git a/drivers/video/rockchip/rk3288_vop.c b/drivers/video/rockchip/rk3288_vop.c index 44f32bb5fa2..a4683852ea0 100644 --- a/drivers/video/rockchip/rk3288_vop.c +++ b/drivers/video/rockchip/rk3288_vop.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/video/rockchip/rk3399_hdmi.c b/drivers/video/rockchip/rk3399_hdmi.c index 3041360c6ed..5f3f5d26886 100644 --- a/drivers/video/rockchip/rk3399_hdmi.c +++ b/drivers/video/rockchip/rk3399_hdmi.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index 7fc79ba9045..b62d8086674 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -14,7 +14,6 @@ #include "rk_mipi.h" #include #include -#include #include #include #include diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c index a34b491058f..cb589c7537e 100644 --- a/drivers/video/rockchip/rk3399_vop.c +++ b/drivers/video/rockchip/rk3399_vop.c @@ -13,7 +13,6 @@ #include #include #include -#include #include "rk_vop.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index dbd70ad583a..5f68a610e4a 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 8dcd4d59645..044a29ee47a 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include "rk_hdmi.h" diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c index 9cf3e3ca768..d0a015e31ee 100644 --- a/drivers/video/rockchip/rk_lvds.c +++ b/drivers/video/rockchip/rk_lvds.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include From 70f9212d61fe79c605b805c6eb0764b29f8ae3b6 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:58 +0100 Subject: [PATCH 15/91] rockchip: rk3588: bind MMC controllers in U-Boot proper pre-reloc Since commit 9e644284ab81 ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation"), bootph-pre-ram doesn't make U-Boot proper bind the device before relocation. While this is usually not much of an issue, it is when there's a lookup for devices by code running before the relocation. Such is the case of env_init() which calls env_driver_lookup() which calls env_get_location() which is a weak symbol and may call arch_env_get_location() also a weak symbol. Those are two functions that may traverse UCLASS to find some devices (e.g. board/theobroma-systems/common/common.c:arch_env_get_location()). This allows something in the env_init() call stack to be able to use uclasses for SD and eMMC controller on RK3588S/RK3588. This aligns the behavior with what seems to be all SoCs except RK356x family. Additionally, if any other env function (e.g. env_load) were to be used before relocation, this is also required as otherwise it wouldn't be able to find the MMC device(s). Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- arch/arm/dts/rk3588s-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index bf3b1ea8a3c..ac67c777ade 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -188,11 +188,13 @@ &sdmmc { bootph-pre-ram; + bootph-some-ram; u-boot,spl-fifo-mode; }; &sdhci { bootph-pre-ram; + bootph-some-ram; u-boot,spl-fifo-mode; }; From 642ee26bc82d230d6283fa98db676ecd12f7a58a Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:01:59 +0100 Subject: [PATCH 16/91] board: rockchip: add Theobroma-Systems RK3588 Jaguar SBC JAGUAR is a Single-Board Computer (SBC) based around the rk3588 SoC and is targeting Autonomous Mobile Robots (AMR). It features: * LPDDR4X (up to 16GB) * 1Gbps Ethernet on RJ45 connector (KSZ9031 or KSZ9131) * PCIe 3.0 4-lane on M.2 M-key connector * PCIe 2.1 1-lane on M.2 E-key * USB 2.0 on M.2 E-key * 2x USB3 OTG type-c ports with DP Alt-Mode * USB2 host port * HDMI output * 2x camera connectors, each exposing: * 2-lane MIPI-CSI * 1v2, 1v8, 2v8 power rails * I2C bus * GPIOs * PPS input * CAN * RS485 UART * FAN connector * SD card slot * eMMC (up to 256GB) * RTC backup battery * Companion microcontroller * ISL1208 RTC emulation * AMC6821 PWM emulation * On/off buzzer control * Secure Element * 80-pin Mezzanine connector for daughterboards: * GPIOs * 1Gbps Ethernet * PCIe 2.1 1-lane * 2x 2-lane MIPI-CSI * ADC channel * I2C bus * PWM * UART * SPI * SDIO * CAN * I2S * 1v8, 3v3, 5v0, dc-in (12-24V) power rails The Device Tree comes from next-20240110 Linux kernel. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3588-jaguar-u-boot.dtsi | 33 + arch/arm/dts/rk3588-jaguar.dts | 803 ++++++++++++++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 28 + board/theobroma-systems/jaguar_rk3588/Kconfig | 16 + .../jaguar_rk3588/MAINTAINERS | 13 + .../theobroma-systems/jaguar_rk3588/Makefile | 10 + .../jaguar_rk3588/jaguar_rk3588.c | 53 ++ configs/jaguar-rk3588_defconfig | 114 +++ doc/board/index.rst | 1 + doc/board/rockchip/rockchip.rst | 1 + doc/board/theobroma-systems/index.rst | 9 + doc/board/theobroma-systems/jaguar_rk3588.rst | 100 +++ include/configs/jaguar_rk3588.h | 15 + 14 files changed, 1197 insertions(+) create mode 100644 arch/arm/dts/rk3588-jaguar-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588-jaguar.dts create mode 100644 board/theobroma-systems/jaguar_rk3588/Kconfig create mode 100644 board/theobroma-systems/jaguar_rk3588/MAINTAINERS create mode 100644 board/theobroma-systems/jaguar_rk3588/Makefile create mode 100644 board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c create mode 100644 configs/jaguar-rk3588_defconfig create mode 100644 doc/board/theobroma-systems/index.rst create mode 100644 doc/board/theobroma-systems/jaguar_rk3588.rst create mode 100644 include/configs/jaguar_rk3588.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 784192125d3..c740c8bc0f5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -194,6 +194,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6b-io.dtb \ rk3588-evb1-v10.dtb \ + rk3588-jaguar.dtb \ rk3588-nanopc-t6.dtb \ rk3588s-orangepi-5.dtb \ rk3588-orangepi-5-plus.dtb \ diff --git a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi new file mode 100644 index 00000000000..dcda4f99d6e --- /dev/null +++ b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; +}; + +&emmc_pwrseq { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_reset { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + /* U-Boot currently cannot handle anything below HS200 for eMMC on RK3588 */ + /delete-property/ mmc-ddr-1_8v; + /delete-property/ cap-mmc-highspeed; +}; diff --git a/arch/arm/dts/rk3588-jaguar.dts b/arch/arm/dts/rk3588-jaguar.dts new file mode 100644 index 00000000000..4ce70fb75a3 --- /dev/null +++ b/arch/arm/dts/rk3588-jaguar.dts @@ -0,0 +1,803 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model = "Theobroma Systems RK3588-SBC Jaguar"; + compatible = "tsd,rk3588-jaguar", "rockchip,rk3588"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + /* Can be controlled through SW2 but also GPIO1 on CP2102 on P20 */ + button-bios-disable { + label = "BIOS_DISABLE"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdhci; + mmc1 = &sdmmc; + rtc0 = &rtc_twi; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + /* DCIN is 12-24V but standard is 12V */ + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led1_pin>; + status = "okay"; + + /* LED1 on PCB */ + led-1 { + gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + color = ; + }; + }; + + pps { + compatible = "pps-gpio"; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v2_s3: vcc-1v2-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v2_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* Exposed on P14 and P15 */ + vcc_2v8_s3: vcc-2v8-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_5v0_usb_a: vcc-5v0-usb-a-regulator { + compatible = "regulator-fixed"; + regulator-name = "usb_a_vcc"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc_5v0_usb_c1: vcc-5v0-usb-c1-regulator { + compatible = "regulator-fixed"; + regulator-name = "5v_usbc1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc_5v0_usb_c2: vcc-5v0-usb-c2-regulator { + compatible = "regulator-fixed"; + regulator-name = "5v_usbc2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc3v3_mdot2: vcc3v3-mdot2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_mdot2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1_ps { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + phy-supply = <&vcc_1v2_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_rx_bus2 + &gmac0_tx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + ð0_pins + ð_reset>; + tx_delay = <0x10>; + rx_delay = <0x10>; + snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 100000>; + + status = "okay"; +}; + +&gpio1 { + mdot2e-w-disable1-n-hog { + gpios = ; + output-low; + line-name = "m.2 E-key W_DISABLE1#"; + gpio-hog; + }; +}; + +&gpio4 { + mdot2e-w-disable2-n-hog { + gpios = ; + output-low; + line-name = "m.2 E-key W_DISABLE2#"; + gpio-hog; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + }; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1m4_xfer>; +}; + +&i2c6 { + pinctrl-0 = <&i2c6m4_xfer>; +}; + +&i2c7 { + status = "okay"; + + /* SE050 Secure Element at 0x48; GPIO1_A4 for enable pin */ + + /* Also on 0x55 */ + eeprom@54 { + compatible = "st,24c04", "atmel,24c04"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@6 { + /* KSZ9031 or KSZ9131 */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x6>; + clocks = <&cru REFCLKO25M_ETH0_OUT>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; /* WIFI_PERST0# */ + vpcie3v3-supply = <&vcc3v3_mdot2>; + status = "okay"; +}; + +&pinctrl { + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + eth_reset: eth-reset { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led1_pin: led1-pin { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-pwrseq = <&emmc_pwrseq>; + no-sdio; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; + supports-cqe; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdmmc { + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-name = "vcca_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-name = "vdda_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-name = "vcca_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdda_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdda_0v75_s0: nldo-reg3 { + regulator-name = "vdda_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-name = "vdda_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc_5v0_usb_a>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +/* Mule-ATtiny debug UART; typically baudrate 9600 */ +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +/* Main debug interface on P20 micro-USB B port and P21 header */ +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* RS485 on P19 */ +&uart3 { + pinctrl-0 = <&uart3m2_xfer &uart3_rtsn>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* Mule-ATtiny UPDI flashing UART */ +&uart7 { + pinctrl-0 = <&uart7m0_xfer>; + status = "okay"; +}; + +/* host0 on P10 USB-A */ +&usb_host0_ehci { + status = "okay"; +}; + +/* host0 on P10 USB-A */ +&usb_host0_ohci { + status = "okay"; +}; + +/* host1 on M.2 E-key */ +&usb_host1_ehci { + status = "okay"; +}; + +/* host1 on M.2 E-key */ +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index a2193fbd41f..c6b79b6cd75 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -6,6 +6,33 @@ config TARGET_EVB_RK3588 help RK3588 EVB is a evaluation board for Rockchp RK3588. +config TARGET_JAGUAR_RK3588 + bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)" + select BOARD_LATE_INIT + help + The SBC-RK3588-AMR is a Single Board Computer designed by + Theobroma Systems for autonomous mobile robots. + + It provides the following features: + * up to 32GB LDDR4 + * up to 128GB on-module eMMC (with 8-bit 1.8V interface) + * SD card + * Gigabit Ethernet + * 1x USB-A 2.0 host + * PCIe M.2 2230 Key M (Gen 2 1-lane) for WiFi+BT + * PCIe M.2 2280 Key M (Gen 3 4-lane) for NVMe + * CAN + * RS485 UART + * 2x USB Type-C 3.1 host/device + * HDMI output + * 2x camera connectors (MIPI-CSI 2-lane + I2C/SPI for IMUs + GPIOs) + * EEPROM + * Secure Element + * ATtiny companion controller implementing: + - low-power RTC functionality (ISL1208 emulation) + - fan controller (AMC6821 emulation) + * 80-pin Mezzanine connector + config TARGET_NANOPCT6_RK3588 bool "FriendlyElec NanoPC-T6 RK3588 board" select BOARD_LATE_INIT @@ -174,5 +201,6 @@ source board/turing/turing-rk1-rk3588/Kconfig source board/rockchip/evb_rk3588/Kconfig source board/radxa/rock5a-rk3588s/Kconfig source board/radxa/rock5b-rk3588/Kconfig +source board/theobroma-systems/jaguar_rk3588/Kconfig endif diff --git a/board/theobroma-systems/jaguar_rk3588/Kconfig b/board/theobroma-systems/jaguar_rk3588/Kconfig new file mode 100644 index 00000000000..0ff417af4dd --- /dev/null +++ b/board/theobroma-systems/jaguar_rk3588/Kconfig @@ -0,0 +1,16 @@ +if TARGET_JAGUAR_RK3588 + +config SYS_BOARD + default "jaguar_rk3588" + +config SYS_VENDOR + default "theobroma-systems" + +config SYS_CONFIG_NAME + default "jaguar_rk3588" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ENV_IS_NOWHERE + +endif diff --git a/board/theobroma-systems/jaguar_rk3588/MAINTAINERS b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS new file mode 100644 index 00000000000..28fae4b479f --- /dev/null +++ b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS @@ -0,0 +1,13 @@ +JAGUAR-RK3588 (SBC-RK3588-AMR Single Board Computer) +M: Klaus Goger +M: Quentin Schulz +M: Heiko Stuebner +S: Maintained +F: board/theobroma-systems/jaguar_rk3588 +F: board/theobroma-systems/common +F: doc/board/theobroma-systems/ +F: include/configs/jaguar_rk3588.h +F: arch/arm/dts/rk3588-jaguar* +F: configs/jaguar-rk3588_defconfig +W: https://theobroma-systems.com/product/jaguar-sbc-rk3588/ +T: git git://git.theobroma-systems.com/jaguar-u-boot.git diff --git a/board/theobroma-systems/jaguar_rk3588/Makefile b/board/theobroma-systems/jaguar_rk3588/Makefile new file mode 100644 index 00000000000..532aab01532 --- /dev/null +++ b/board/theobroma-systems/jaguar_rk3588/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += jaguar_rk3588.o +ifneq ($(CONFIG_SPL_BUILD),y) +obj-y += ../common/common.o +endif diff --git a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c new file mode 100644 index 00000000000..a6d44f10db3 --- /dev/null +++ b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 Theobroma Systems Design und Consulting GmbH + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/common.h" + +#define GPIO2C3_SEL_MASK GENMASK(15, 12) +#define GPIO2C3_ETH0_REFCLKO_25M FIELD_PREP(GPIO2C3_SEL_MASK, 1) + +#define REFCLKO25M_ETH0_OUT_SEL_MASK BIT(15) +#define REFCLKO25M_ETH0_OUT_SEL_CPLL FIELD_PREP(REFCLKO25M_ETH0_OUT_SEL_MASK, 1) +#define REFCLKO25M_ETH0_OUT_DIV_MASK GENMASK(14, 8) +#define REFCLKO25M_ETH0_OUT_DIV(x) FIELD_PREP(REFCLKO25M_ETH0_OUT_DIV_MASK, (x) - 1) + +#define REFCLKO25M_ETH0_OUT_EN BIT(4) + +void setup_eth0refclko(void) +{ + /* Configure and enable ETH0_REFCLKO_25MHz */ + static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE; + static struct rk3588_cru * const cru = (void *)CRU_BASE; + + /* 1. Pinmux */ + rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_l, GPIO2C3_SEL_MASK, GPIO2C3_ETH0_REFCLKO_25M); + /* 2. Parent clock selection + divider => CPLL (1.5GHz) / 60 => 25MHz */ + rk_clrsetreg(&cru->clksel_con[15], + REFCLKO25M_ETH0_OUT_SEL_MASK | REFCLKO25M_ETH0_OUT_DIV_MASK, + REFCLKO25M_ETH0_OUT_SEL_CPLL | REFCLKO25M_ETH0_OUT_DIV(60)); + /* 3. Enable clock */ + rk_clrreg(&cru->clkgate_con[5], REFCLKO25M_ETH0_OUT_EN); +} + +int rockchip_early_misc_init_r(void) +{ + setup_boottargets(); + + setup_eth0refclko(); + + return 0; +} diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig new file mode 100644 index 00000000000..f55bfb1c82b --- /dev/null +++ b/configs/jaguar-rk3588_defconfig @@ -0,0 +1,114 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_ENV_SIZE=0x1f000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-jaguar" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_JAGUAR_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xfeb50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_BOOTMETH_VBE is not set +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-jaguar.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CYCLIC=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SF is not set +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MII is not set +# CONFIG_CMD_BLOCK_CACHE is not set +# CONFIG_CMD_EFICONFIG is not set +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EROFS=y +CONFIG_CMD_SQUASHFS=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +# CONFIG_OF_TAG_MIGRATE is not set +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_SPL_CLK=y +CONFIG_CLK_GPIO=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_SPL_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +# CONFIG_SPI_FLASH is not set +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/index.rst b/doc/board/index.rst index 62357c99388..f0a11f84ccc 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -53,6 +53,7 @@ Board-specific doc ste/index tbs/index thead/index + theobroma-systems/index ti/index toradex/index variscite/index diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index e23ca4231cc..1d5451183be 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -120,6 +120,7 @@ List of mainline supported Rockchip boards: - Turing Machines RK1 (turing-rk1-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) + - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) - Xunlong Orange Pi 5 (orangepi-5-rk3588s) - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) diff --git a/doc/board/theobroma-systems/index.rst b/doc/board/theobroma-systems/index.rst new file mode 100644 index 00000000000..945f7a2f976 --- /dev/null +++ b/doc/board/theobroma-systems/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Theobroma Systems +================= + +.. toctree:: + :maxdepth: 2 + + jaguar_rk3588 diff --git a/doc/board/theobroma-systems/jaguar_rk3588.rst b/doc/board/theobroma-systems/jaguar_rk3588.rst new file mode 100644 index 00000000000..db15f945d3b --- /dev/null +++ b/doc/board/theobroma-systems/jaguar_rk3588.rst @@ -0,0 +1,100 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +SBC-RK3588-AMR Jaguar +===================== + +The SBC-RK3588-AMR is a Single Board Computer designed by +Theobroma Systems for autonomous mobile robots. + +It provides the following features: + + * up to 32GB LDDR4 + * up to 128GB on-module eMMC (with 8-bit 1.8V interface) + * SD card + * Gigabit Ethernet + * 1x USB-A 2.0 host + * PCIe M.2 2230 Key M (Gen 2 1-lane) for WiFi+BT + * PCIe M.2 2280 Key M (Gen 3 4-lane) for NVMe + * CAN + * RS485 UART + * 2x USB Type-C 3.1 host/device + * HDMI output + * 2x camera connectors (MIPI-CSI 2-lane I2C/SPI for IMUs GPIOs) + * EEPROM + * Secure Element + * ATtiny companion controller implementing: + + - low-power RTC functionality (ISL1208 emulation) + - fan controller (AMC6821 emulation) + + * 80-pin Mezzanine connector + +Here is the step-by-step to boot to U-Boot on SBC-RK3588-AMR Jaguar from Theobroma +Systems. + +Get the TF-A and DDR init (TPL) binaries +---------------------------------------- + +.. prompt:: bash + + git clone https://github.com/rockchip-linux/rkbin + cd rkbin + export RKBIN=$(pwd) + export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.38.elf + export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin + sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt + ./tools/ddrbin_tool tools/ddrbin_param.txt "$ROCKCHIP_TPL" + ./tools/boot_merger RKBOOT/RK3588MINIALL.ini + export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin + +This will setup all required external dependencies for compiling U-Boot. This will +be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot +gains support for open-source DRAM initialization in TPL. + +Build U-Boot +------------ + +.. prompt:: bash + + cd ../u-boot + make CROSS_COMPILE=aarch64-linux-gnu- jaguar-rk3588_defconfig all + +This will build ``u-boot-rockchip.bin`` which can be written to an MMC device +(eMMC or SD card). + +Flash the image +--------------- + +Copy ``u-boot-rockchip.bin`` to offset 32k for SD/eMMC. + +SD-Card +~~~~~~~ + +.. prompt:: bash + + dd if=u-boot-rockchip.bin of=/dev/sdX seek=64 + +.. note:: + + Replace ``/dev/sdX`` to match your SD card kernel device. + +eMMC +~~~~ + +``rkdeveloptool`` allows to flash the on-board eMMC via the USB OTG interface +with help of the Rockchip loader binary. + +To enter the USB flashing mode, remove any SD card, insert a USB-C cable in the +``DOWNLOAD`` USB Type-C connector (P11) and then power cycle or reset the board +while pressing the ``BIOS`` (SW2) button. A new USB device should have appeared +on your PC (check with ``lsusb -d 2207:350b``). + +To flash U-Boot on the eMMC with ``rkdeveloptool``: + +.. prompt:: bash + + git clone https://github.com/rockchip-linux/rkdeveloptool + cd rkdeveloptool + autoreconf -i && CPPFLAGS=-Wno-format-truncation ./configure && make + ./rkdeveloptool db "$RKDB" + ./rkdeveloptool wl 64 ../u-boot-rockchip.bin diff --git a/include/configs/jaguar_rk3588.h b/include/configs/jaguar_rk3588.h new file mode 100644 index 00000000000..843028c5385 --- /dev/null +++ b/include/configs/jaguar_rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +#ifndef __JAGUAR_RK3588_H +#define __JAGUAR_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif /* __JAGUAR_RK3588_H */ From fff2b0a9ecc921a6ed9dd5f7c79c449df040ae1d Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:02:00 +0100 Subject: [PATCH 17/91] rockchip: puma-rk3399: MAINTAINERS: use glob for dtses There are multiple Device Trees in U-Boot git repo for Puma, so let's make the MAINTAINERS entry match them all. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- board/theobroma-systems/puma_rk3399/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS b/board/theobroma-systems/puma_rk3399/MAINTAINERS index 93f570fc4f9..23701b3f0ed 100644 --- a/board/theobroma-systems/puma_rk3399/MAINTAINERS +++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS @@ -5,7 +5,7 @@ S: Maintained F: board/theobroma-systems/puma_rk3399 F: board/theobroma-systems/common F: include/configs/puma_rk3399.h -F: arch/arm/dts/rk3399-puma.dts +F: arch/arm/dts/rk3399-puma* F: configs/puma-rk3399_defconfig W: https://www.theobroma-systems.com/rk3399-q7/tech-specs T: git git://git.theobroma-systems.com/puma-u-boot.git From 3308a874dca18b0066a350b4ed986b3f5a5375fa Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:02:01 +0100 Subject: [PATCH 18/91] rockchip: rk3399-puma: migrate README to doc/board in rST format This migrates the plaintext README in board/theobroma-systems/puma_rk3399 to doc/board/theobroma-systems and while doing so, update the instructions and rewrite it in rST. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- .../theobroma-systems/puma_rk3399/MAINTAINERS | 1 + board/theobroma-systems/puma_rk3399/README | 90 +------------ doc/board/theobroma-systems/index.rst | 1 + doc/board/theobroma-systems/puma_rk3399.rst | 126 ++++++++++++++++++ 4 files changed, 129 insertions(+), 89 deletions(-) create mode 100644 doc/board/theobroma-systems/puma_rk3399.rst diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS b/board/theobroma-systems/puma_rk3399/MAINTAINERS index 23701b3f0ed..7e84a5be262 100644 --- a/board/theobroma-systems/puma_rk3399/MAINTAINERS +++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS @@ -4,6 +4,7 @@ M: Klaus Goger S: Maintained F: board/theobroma-systems/puma_rk3399 F: board/theobroma-systems/common +F: doc/board/theobroma-systems F: include/configs/puma_rk3399.h F: arch/arm/dts/rk3399-puma* F: configs/puma-rk3399_defconfig diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README index 649aa3c543d..39c9d618866 100644 --- a/board/theobroma-systems/puma_rk3399/README +++ b/board/theobroma-systems/puma_rk3399/README @@ -1,89 +1 @@ -Introduction -============ - -The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip -RK3399 in a Qseven-compatible form-factor. - -RK3399-Q7 features: - * CPU: ARMv8 64bit Big-Little architecture, - * Big: dual-core Cortex-A72 - * Little: quad-core Cortex-A53 - * IRAM: 200KB - * DRAM: 4GB-128MB dual-channel - * eMMC: onboard eMMC - * SD/MMC - * GbE (onboard Micrel KSZ9031) Gigabit ethernet PHY - * USB: - * USB3.0 dual role port - * 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub - * Display: HDMI/eDP/MIPI - * Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF) - * NOR Flash: onboard SPI NOR - * Companion Controller: onboard additional Cortex-M0 microcontroller - * RTC - * fan controller - * CAN - -Here is the step-by-step to boot to U-Boot on rk3399. - -Get the Source and build ATF binary -=================================== - - > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git - -Compile the ATF -=============== - - > cd trusted-firmware-a - > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 - > cp build/rk3399/release/bl31/bl31.elf ../u-boot/bl31.elf - -Compile the U-Boot -================== - - > cd ../u-boot - > make CROSS_COMPILE=aarch64-linux-gnu- puma-rk3399_defconfig all - -Flash the image -=============== - -Copy u-boot-rockchip.bin to offset 32k for SD/eMMC. -Copy u-boot-rockchip-spi.bin to offset 0 for NOR-flash. - -SD-Card -------- - - > dd if=u-boot-rockchip.bin of=/dev/sdb seek=64 - -eMMC ----- - -rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with -help of the Rockchip loader binary. - - > git clone https://github.com/rockchip-linux/rkdeveloptool - > cd rkdeveloptool - > autoreconf -i && ./configure && make - > git clone https://github.com/rockchip-linux/rkbin.git - > cd rkbin - > ./tools/boot_merger RKBOOT/RK3399MINIALL.ini - > cd .. - > ./rkdeveloptool db rkbin/rk3399_loader_v1.25.126.bin - > ./rkdeveloptool wl 64 ../u-boot-rockchip.bin - -NOR-Flash ---------- - -rkdeveloptool allows to flash the on-board SPI via the USB OTG interface with -help of the Rockchip loader binary. - - > git clone https://github.com/rockchip-linux/rkdeveloptool - > cd rkdeveloptool - > autoreconf -i && ./configure && make - > git clone https://github.com/rockchip-linux/rkbin.git - > cd rkbin - > ./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini - > cd .. - > ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.25.114.bin - > ./rkdeveloptool ef - > ./rkdeveloptool wl 0 ../u-boot-rockchip-spi.bin +See doc/board/theobroma-systems/puma_rk3399.rst. diff --git a/doc/board/theobroma-systems/index.rst b/doc/board/theobroma-systems/index.rst index 945f7a2f976..0720128ad52 100644 --- a/doc/board/theobroma-systems/index.rst +++ b/doc/board/theobroma-systems/index.rst @@ -7,3 +7,4 @@ Theobroma Systems :maxdepth: 2 jaguar_rk3588 + puma_rk3399 diff --git a/doc/board/theobroma-systems/puma_rk3399.rst b/doc/board/theobroma-systems/puma_rk3399.rst new file mode 100644 index 00000000000..5bc6385e451 --- /dev/null +++ b/doc/board/theobroma-systems/puma_rk3399.rst @@ -0,0 +1,126 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +RK3399-Q7 Puma +============== + +The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip +RK3399 in a Qseven-compatible form-factor. + +RK3399-Q7 features: + + * CPU: ARMv8 64bit Big-Little architecture, + + * Big: dual-core Cortex-A72 + * Little: quad-core Cortex-A53 + * IRAM: 200KB + * DRAM: 4GB-128MB dual-channel + + * eMMC: onboard eMMC + * SD/MMC + * GbE (onboard Micrel KSZ9031) Gigabit ethernet PHY + * USB: + + * USB3.0 dual role port + * 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub + + * Display: HDMI/eDP/MIPI + * Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF) + * NOR Flash: onboard SPI NOR + * Companion Controller: onboard additional Cortex-M0 microcontroller + * RTC + * fan controller + * CAN + +Here is the step-by-step to boot to U-Boot on RK3399-Q7 from Theobroma Systems. + +Get the Source and build ATF binary +----------------------------------- + +.. prompt:: bash + + git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + cd trusted-firmware-a + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 + export BL31=$PWD/build/rk3399/release/bl31/bl31.elf + +Compile the U-Boot +------------------ + +.. prompt:: bash + + cd ../u-boot + make CROSS_COMPILE=aarch64-linux-gnu- puma-rk3399_defconfig all + +This will build ``u-boot-rockchip.bin`` which can be written to an MMC device +(eMMC or SD card), and ``u-boot-rockchip-spi.bin`` which can be written to the +SPI-NOR flash. + +Flash the image +--------------- + +Copy ``u-boot-rockchip.bin`` to offset 32k for SD/eMMC. +Copy ``u-boot-rockchip-spi.bin`` to offset 0 for NOR-flash. + +SD-Card +~~~~~~~ + +.. prompt:: bash + + dd if=u-boot-rockchip.bin of=/dev/sdX seek=64 + +.. note:: + + Replace ``/dev/sdX`` to match your SD card kernel device. + +eMMC +~~~~ + +``rkdeveloptool`` allows to flash the on-board eMMC via the USB OTG interface +with help of the Rockchip loader binary. + +To enter the USB flashing mode on Haikou baseboard, remove any SD card, insert a +micro-USB cable in the ``Q7 USB P1`` connector (P8), move ``SW5`` switch into +``BIOS Disable`` mode, power cycle or reset the board and move ``SW5`` switch +back to ``Normal Boot`` mode. A new USB device should have appeared on your PC +(check with ``lsusb -d 2207:330c``). + +To flash U-Boot on the eMMC with ``rkdeveloptool``: + +.. prompt:: bash + + git clone https://github.com/rockchip-linux/rkdeveloptool + cd rkdeveloptool + autoreconf -i && CPPFLAGS=-Wno-format-truncation ./configure && make + git clone https://github.com/rockchip-linux/rkbin.git + cd rkbin + ./tools/boot_merger RKBOOT/RK3399MINIALL.ini + cd .. + ./rkdeveloptool db rkbin/rk3399_loader_v1.30.130.bin + ./rkdeveloptool wl 64 ../u-boot-rockchip.bin + +NOR-Flash +~~~~~~~~~ + +``rkdeveloptool`` allows to flash the on-board SPI via the USB OTG interface with +help of the Rockchip loader binary. + +To enter the USB flashing mode on Haikou baseboard, remove any SD card, insert a +micro-USB cable in the ``Q7 USB P1`` connector (P8), move ``SW5`` switch into +``BIOS Disable`` mode, power cycle or reset the board and move ``SW5`` switch +back to ``Normal Boot`` mode. A new USB device should have appeared on your PC +(check with ``lsusb -d 2207:330c``). + +To flash U-Boot on the SPI with ``rkdeveloptool``: + +.. prompt:: bash + + git clone https://github.com/rockchip-linux/rkdeveloptool + cd rkdeveloptool + autoreconf -i && CPPFLAGS=-Wno-format-truncation ./configure && make + git clone https://github.com/rockchip-linux/rkbin.git + cd rkbin + ./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini + cd .. + ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.30.114.bin + ./rkdeveloptool ef + ./rkdeveloptool wl 0 ../u-boot-rockchip-spi.bin From ed913a71e21a6002656d9e556c35df146e9fc800 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:02:02 +0100 Subject: [PATCH 19/91] rockchip: ringneck_px30: migrate README to doc/board in rST format This migrates the plaintext README in board/theobroma-systems/ringneck_px30 to doc/board/theobroma-systems and while doing so, update the instructions and rewrite it in rST. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- .../ringneck_px30/MAINTAINERS | 1 + board/theobroma-systems/ringneck_px30/README | 70 +------------- doc/board/theobroma-systems/index.rst | 1 + doc/board/theobroma-systems/ringneck_px30.rst | 95 +++++++++++++++++++ 4 files changed, 98 insertions(+), 69 deletions(-) create mode 100644 doc/board/theobroma-systems/ringneck_px30.rst diff --git a/board/theobroma-systems/ringneck_px30/MAINTAINERS b/board/theobroma-systems/ringneck_px30/MAINTAINERS index 06e1beaab14..601830fe45b 100644 --- a/board/theobroma-systems/ringneck_px30/MAINTAINERS +++ b/board/theobroma-systems/ringneck_px30/MAINTAINERS @@ -4,6 +4,7 @@ M: Klaus Goger S: Maintained F: board/theobroma-systems/ringneck_px30 F: board/theobroma-systems/common +F: doc/board/theobroma-systems/ F: include/configs/ringneck_px30.h F: arch/arm/dts/px30-ringneck* F: configs/ringneck-px30_defconfig diff --git a/board/theobroma-systems/ringneck_px30/README b/board/theobroma-systems/ringneck_px30/README index e756b3a8ffc..915baf4a9a0 100644 --- a/board/theobroma-systems/ringneck_px30/README +++ b/board/theobroma-systems/ringneck_px30/README @@ -1,69 +1 @@ -Introduction -============ - -The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, MXM-230 -connector) system-on-module from Theobroma Systems[1], featuring the -Rockchip PX30. - -It provides the following feature set: - * up to 4GB DDR4 - * up to 128GB on-module eMMC (with 8-bit 1.8V interface) - * SD card (on a baseboard) via edge connector - * Fast Ethernet with on-module TI DP83825I PHY - * MIPI-DSI/LVDS - * MIPI-CSI - * USB - - 1x USB 2.0 dual-role - - 3x USB 2.0 host - * on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing: - - low-power RTC functionality (ISL1208 emulation) - - fan controller (AMC6821 emulation) - - USB<->CAN bridge controller (STM32 only) - * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi - * on-module NXP SE05x Secure Element - -Here is the step-by-step to boot to U-Boot on px30. - -Get the Source and build ATF binary -=================================== - - > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git - -Compile the ATF -=============== - - > cd trusted-firmware-a - > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=px30 bl31 - > cp build/px30/release/bl31/bl31.elf ../u-boot/bl31.elf - -Compile the U-Boot -================== - - > cd ../u-boot - > make CROSS_COMPILE=aarch64-linux-gnu- ringneck-px30_defconfig all - -Flash the image -=============== - -Copy u-boot-rockchip.bin to offset 32k for SD/eMMC. - -SD-Card -------- - - > dd if=u-boot-rockchip.bin of=/dev/sdb seek=64 - -eMMC ----- - -rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with -help of the Rockchip loader binary. - - > git clone https://github.com/rockchip-linux/rkdeveloptool - > cd rkdeveloptool - > autoreconf -i && ./configure && make - > git clone https://github.com/rockchip-linux/rkbin.git - > cd rkbin - > ./tools/boot_merger RKBOOT/PX30MINIALL.ini - > cd .. - > ./rkdeveloptool db rkbin/px30_loader_v1.16.131.bin - > ./rkdeveloptool wl 64 ../u-boot-rockchip.bin +See doc/board/theobroma-systems/ringneck_px30.rst. diff --git a/doc/board/theobroma-systems/index.rst b/doc/board/theobroma-systems/index.rst index 0720128ad52..b4da2616c37 100644 --- a/doc/board/theobroma-systems/index.rst +++ b/doc/board/theobroma-systems/index.rst @@ -8,3 +8,4 @@ Theobroma Systems jaguar_rk3588 puma_rk3399 + ringneck_px30 diff --git a/doc/board/theobroma-systems/ringneck_px30.rst b/doc/board/theobroma-systems/ringneck_px30.rst new file mode 100644 index 00000000000..c16b9ed17ed --- /dev/null +++ b/doc/board/theobroma-systems/ringneck_px30.rst @@ -0,0 +1,95 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +PX30-uQ7 Ringneck +================= + +The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, MXM-230 +connector) system-on-module from Theobroma Systems, featuring the Rockchip PX30. + +It provides the following feature set: + + * up to 4GB DDR4 + * up to 128GB on-module eMMC (with 8-bit 1.8V interface) + * SD card (on a baseboard) via edge connector + * Fast Ethernet with on-module TI DP83825I PHY + * MIPI-DSI/LVDS + * MIPI-CSI + * USB + + - 1x USB 2.0 dual-role + - 3x USB 2.0 host + + * on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing: + + - low-power RTC functionality (ISL1208 emulation) + - fan controller (AMC6821 emulation) + - USB<->CAN bridge controller (STM32 only) + + * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi + * on-module NXP SE05x Secure Element + +Here is the step-by-step to boot to U-Boot on PX30-uQ7 Ringneck from Theobroma +Systems. + +Get the Source and build ATF binary +----------------------------------- + +.. prompt:: bash + + git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + cd trusted-firmware-a + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=px30 bl31 + export BL31=$PWD/build/px30/release/bl31/bl31.elf + +Compile the U-Boot +------------------ + +.. prompt:: bash + + cd ../u-boot + make CROSS_COMPILE=aarch64-linux-gnu- ringneck-px30_defconfig all + +This will build ``u-boot-rockchip.bin`` which can be written to an MMC device +(eMMC or SD card). + +Flash the image +--------------- + +Copy ``u-boot-rockchip.bin`` to offset 32k for SD/eMMC. + +SD-Card +~~~~~~~ + +.. prompt:: bash + + dd if=u-boot-rockchip.bin of=/dev/sdX seek=64 + +.. note:: + + Replace ``/dev/sdX`` to match your SD card kernel device. + +eMMC +~~~~ + +``rkdeveloptool`` allows to flash the on-board eMMC via the USB OTG interface +with help of the Rockchip loader binary. + +To enter the USB flashing mode on Haikou baseboard, remove any SD card, insert a +micro-USB cable in the ``Q7 USB P1`` connector (P8), move ``SW5`` switch into +``BIOS Disable`` mode, power cycle or reset the board and move ``SW5`` switch +back to ``Normal Boot`` mode. A new USB device should have appeared on your PC +(check with ``lsusb -d 2207:330d``). + +To flash U-Boot on the eMMC with ``rkdeveloptool``: + +.. prompt:: bash + + git clone https://github.com/rockchip-linux/rkdeveloptool + cd rkdeveloptool + autoreconf -i && CPPFLAGS=-Wno-format-truncation ./configure && make + git clone https://github.com/rockchip-linux/rkbin.git + cd rkbin + ./tools/boot_merger RKBOOT/PX30MINIALL.ini + cd .. + ./rkdeveloptool db rkbin/px30_loader_v2.08.135.bin + ./rkdeveloptool wl 64 ../u-boot-rockchip.bin From 3080945aca15090ccc57f9e7177d59d3b0925d94 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 11 Mar 2024 13:02:03 +0100 Subject: [PATCH 20/91] rockchip: ringneck_px30: update website link The original link returns a custom 404, so let's point to a link that works today instead. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- board/theobroma-systems/ringneck_px30/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/theobroma-systems/ringneck_px30/MAINTAINERS b/board/theobroma-systems/ringneck_px30/MAINTAINERS index 601830fe45b..97baf334d02 100644 --- a/board/theobroma-systems/ringneck_px30/MAINTAINERS +++ b/board/theobroma-systems/ringneck_px30/MAINTAINERS @@ -8,4 +8,4 @@ F: doc/board/theobroma-systems/ F: include/configs/ringneck_px30.h F: arch/arm/dts/px30-ringneck* F: configs/ringneck-px30_defconfig -W: https://www.theobroma-systems.com/px30-uq7#tech-spec +W: https://theobroma-systems.com/product/ringneck-som-px30-uq7/ From d958801dda1f65c40747df5bfae613dae7083b4c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:27 +0000 Subject: [PATCH 21/91] rockchip: rk3328: Update default u-boot, spl-boot-order prop Change to use a common FIT load order, same-as-spl > SD-card > eMMC on RK3328 boards. Only EVB and Radxa ROCK Pi E is affected by this change. Signed-off-by: Jonas Karlman Reviewed-by: Dragan Simic Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi | 6 ------ arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 5 ----- arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 5 ----- arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 5 ----- arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 5 +---- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 5 +---- arch/arm/dts/rk3328-u-boot.dtsi | 2 +- 7 files changed, 3 insertions(+), 30 deletions(-) diff --git a/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi index f8adb9e5e1f..1dc3c022c50 100644 --- a/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi @@ -1,9 +1,3 @@ // SPDX-License-Identifier: GPL-2.0-or-later #include "rk3328-nanopi-r2c-u-boot.dtsi" - -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; -}; diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi index 78d37ab4755..d969b008775 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi @@ -6,11 +6,6 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr4-666.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; -}; &gpio0 { bootph-pre-ram; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi index ebe33e48cb9..5aaa5ccb15c 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi @@ -6,11 +6,6 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-lpddr3-666.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; -}; &gpio0 { bootph-pre-ram; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi index 637c70adf19..6d3db86dce6 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi @@ -6,11 +6,6 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr4-666.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; -}; &gpio0 { bootph-pre-ram; diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi index 2062f34bf82..8bc2f134f8f 100644 --- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -5,11 +5,8 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr4-666.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; +/ { smbios { compatible = "u-boot,sysinfo-smbios"; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 6904515b969..bfe506fd224 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -5,11 +5,8 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-lpddr3-1600.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; +/ { smbios { compatible = "u-boot,sysinfo-smbios"; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index a9f2536de2a..a12be7876db 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -13,7 +13,7 @@ }; chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; }; dmc: dmc { From 93cc018ca86c794e07d1e40fdc8acf50ba03a41a Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:28 +0000 Subject: [PATCH 22/91] rockchip: rk3328-evb: Update defconfig Update defconfig for rk3328-evb with new defaults. Add DM_RESET=y to support using reset signals. Remove the xPL_DRIVERS_MISC=y option, no misc driver is used in xPL. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep support for scripts. Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator commands. Add MISC_INIT_R=y, ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE. Remove pinctrl-0 and pinctrl-names from CONFIG_OF_SPL_REMOVE_PROPS, SPL need to configure pinctrl for e.g. SD-card. Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL. Add DM_ETH_PHY=y, PHY_MOTORCOMM=y and PHY_REALTEK=y to support common ethernet PHYs. Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used. Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random generator. Add SYSINFO=y to support the sysinfo uclass. Also add missing device tree files to MAINTAINERS and remove the obsolete README file. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- board/rockchip/evb_rk3328/MAINTAINERS | 2 + board/rockchip/evb_rk3328/README | 70 --------------------------- configs/evb-rk3328_defconfig | 22 ++++++--- 3 files changed, 18 insertions(+), 76 deletions(-) delete mode 100644 board/rockchip/evb_rk3328/README diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 5fc114a63f6..dc750bd6942 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -4,6 +4,8 @@ S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig +F: arch/arm/dts/rk3328-evb.dts +F: arch/arm/dts/rk3328-evb-u-boot.dtsi NANOPI-R2C-RK3328 M: Tianling Shen diff --git a/board/rockchip/evb_rk3328/README b/board/rockchip/evb_rk3328/README deleted file mode 100644 index 6cbb66a4cf8..00000000000 --- a/board/rockchip/evb_rk3328/README +++ /dev/null @@ -1,70 +0,0 @@ -Introduction -============ - -RK3328 key features we might use in U-Boot: -* CPU: ARMv8 64bit quad-core Cortex-A53 -* IRAM: 36KB -* DRAM: 4GB-16MB dual-channel -* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50 -* SD/MMC: support SD 3.0, MMC 4.51 -* USB: USB2.0 EHCI host port *2 -* Display: RGB/HDMI/DP/MIPI/EDP - -evb key features: -* regulator: pwm regulator for CPU B/L -* PMIC: rk808 -* debug console: UART2 - -In order to support Arm Trust Firmware(ATF), we need to use the -miniloader from rockchip which: -* do DRAM init -* load and verify ATF image -* load and verify U-Boot image - -Here is the step-by-step to boot to U-Boot on rk3328. - -Get the Source and prebuild binary -================================== - - > mkdir ~/evb_rk3328 - > cd ~/evb_rk3328 - > git clone https://github.com/ARM-software/arm-trusted-firmware.git - > git clone https://github.com/rockchip-linux/rkbin - > git clone https://github.com/rockchip-linux/rkflashtool - -Compile ATF -=============== - - > cd arm-trusted-firmware - > make realclean - > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3328 bl31 - -Compile U-Boot -================== - - > cd ../u-boot - > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3328_defconfig all - -Compile rkflashtool -======================= - - > cd ../rkflashtool - > make - -Package image for miniloader -================================ - > cd .. - > cp arm-trusted-firmware/build/rk3328/release/bl31.bin rkbin/rk33 - > ./rkbin/tools/trust_merger rkbin/tools/RK3328TRUST.ini - > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img - > mkdir image - > mv trust.img ./image/ - > mv uboot.img ./image/rk3328evb-uboot.bin - -Flash image -=============== -Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: - - > ./rkflashtool/rkflashloader rk3328evb - -You should be able to get U-Boot log message in console/UART2 now. diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index b9c541a92a1..5a5f59c04b3 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -9,11 +9,11 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x4000000 CONFIG_SPL_STACK=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -25,10 +25,13 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -41,22 +44,23 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y -CONFIG_TPL_DRIVERS_MISC=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -70,8 +74,13 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -79,17 +88,18 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y From 51ee38dd67e217f39f00f6087480f29202e21517 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:29 +0000 Subject: [PATCH 23/91] rockchip: rk3328-rock64: Update defconfig Update defconfig for rk3328-rock64 with new defaults. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep support for scripts. Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is not included in the SPL fdt. Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator commands. Also add CMD_POWEROFF=y to be able to use the poweroff command. Remove the NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from eFUSE. Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL. Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY. Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used. Also add missing device tree file to MAINTAINERS and add myself as a reviewer for this board. Signed-off-by: Jonas Karlman Reviewed-by: Dragan Simic Reviewed-by: Kever Yang --- board/rockchip/evb_rk3328/MAINTAINERS | 2 ++ configs/rock64-rk3328_defconfig | 14 +++++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index dc750bd6942..419bc8ded37 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -47,8 +47,10 @@ F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi ROCK64-RK3328 M: Matwey V. Kornilov +R: Jonas Karlman S: Maintained F: configs/rock64-rk3328_defconfig +F: arch/arm/dts/rk3328-rock64.dts F: arch/arm/dts/rk3328-rock64-u-boot.dtsi ROCKPIE-RK3328 diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 0297d098761..feda8701428 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -39,17 +40,19 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -57,8 +60,8 @@ CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -76,6 +79,9 @@ CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -83,9 +89,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y From c5074c90b0ff800fabaa04c059aedef7c8a59b6a Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:30 +0000 Subject: [PATCH 24/91] rockchip: rk3328-roc-cc: Update defconfig Update defconfig for rk3328-roc-cc with new defaults. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep support for scripts. Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is not included in the SPL fdt. Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator commands. Also add CMD_POWEROFF=y to be able to use the poweroff command. Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE. Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL. Add DM_ETH_PHY=y, PHY_MOTORCOMM=y and PHY_REALTEK=y to support common ethernet PHYs. Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used. Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random generator. Also add missing device tree file to MAINTAINERS and add myself as a reviewer for this board. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- board/rockchip/evb_rk3328/MAINTAINERS | 2 ++ configs/roc-cc-rk3328_defconfig | 15 ++++++++++----- doc/board/rockchip/rockchip.rst | 2 +- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 419bc8ded37..09488eaf083 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -41,8 +41,10 @@ F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi ROC-RK3328-CC M: Loic Devulder M: Chen-Yu Tsai +R: Jonas Karlman S: Maintained F: configs/roc-cc-rk3328_defconfig +F: arch/arm/dts/rk3328-roc-cc.dts F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi ROCK64-RK3328 diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 4ac3c9403b0..c4abc06092f 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -39,18 +40,20 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -58,8 +61,8 @@ CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -73,9 +76,11 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y @@ -84,9 +89,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y @@ -95,6 +98,8 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 1d5451183be..73e15880946 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -60,8 +60,8 @@ List of mainline supported Rockchip boards: - ODROID-GO Advance (odroid-go2) * rk3328 - Rockchip Evb-RK3328 (evb-rk3328) + - Firefly ROC-RK3328-CC (roc-cc-rk3328) - Pine64 Rock64 (rock64-rk3328) - - Firefly-RK3328 (roc-cc-rk3328) - Radxa Rockpi E (rock-pi-e-rk3328) * rk3368 - GeekBox (geekbox) From 1376592f4052290e948644b7d1aaeac61ac3c21e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:31 +0000 Subject: [PATCH 25/91] rockchip: rk3328-rock-pi-e: Update defconfig Update defconfig for rk3328-rock-pi-e with new defaults. Remove the xPL_DRIVERS_MISC=y option, no misc driver is used in xPL. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep support for scripts. Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is not included in the SPL fdt. Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator commands. Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE. Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL. Add DM_MDIO=y to ensure device tree props can be used by PHY driver. Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used. Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random generator. Also add myself as a reviewer for this board. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Reviewed-by: Kever Yang --- board/rockchip/evb_rk3328/MAINTAINERS | 1 + configs/rock-pi-e-rk3328_defconfig | 17 ++++++++++------- doc/board/rockchip/rockchip.rst | 2 +- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 09488eaf083..47fd05d2ea8 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -57,6 +57,7 @@ F: arch/arm/dts/rk3328-rock64-u-boot.dtsi ROCKPIE-RK3328 M: Banglang Huang +R: Jonas Karlman S: Maintained F: configs/rock-pi-e-rk3328_defconfig F: arch/arm/dts/rk3328-rock-pi-e.dts diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 6dda900a9b4..35caad76455 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x4000000 CONFIG_SPL_STACK=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -27,7 +26,9 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -41,17 +42,17 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y -CONFIG_TPL_DRIVERS_MISC=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -59,8 +60,8 @@ CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -74,10 +75,13 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -85,9 +89,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y @@ -95,9 +97,10 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 73e15880946..c8ba8ff0a4a 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -62,7 +62,7 @@ List of mainline supported Rockchip boards: - Rockchip Evb-RK3328 (evb-rk3328) - Firefly ROC-RK3328-CC (roc-cc-rk3328) - Pine64 Rock64 (rock64-rk3328) - - Radxa Rockpi E (rock-pi-e-rk3328) + - Radxa ROCK Pi E (rock-pi-e-rk3328) * rk3368 - GeekBox (geekbox) - PX5 EVB (evb-px5) From 55ecc23cf9229949dcefa717e532fc8ffcec4b17 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:32 +0000 Subject: [PATCH 26/91] rockchip: rk3328-nanopi-r2: Update defconfig Update defconfig for rk3328-nanopi-r2* boards with new defaults. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep support for scripts. Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is not included in the SPL fdt. Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator commands. Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE. Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL. Add DM_ETH_PHY=y, PHY_GIGE=y, PHY_MOTORCOMM=y, PHY_REALTEK=y and remove &gmac2io to support reset of onboard ethernet PHYs. Also add DM_MDIO=y to ensure device tree props is used by motorcomm PHY driver. Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used. Add DM_REGULATOR_GPIO=y and SPL_DM_REGULATOR_GPIO=y to support the regulator-gpio compatible. Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random generator. Also add missing device tree files to MAINTAINERS file. Signed-off-by: Jonas Karlman Reviewed-by: Tianling Shen Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 6 ------ board/rockchip/evb_rk3328/MAINTAINERS | 2 ++ configs/nanopi-r2c-plus-rk3328_defconfig | 20 +++++++++++++++----- configs/nanopi-r2c-rk3328_defconfig | 20 +++++++++++++++----- configs/nanopi-r2s-rk3328_defconfig | 20 +++++++++++++++----- doc/board/rockchip/rockchip.rst | 3 +++ 6 files changed, 50 insertions(+), 21 deletions(-) diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi index d969b008775..0a1152e8b52 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi @@ -27,9 +27,3 @@ &vcc_sd { bootph-pre-ram; }; - -&gmac2io { - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; -}; diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 47fd05d2ea8..b88727acad2 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -11,12 +11,14 @@ NANOPI-R2C-RK3328 M: Tianling Shen S: Maintained F: configs/nanopi-r2c-rk3328_defconfig +F: arch/arm/dts/rk3328-nanopi-r2c.dts F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi NANOPI-R2C-PLUS-RK3328 M: Tianling Shen S: Maintained F: configs/nanopi-r2c-plus-rk3328_defconfig +F: arch/arm/dts/rk3328-nanopi-r2c-plus.dts F: arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi NANOPI-R2S-RK3328 diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig index 320ed8b434a..7a7b0342629 100644 --- a/configs/nanopi-r2c-plus-rk3328_defconfig +++ b/configs/nanopi-r2c-plus-rk3328_defconfig @@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -39,17 +40,18 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -57,8 +59,8 @@ CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -72,8 +74,14 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -81,16 +89,18 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index 583179d7c54..becad021f95 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -39,17 +40,18 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -57,8 +59,8 @@ CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -72,8 +74,14 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -81,16 +89,18 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index f7ed71e4122..fc910b9d03c 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -39,17 +40,18 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -57,8 +59,8 @@ CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -72,8 +74,14 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -81,16 +89,18 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index c8ba8ff0a4a..3f7a5dc99b3 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -61,6 +61,9 @@ List of mainline supported Rockchip boards: * rk3328 - Rockchip Evb-RK3328 (evb-rk3328) - Firefly ROC-RK3328-CC (roc-cc-rk3328) + - FriendlyElec NanoPi R2C (nanopi-r2c-rk3328) + - FriendlyElec NanoPi R2C Plus (nanopi-r2c-plus-rk3328) + - FriendlyElec NanoPi R2S (nanopi-r2s-rk3328) - Pine64 Rock64 (rock64-rk3328) - Radxa ROCK Pi E (rock-pi-e-rk3328) * rk3368 From f652b25feea6cb55548660575e23b1418b7aaa30 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:33 +0000 Subject: [PATCH 27/91] rockchip: rk3328-orangepi-r1-plus: Update defconfig Update defconfig for rk3328-orangepi-r1-plus boards with new defaults. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep support for scripts. Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is not included in the SPL fdt. Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator commands. Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE. Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL. Add DM_ETH_PHY=y, PHY_GIGE=y, PHY_MOTORCOMM=y, PHY_REALTEK=y and remove &gmac2io to support reset of onboard ethernet PHYs. Also add DM_MDIO=y to ensure device tree props is used by motorcomm PHY driver. Add PHY_ROCKCHIP_INNO_USB2=y option to support the onboard USB PHY. Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used. Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random generator. Also add missing device tree files to MAINTAINERS file. Signed-off-by: Jonas Karlman Reviewed-by: Tianling Shen Reviewed-by: Kever Yang --- .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 6 ------ .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 6 ------ board/rockchip/evb_rk3328/MAINTAINERS | 2 ++ configs/orangepi-r1-plus-lts-rk3328_defconfig | 19 ++++++++++++++----- configs/orangepi-r1-plus-rk3328_defconfig | 19 ++++++++++++++----- doc/board/rockchip/rockchip.rst | 2 ++ 6 files changed, 32 insertions(+), 22 deletions(-) diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi index 5aaa5ccb15c..8a4189c6f1c 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi @@ -28,12 +28,6 @@ bootph-pre-ram; }; -&gmac2io { - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; -}; - &spi0 { spi_flash: spiflash@0 { bootph-all; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi index 6d3db86dce6..2e3b6a77a26 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi @@ -28,12 +28,6 @@ bootph-pre-ram; }; -&gmac2io { - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; -}; - &spi0 { spi_flash: spiflash@0 { bootph-all; diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index b88727acad2..675b72dd060 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -32,12 +32,14 @@ ORANGEPI-R1-PLUS-RK3328 M: Tianling Shen S: Maintained F: configs/orangepi-r1-plus-rk3328_defconfig +F: arch/arm/dts/rk3328-orangepi-r1-plus.dts F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi ORANGEPI-R1-PLUS-LTS-RK3328 M: Tianling Shen S: Maintained F: configs/orangepi-r1-plus-lts-rk3328_defconfig +F: arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi ROC-RK3328-CC diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig index d3d9417509e..96d563bb4fc 100644 --- a/configs/orangepi-r1-plus-lts-rk3328_defconfig +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -39,17 +40,18 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -57,8 +59,8 @@ CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -72,18 +74,23 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y @@ -91,6 +98,8 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig index 9356e87132e..dfb05f17655 100644 --- a/configs/orangepi-r1-plus-rk3328_defconfig +++ b/configs/orangepi-r1-plus-rk3328_defconfig @@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -39,17 +40,18 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -57,8 +59,8 @@ CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -72,18 +74,23 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y @@ -91,6 +98,8 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 3f7a5dc99b3..bfe7aede880 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -66,6 +66,8 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPi R2S (nanopi-r2s-rk3328) - Pine64 Rock64 (rock64-rk3328) - Radxa ROCK Pi E (rock-pi-e-rk3328) + - Xunlong Orange Pi R1 Plus (orangepi-r1-plus-rk3328) + - Xunlong Orange Pi R1 Plus LTS (orangepi-r1-plus-lts-rk3328) * rk3368 - GeekBox (geekbox) - PX5 EVB (evb-px5) From 1e21f569304573759b61ca8ee38087c5509ef070 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:34 +0000 Subject: [PATCH 28/91] rockchip: rk3328: Fix loading FIT from SD-card when booting from eMMC When RK3328 boards run SPL from eMMC and fail to load FIT from eMMC due to it being missing or checksum validation fails there is a fallback to read FIT from SD-card. However, without proper pinctrl configuration reading FIT from SD-card will fail: U-Boot SPL 2024.04-rc1 (Feb 05 2024 - 22:18:22 +0000) Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Fix this by tagging related emmc and sdmmc pinctrl nodes with bootph props. Also sort and move common nodes shared by all boards to the SoC u-boot.dtsi. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-evb-u-boot.dtsi | 4 + arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 17 ++- .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 27 ++--- .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 27 ++--- arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 17 --- arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 17 --- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 27 ++--- arch/arm/dts/rk3328-u-boot.dtsi | 101 +++++++++++++++--- 8 files changed, 117 insertions(+), 120 deletions(-) diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 12b68df1ac6..38ad3cc16d0 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -44,3 +44,7 @@ /* Integrated PHY unsupported by U-Boot */ status = "broken"; }; + +&vcc_sd { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi index 0a1152e8b52..cca4f06145c 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi @@ -7,23 +7,18 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr4-666.dtsi" -&gpio0 { +&gpio1 { bootph-pre-ram; }; -&pinctrl { +&sdio_vcc_pin { + bootph-all; +}; + +&vcc_io_sdio { bootph-pre-ram; }; -&sdmmc0m1_pin { - bootph-pre-ram; -}; - -&pcfg_pull_up_4ma { - bootph-pre-ram; -}; - -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi index 8a4189c6f1c..7cdf6913795 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi @@ -7,29 +7,16 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-lpddr3-666.dtsi" -&gpio0 { +&spi0 { bootph-pre-ram; + bootph-some-ram; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; }; -&pinctrl { - bootph-pre-ram; -}; - -&sdmmc0m1_pin { - bootph-pre-ram; -}; - -&pcfg_pull_up_4ma { - bootph-pre-ram; -}; - -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; }; - -&spi0 { - spi_flash: spiflash@0 { - bootph-all; - }; -}; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi index 2e3b6a77a26..35baeb2464b 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi @@ -7,29 +7,16 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr4-666.dtsi" -&gpio0 { +&spi0 { bootph-pre-ram; + bootph-some-ram; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; }; -&pinctrl { - bootph-pre-ram; -}; - -&sdmmc0m1_pin { - bootph-pre-ram; -}; - -&pcfg_pull_up_4ma { - bootph-pre-ram; -}; - -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; }; - -&spi0 { - spi_flash: spiflash@0 { - bootph-all; - }; -}; diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi index 8bc2f134f8f..47d74964fd0 100644 --- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -29,23 +29,6 @@ }; }; -&gpio0 { - bootph-pre-ram; -}; - -&pinctrl { - bootph-pre-ram; -}; - -&sdmmc0m1_pin { - bootph-pre-ram; -}; - -&pcfg_pull_up_4ma { - bootph-pre-ram; -}; - -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi index 1f220c6dcd0..9ed0aef1ecc 100644 --- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi @@ -29,23 +29,6 @@ }; }; -&gpio0 { - bootph-pre-ram; -}; - -&pinctrl { - bootph-pre-ram; -}; - -&sdmmc0m1_pin { - bootph-pre-ram; -}; - -&pcfg_pull_up_4ma { - bootph-pre-ram; -}; - -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index bfe506fd224..9de645d8d7a 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -29,29 +29,16 @@ }; }; -&gpio0 { +&spi0 { bootph-pre-ram; + bootph-some-ram; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; }; -&pinctrl { - bootph-pre-ram; -}; - -&sdmmc0m1_pin { - bootph-pre-ram; -}; - -&pcfg_pull_up_4ma { - bootph-pre-ram; -}; - -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; }; - -&spi0 { - spi_flash: flash@0 { - bootph-all; - }; -}; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index a12be7876db..687c16da513 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -38,33 +38,104 @@ bootph-all; }; +&emmc { + bootph-pre-ram; + bootph-some-ram; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&emmc_bus8 { + bootph-pre-ram; +}; + +&emmc_clk { + bootph-pre-ram; +}; + +&emmc_cmd { + bootph-pre-ram; +}; + +&gpio0 { + bootph-pre-ram; +}; + &grf { bootph-all; }; +&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_none_8ma { + bootph-pre-ram; +}; + +&pcfg_pull_none_12ma { + bootph-pre-ram; +}; + +&pcfg_pull_up { + bootph-all; +}; + +&pcfg_pull_up_4ma { + bootph-pre-ram; +}; + +&pcfg_pull_up_8ma { + bootph-pre-ram; +}; + +&pcfg_pull_up_12ma { + bootph-pre-ram; +}; + +&pinctrl { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc { + bootph-pre-ram; + bootph-some-ram; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&sdmmc0_bus4 { + bootph-pre-ram; +}; + +&sdmmc0_clk { + bootph-pre-ram; +}; + +&sdmmc0_cmd { + bootph-pre-ram; +}; + +&sdmmc0_dectn { + bootph-pre-ram; +}; + +&sdmmc0m1_pin { + bootph-pre-ram; +}; + &uart2 { bootph-all; clock-frequency = <24000000>; }; -&emmc { +&uart2m1_xfer { bootph-all; - - /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ - u-boot,spl-fifo-mode; -}; - -&sdmmc { - bootph-all; - - /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ - u-boot,spl-fifo-mode; }; &usb20_otg { hnp-srp-disable; }; - -&spi0 { - bootph-all; -}; From f41738d0f101fc07c79aea6093650ab2ed4bf8c4 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:35 +0000 Subject: [PATCH 29/91] gpio: rockchip: Use gpio alias id as gpio bank id The U-Boot driver try to base the gpio bank id on the gpio-ranges prop and fall back to base the bank id on the node name. However, the linux driver try to base the bank id on the gpio alias id and fall back on node order. This can cause issues when SoC DT is synced from linux and gpioX@ nodes has been renamed to gpio@ and gpio-ranges or a SoC specific alias has not been assigned. Try to use the gpio alias id as first fallback when a gpio-ranges prop is missing to ease sync of updated SoC DT. Keep the current fallback on node name as a third fallback to not affect any existing unsynced DT. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/gpio/rk_gpio.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index c5e096bb1ad..2e901ac5c73 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -200,8 +200,11 @@ static int rockchip_gpio_probe(struct udevice *dev) priv->bank = args.args[1] / ROCKCHIP_GPIOS_PER_BANK; } else { uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK; - end = strrchr(dev->name, '@'); - priv->bank = trailing_strtoln(dev->name, end); + ret = dev_read_alias_seq(dev, &priv->bank); + if (ret) { + end = strrchr(dev->name, '@'); + priv->bank = trailing_strtoln(dev->name, end); + } } priv->name[0] = 'A' + priv->bank; From 1bc79dce57af1ea5b56d0ea465c3bc596f7a6be1 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:36 +0000 Subject: [PATCH 30/91] rng: rockchip: Use same compatible as linux Replace the rockchip,cryptov1-rng compatible with compatibles used in the linux device tree for RK3288, RK3328 and RK3399 to ease sync of SoC device tree from linux. Signed-off-by: Jonas Karlman Reviewed-by: Heinrich Schuchardt Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-u-boot.dtsi | 2 +- arch/arm/dts/rk3399-u-boot.dtsi | 2 +- drivers/rng/rockchip_rng.c | 10 +++++++++- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index 687c16da513..ea34bf6b78b 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -28,7 +28,7 @@ }; rng: rng@ff060000 { - compatible = "rockchip,cryptov1-rng"; + compatible = "rockchip,rk3328-crypto"; reg = <0x0 0xff060000 0x0 0x4000>; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 3423b882c43..87b173e5957 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -30,7 +30,7 @@ }; rng: rng@ff8b8000 { - compatible = "rockchip,cryptov1-rng"; + compatible = "rockchip,rk3399-crypto"; reg = <0x0 0xff8b8000 0x0 0x1000>; status = "okay"; }; diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c index ce390864262..2426648fbd5 100644 --- a/drivers/rng/rockchip_rng.c +++ b/drivers/rng/rockchip_rng.c @@ -301,7 +301,15 @@ static const struct dm_rng_ops rockchip_rng_ops = { static const struct udevice_id rockchip_rng_match[] = { { - .compatible = "rockchip,cryptov1-rng", + .compatible = "rockchip,rk3288-crypto", + .data = (ulong)&rk_cryptov1_soc_data, + }, + { + .compatible = "rockchip,rk3328-crypto", + .data = (ulong)&rk_cryptov1_soc_data, + }, + { + .compatible = "rockchip,rk3399-crypto", .data = (ulong)&rk_cryptov1_soc_data, }, { From 9b67e6007cc499e96c13dbf5047439ca17ed24b0 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:37 +0000 Subject: [PATCH 31/91] rockchip: rk3328: Sync device tree from linux v6.8-rc1 Sync rk3328 device tree from linux v6.8-rc1. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-evb.dts | 1 + arch/arm/dts/rk3328-nanopi-r2s.dts | 3 +- arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 4 +- arch/arm/dts/rk3328-orangepi-r1-plus.dts | 1 + arch/arm/dts/rk3328-roc-cc.dts | 3 +- arch/arm/dts/rk3328-rock-pi-e.dts | 55 +++++++++++++++++ arch/arm/dts/rk3328-rock64.dts | 1 + arch/arm/dts/rk3328-u-boot.dtsi | 6 -- arch/arm/dts/rk3328.dtsi | 64 +++++++++++++++----- 9 files changed, 112 insertions(+), 26 deletions(-) diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index ff6b466e0e0..1eef5504445 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -11,6 +11,7 @@ compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2phy; mmc0 = &sdmmc; mmc1 = &sdio; mmc2 = &emmc; diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts index 3857d487ab8..a4399da7d8b 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s.dts +++ b/arch/arm/dts/rk3328-nanopi-r2s.dts @@ -14,6 +14,7 @@ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; ethernet1 = &rtl8153; mmc0 = &sdmmc; }; @@ -34,7 +35,7 @@ pinctrl-0 = <&reset_button_pin>; pinctrl-names = "default"; - reset { + key-reset { label = "reset"; gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts index 5d7d567283e..4237f2ee8fe 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts @@ -26,9 +26,11 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + motorcomm,auto-sleep-disabled; motorcomm,clk-out-frequency-hz = <125000000>; motorcomm,keep-pll-enabled; - motorcomm,auto-sleep-disabled; + motorcomm,rx-clk-drv-microamp = <5020>; + motorcomm,rx-data-drv-microamp = <5020>; pinctrl-0 = <ð_phy_reset_pin>; pinctrl-names = "default"; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts b/arch/arm/dts/rk3328-orangepi-r1-plus.dts index dc83d74045a..f20662929c7 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus.dts +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts @@ -15,6 +15,7 @@ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; ethernet1 = &rtl8153; mmc0 = &sdmmc; }; diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts index aa22a0c2226..414897a57e7 100644 --- a/arch/arm/dts/rk3328-roc-cc.dts +++ b/arch/arm/dts/rk3328-roc-cc.dts @@ -11,6 +11,7 @@ compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; mmc0 = &sdmmc; mmc1 = &emmc; }; @@ -96,7 +97,6 @@ linux,default-trigger = "heartbeat"; gpios = <&rk805 1 GPIO_ACTIVE_LOW>; default-state = "on"; - mode = <0x23>; }; user_led: led-1 { @@ -104,7 +104,6 @@ linux,default-trigger = "mmc1"; gpios = <&rk805 0 GPIO_ACTIVE_LOW>; default-state = "off"; - mode = <0x05>; }; }; }; diff --git a/arch/arm/dts/rk3328-rock-pi-e.dts b/arch/arm/dts/rk3328-rock-pi-e.dts index 018a3a5075c..3cda6c627b6 100644 --- a/arch/arm/dts/rk3328-rock-pi-e.dts +++ b/arch/arm/dts/rk3328-rock-pi-e.dts @@ -21,6 +21,8 @@ compatible = "radxa,rockpi-e", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; + ethernet1 = &gmac2phy; mmc0 = &sdmmc; mmc1 = &emmc; }; @@ -180,6 +182,59 @@ status = "okay"; }; +&gpio0 { + gpio-line-names = + /* GPIO0_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_D0 - D7 */ + "", "", "", "pin-15 [GPIO0_D3]", "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_D0 - D7 */ + "", "", "", "", "pin-07 [GPIO1_D4]", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0 - A7 */ + "pin-08 [GPIO2_A0]", "pin-10 [GPIO2_A1]", "pin-11 [GPIO2_A2]", + "pin-13 [GPIO2-A3]", "pin-27 [GPIO2_A4]", "pin-28 [GPIO2_A5]", + "pin-33 [GPIO2_A6]", "", + /* GPIO2_B0 - B7 */ + "", "", "", "", "pin-26 [GPIO2_B4]", "", "", "pin-36 [GPIO2_B7]", + /* GPIO2_C0 - C7 */ + "pin-32 [GPIO2_C0]", "pin-35 [GPIO2_C1]", "pin-12 [GPIO2_C2]", + "pin-38 [GPIO2_C3]", "pin-29 [GPIO2_C4]", "pin-31 [GPIO2_C5]", + "pin-37 [GPIO2_C6]", "pin-40 [GPIO2_C7]", + /* GPIO2_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0 - A7 */ + "pin-23 [GPIO3_A0]", "pin-19 [GPIO3_A1]", "pin-21 [GPIO3_A2]", + "", "pin-03 [GPIO3_A4]", "", "pin-05 [GPIO3_A6]", "", + /* GPIO3_B0 - B7 */ + "pin-24 [GPIO3_B0]", "", "", "", "", "", "", "", + /* GPIO3_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO3_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + &i2c1 { status = "okay"; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index 0a27fa5271f..229fe9da9c2 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -11,6 +11,7 @@ compatible = "pine64,rock64", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; mmc0 = &sdmmc; mmc1 = &emmc; }; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index ea34bf6b78b..a030f1a5e51 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -26,12 +26,6 @@ 0x0 0xff720000 0x0 0x1000 0x0 0xff798000 0x0 0x1000>; }; - - rng: rng@ff060000 { - compatible = "rockchip,rk3328-crypto"; - reg = <0x0 0xff060000 0x0 0x4000>; - status = "okay"; - }; }; &cru { diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index e8d8f00be8a..fe81b97bbe7 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -20,6 +20,10 @@ #size-cells = <2>; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -27,8 +31,6 @@ i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; - ethernet0 = &gmac2io; - ethernet1 = &gmac2phy; }; cpus { @@ -102,10 +104,12 @@ l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; - cpu0_opp_table: opp_table0 { + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -306,6 +310,10 @@ }; power-domain@RK3328_PD_VIDEO { reg = ; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; #power-domain-cells = <0>; }; power-domain@RK3328_PD_VPU { @@ -489,7 +497,7 @@ status = "disabled"; }; - dmac: dmac@ff1f0000 { + dmac: dma-controller@ff1f0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff1f0000 0x0 0x4000>; interrupts = , @@ -599,7 +607,7 @@ gpu: gpu@ff300000 { compatible = "rockchip,rk3328-mali", "arm,mali-450"; - reg = <0x0 0xff300000 0x0 0x40000>; + reg = <0x0 0xff300000 0x0 0x30000>; interrupts = , , , @@ -623,7 +631,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff330200 0 0x100>; interrupts = ; - interrupt-names = "h265e_mmu"; clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -634,7 +641,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff340800 0x0 0x40>; interrupts = ; - interrupt-names = "vepu_mmu"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -656,22 +662,34 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff350800 0x0 0x40>; interrupts = ; - interrupt-names = "vpu_mmu"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk", "iface"; #iommu-cells = <0>; power-domains = <&power RK3328_PD_VPU>; }; - rkvdec_mmu: iommu@ff360480 { + vdec: video-codec@ff360000 { + compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; + reg = <0x0 0xff360000 0x0 0x480>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <400000000>, <400000000>, <300000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3328_PD_VIDEO>; + }; + + vdec_mmu: iommu@ff360480 { compatible = "rockchip,iommu"; reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; interrupts = ; - interrupt-names = "rkvdec_mmu"; clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3328_PD_VIDEO>; }; vop: vop@ff370000 { @@ -700,7 +718,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff373f00 0x0 0x100>; interrupts = ; - interrupt-names = "vop_mmu"; clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -901,6 +918,8 @@ resets = <&cru SRST_GMAC2IO_A>; reset-names = "stmmaceth"; rockchip,grf = <&grf>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; snps,txpbl = <0x4>; status = "disabled"; }; @@ -923,6 +942,8 @@ reset-names = "stmmaceth"; phy-mode = "rmii"; phy-handle = <&phy>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; snps,txpbl = <0x4>; clock_in_out = "output"; status = "disabled"; @@ -1021,6 +1042,17 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + crypto: crypto@ff060000 { + compatible = "rockchip,rk3328-crypto"; + reg = <0x0 0xff060000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, + <&cru SCLK_CRYPTO>; + clock-names = "hclk_master", "hclk_slave", "sclk"; + resets = <&cru SRST_CRYPTO>; + reset-names = "crypto-rst"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3328-pinctrl"; rockchip,grf = <&grf>; @@ -1028,7 +1060,7 @@ #size-cells = <2>; ranges; - gpio0: gpio0@ff210000 { + gpio0: gpio@ff210000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff210000 0x0 0x100>; interrupts = ; @@ -1041,7 +1073,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@ff220000 { + gpio1: gpio@ff220000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff220000 0x0 0x100>; interrupts = ; @@ -1054,7 +1086,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@ff230000 { + gpio2: gpio@ff230000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff230000 0x0 0x100>; interrupts = ; @@ -1067,7 +1099,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@ff240000 { + gpio3: gpio@ff240000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff240000 0x0 0x100>; interrupts = ; From 2f440ffb1d26e07f14e1d0341ceadfa374bdf8e3 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:38 +0000 Subject: [PATCH 32/91] Revert "rockchip: Allow booting from SPI" This reverts commit 3523c07867b403d5b3b68812aebac8a5afa5be4c. Booting from SPI was already allowed before this commit was first introduced. A few lines further down the exact same code already existed and still does. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/spl-boot-order.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 2c39a215c10..79c856d2a0a 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -65,9 +65,6 @@ static int spl_node_to_boot_device(int node) default: return -ENOSYS; } - } else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, - &parent)) { - return BOOT_DEVICE_SPI; } /* From c60b835be28a9d6d7a03a64b42a922c08e62530d Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:39 +0000 Subject: [PATCH 33/91] rockchip: rk3328: Add support to build bootable SPI image Similar to RK35xx the BootRom in RK3328 can read all data and look for idbloader at 0x8000, same as it does for SD and eMMC. Use the rksd format and modify the mkimage offset to generate a bootable u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-u-boot.dtsi | 11 +++++++++++ arch/arm/mach-rockchip/rk3328/rk3328.c | 1 + 2 files changed, 12 insertions(+) diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index a030f1a5e51..4d43fe2fb51 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -133,3 +133,14 @@ &usb20_otg { hnp-srp-disable; }; + +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { + simple-bin-spi { + mkimage { + args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; + offset = <0x8000>; + }; + }; +}; +#endif diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index b8e657e9bf4..ca3fa81e127 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -35,6 +35,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff190000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@ff500000", }; From a37a3ddd515b751e495a488cbbdd4afaf32e7d30 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:40 +0000 Subject: [PATCH 34/91] rockchip: rk3328-rock64: Enable boot from SPI NOR flash Add Kconfig options to enable support for booting from SPI NOR flash on Pine64 Rock64. The generated bootable u-boot-rockchip-spi.bin can be written to 0x0 of SPI NOR flash. The FIT image is loaded from 0x60000, same as on RK35xx boards. => sf probe SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1359872 bytes read in 65 ms (20 MiB/s) => sf update ${fileaddr} 0 ${filesize} device 0 offset 0x0, size 0x14c000 1118208 bytes written, 241664 bytes skipped in 8.516s, speed 163516 B/s Signed-off-by: Jonas Karlman Reviewed-by: Dragan Simic Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 16 ++++++++++++++++ configs/rock64-rk3328_defconfig | 9 +++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 9de645d8d7a..85426495c3d 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -39,6 +39,22 @@ }; }; +&spi0m2_clk { + bootph-pre-ram; +}; + +&spi0m2_cs0 { + bootph-pre-ram; +}; + +&spi0m2_rx { + bootph-pre-ram; +}; + +&spi0m2_tx { + bootph-pre-ram; +}; + &vcc_sd { bootph-pre-ram; }; diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index feda8701428..0c640d7eaad 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x600000 @@ -20,6 +21,8 @@ CONFIG_SPL_STACK=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set @@ -41,6 +44,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y @@ -78,7 +83,11 @@ CONFIG_MISC=y CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y From aa321d49f7d5b9e6dd14cfdc7829d0bf5ea098cc Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 00:22:41 +0000 Subject: [PATCH 35/91] rockchip: rk3328-orangepi-r1-plus: Enable boot from SPI NOR flash Add Kconfig options to enable support for booting from SPI NOR flash on Orange Pi R1 Plus boards. The generated bootable u-boot-rockchip-spi.bin can be written to 0x0 of SPI NOR flash. The FIT image is loaded from 0x60000, same as on RK35xx boards. => sf probe SF: Detected zb25vq128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1376768 bytes read in 66 ms (19.9 MiB/s) => sf update ${fileaddr} 0 ${filesize} device 0 offset 0x0, size 0x150200 1126912 bytes written, 249856 bytes skipped in 14.22s, speed 100542 B/s Signed-off-by: Jonas Karlman Reviewed-by: Tianling Shen Reviewed-by: Kever Yang --- .../dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 16 ++++++++++++++++ configs/orangepi-r1-plus-lts-rk3328_defconfig | 10 ++++++++++ configs/orangepi-r1-plus-rk3328_defconfig | 10 ++++++++++ 4 files changed, 52 insertions(+) diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi index 7cdf6913795..0dbe5a01f98 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi @@ -17,6 +17,22 @@ }; }; +&spi0m2_clk { + bootph-pre-ram; +}; + +&spi0m2_cs0 { + bootph-pre-ram; +}; + +&spi0m2_rx { + bootph-pre-ram; +}; + +&spi0m2_tx { + bootph-pre-ram; +}; + &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi index 35baeb2464b..1af75ada1a6 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi @@ -17,6 +17,22 @@ }; }; +&spi0m2_clk { + bootph-pre-ram; +}; + +&spi0m2_cs0 { + bootph-pre-ram; +}; + +&spi0m2_rx { + bootph-pre-ram; +}; + +&spi0m2_tx { + bootph-pre-ram; +}; + &vcc_sd { bootph-pre-ram; }; diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig index 96d563bb4fc..18dcf6cd4fa 100644 --- a/configs/orangepi-r1-plus-lts-rk3328_defconfig +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x600000 @@ -20,6 +21,8 @@ CONFIG_SPL_STACK=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set @@ -41,6 +44,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y @@ -77,7 +82,12 @@ CONFIG_MISC=y CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_ZBIT=y CONFIG_PHY_MOTORCOMM=y CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig index dfb05f17655..1078f2ff886 100644 --- a/configs/orangepi-r1-plus-rk3328_defconfig +++ b/configs/orangepi-r1-plus-rk3328_defconfig @@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x600000 @@ -20,6 +21,8 @@ CONFIG_SPL_STACK=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set @@ -41,6 +44,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y @@ -77,7 +82,12 @@ CONFIG_MISC=y CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_ZBIT=y CONFIG_PHY_MOTORCOMM=y CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y From 7d4c773e66f37729d8a429fe25678b9a24094b1d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 12 Feb 2024 21:51:04 +0800 Subject: [PATCH 36/91] rockchip: rk3328: Read cpuid and generate MAC address from efuse The rockchip-efuse driver supports the efuse found on RK3328. This hardware block is part of the SoC and contains the CPUID, which can be used to generate stable serial numbers and MAC addresses. Enable the driver and reading cpuid by default for RK3328. Signed-off-by: Chen-Yu Tsai Reviewed-by: Christopher Obbard Reviewed-by: Dragan Simic --- arch/arm/mach-rockchip/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 343361a5327..651e7d7fa62 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -189,6 +189,9 @@ config ROCKCHIP_RK3328 select ENABLE_ARM_SOC_BOOT0_HOOK select DEBUG_UART_BOARD_INIT select SYS_NS16550 + imply MISC + imply ROCKCHIP_EFUSE + imply MISC_INIT_R help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two From 3cd617ff07385a2ca5e482e6003239883686c9ee Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 12 Feb 2024 21:51:05 +0800 Subject: [PATCH 37/91] rockchip: rk3399: Read cpuid and generate MAC address from efuse The rockchip-efuse driver supports the efuse found on RK3399. This hardware block is part of the SoC and contains the CPUID, which can be used to generate stable serial numbers and MAC addresses. Enable the driver and reading cpuid by default for RK3399. Signed-off-by: Chen-Yu Tsai Reviewed-by: Christopher Obbard Reviewed-by: Dragan Simic --- arch/arm/mach-rockchip/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 651e7d7fa62..99e42e5de16 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -270,6 +270,9 @@ config ROCKCHIP_RK3399 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT imply BOOTSTD_FULL imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT + imply MISC + imply ROCKCHIP_EFUSE + imply MISC_INIT_R help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. From 19b4caf32175f227868e9bc3185207f53b9d651f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 12 Feb 2024 21:51:06 +0800 Subject: [PATCH 38/91] rockchip: rk3328: regenerate defconfigs Regenerate RK3328 defconfigs after adding imply statements. Signed-off-by: Chen-Yu Tsai Reviewed-by: Christopher Obbard Reviewed-by: Dragan Simic --- configs/evb-rk3328_defconfig | 3 --- configs/nanopi-r2c-plus-rk3328_defconfig | 3 --- configs/nanopi-r2c-rk3328_defconfig | 3 --- configs/nanopi-r2s-rk3328_defconfig | 3 --- configs/orangepi-r1-plus-lts-rk3328_defconfig | 3 --- configs/orangepi-r1-plus-rk3328_defconfig | 3 --- configs/roc-cc-rk3328_defconfig | 3 --- configs/rock-pi-e-rk3328_defconfig | 3 --- configs/rock64-rk3328_defconfig | 3 --- 9 files changed, 27 deletions(-) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 5a5f59c04b3..da422c8ba4e 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -73,8 +72,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_MOTORCOMM=y diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig index 7a7b0342629..25850328f8b 100644 --- a/configs/nanopi-r2c-plus-rk3328_defconfig +++ b/configs/nanopi-r2c-plus-rk3328_defconfig @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -73,8 +72,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_MOTORCOMM=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index becad021f95..a4cb148246e 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -73,8 +72,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_MOTORCOMM=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index fc910b9d03c..c5d13788528 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -73,8 +72,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_MOTORCOMM=y diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig index 18dcf6cd4fa..6360f5df386 100644 --- a/configs/orangepi-r1-plus-lts-rk3328_defconfig +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -34,7 +34,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -78,8 +77,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig index 1078f2ff886..9473a08fe20 100644 --- a/configs/orangepi-r1-plus-rk3328_defconfig +++ b/configs/orangepi-r1-plus-rk3328_defconfig @@ -34,7 +34,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -78,8 +77,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index c4abc06092f..c66b1ccba26 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -75,8 +74,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_REALTEK=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 35caad76455..275ffc3ed8f 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -32,7 +32,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -74,8 +73,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_REALTEK=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 0c640d7eaad..1cb4e6777d4 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -34,7 +34,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -79,8 +78,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y From 701ed2feb68daa83e25a72dd8d9f65245b2f14bd Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 12 Feb 2024 21:51:07 +0800 Subject: [PATCH 39/91] rockchip: rk3399: regenerate defconfigs Regenerate RK3399 defconfigs after adding imply statements. Signed-off-by: Chen-Yu Tsai Reviewed-by: Christopher Obbard Reviewed-by: Dragan Simic Reviewed-by: Quentin Schulz --- configs/chromebook_bob_defconfig | 3 --- configs/chromebook_kevin_defconfig | 3 --- configs/eaidk-610-rk3399_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/firefly-rk3399_defconfig | 3 --- configs/khadas-edge-captain-rk3399_defconfig | 1 - configs/khadas-edge-rk3399_defconfig | 1 - configs/khadas-edge-v-rk3399_defconfig | 1 - configs/leez-rk3399_defconfig | 1 - configs/nanopc-t4-rk3399_defconfig | 1 - configs/nanopi-m4-2gb-rk3399_defconfig | 1 - configs/nanopi-m4-rk3399_defconfig | 1 - configs/nanopi-m4b-rk3399_defconfig | 1 - configs/nanopi-neo4-rk3399_defconfig | 1 - configs/nanopi-r4s-rk3399_defconfig | 3 --- configs/orangepi-rk3399_defconfig | 1 - configs/pinebook-pro-rk3399_defconfig | 3 --- configs/pinephone-pro-rk3399_defconfig | 3 --- configs/puma-rk3399_defconfig | 3 --- configs/roc-pc-mezzanine-rk3399_defconfig | 3 --- configs/roc-pc-rk3399_defconfig | 3 --- configs/rock-4c-plus-rk3399_defconfig | 3 --- configs/rock-4se-rk3399_defconfig | 3 --- configs/rock-pi-4-rk3399_defconfig | 3 --- configs/rock-pi-4c-rk3399_defconfig | 3 --- configs/rock-pi-n10-rk3399pro_defconfig | 2 -- configs/rock960-rk3399_defconfig | 2 -- configs/rockpro64-rk3399_defconfig | 3 --- 28 files changed, 58 deletions(-) diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index b5a5ae737e5..989a8211f64 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -27,7 +27,6 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_MISC_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 @@ -67,8 +66,6 @@ CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_I2C_MUX=y CONFIG_CROS_EC_KEYB=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 20913d2cf0f..07a96aa1898 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -28,7 +28,6 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_MISC_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 @@ -68,8 +67,6 @@ CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_I2C_MUX=y CONFIG_CROS_EC_KEYB=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index 22ad98b95ad..0ca4cebc4d9 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -40,7 +40,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index d6140527b75..1d1e5516229 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -43,7 +43,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index b7c8e95b7b8..2fe38f81c50 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -20,7 +20,6 @@ CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -45,8 +44,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 7f4e48a4e75..28a59899e1c 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -43,7 +43,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 9de8a53c1ae..075e28a509f 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -42,7 +42,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index f31b8ecf6ee..c65690ce3da 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -43,7 +43,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 76dd91911c7..2122018e7a3 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -39,7 +39,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index c18e7b1bd16..c1617d74011 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -43,7 +43,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index e3bdbccccbe..4d70fde6b14 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -40,7 +40,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index e51e51c8cf5..a96fe0306da 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -40,7 +40,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index ca57c7f81a5..c8faccb233a 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -40,7 +40,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 02e7f4e2ecb..1c4ffbb4404 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -40,7 +40,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index cacaab14d21..f97c06412f0 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -41,8 +40,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_ROCKCHIP_OTP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 27add8a29b9..bc2c4782efb 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -40,7 +40,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index de357415fbe..3083d0a8bb7 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -26,7 +26,6 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -60,8 +59,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_SPL_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index d08224fe536..454cb7eec76 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -25,7 +25,6 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -59,8 +58,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c2aa02ec74b..7e76ec5076f 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -25,7 +25,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -67,8 +66,6 @@ CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index de6539bedf4..8d4153ea5f0 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -26,7 +26,6 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -55,8 +54,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 7123a7a0729..3824eb22d3d 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -27,7 +27,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -55,8 +54,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index 18525c8bf50..67ad54610a7 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -21,7 +21,6 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -52,8 +51,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index 171de23ec8f..b0993bb8102 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -53,8 +52,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 83fc4ad7dab..2df3cd41e16 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -54,8 +53,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 089344097e0..bac745202bc 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -21,7 +21,6 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -52,8 +51,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index dc4b3b40380..e86df4b7456 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -22,7 +22,6 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" # CONFIG_CONSOLE_MUX is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -47,7 +46,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index b93dda56593..a9cae27ccd2 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -20,7 +20,6 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" CONFIG_SYS_PBSIZE=1052 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -50,7 +49,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 711541f8462..b9c885cfee5 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -28,7 +28,6 @@ CONFIG_BOOTSTAGE_REPORT=y CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -63,8 +62,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y From e8fe7c25425f5b95ce518f19a255107e0d4d98f3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 12 Feb 2024 21:51:08 +0800 Subject: [PATCH 40/91] rockchip: nanopi-r4s: Drop ROCKCHIP_OTP The NanoPi R4S has an RK3399 SoC, which has efuse supported by ROCKCHIP_EFUSE, not ROCKCHIP_OTP. Signed-off-by: Chen-Yu Tsai Reviewed-by: Dragan Simic --- configs/nanopi-r4s-rk3399_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index f97c06412f0..50dbd7a854d 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -40,7 +40,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_OTP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y From 341f13e469063d3b8d0316f36c0d4836c74e1ac1 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sat, 17 Feb 2024 19:24:59 +0800 Subject: [PATCH 41/91] board: rockchip: Add support for rk3588s based Cool Pi 4B CoolPi 4B is a rk3588s based SBC. Specification: - Rockchip RK3588S - LPDDR4 2/4/8/16 GB - TF scard slot - eMMC 8/32/64/128 GB module - SPI Nor 8MB - Gigabit ethernet drived by PCIE with RTL8111HS - HDMI Type D out - Mini DP out - USB 2.0 Host x 2 - USB 3.0 OTG x 1 - USB 3.0 Host x 1 - WIFI/BT module AIC8800 - 40 pin header The dts is from linux-6.8 rc1. Signed-off-by: Andy Yan Reviewed-by: Kever Yang [0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/ --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi | 29 + arch/arm/dts/rk3588s-coolpi-4b.dts | 812 +++++++++++++++++++++ board/rockchip/evb_rk3588/MAINTAINERS | 7 + configs/coolpi-4b-rk3588s_defconfig | 113 +++ 5 files changed, 962 insertions(+) create mode 100644 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588s-coolpi-4b.dts create mode 100644 configs/coolpi-4b-rk3588s_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c740c8bc0f5..1c93cad4fb4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -191,6 +191,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ + rk3588s-coolpi-4b.dts \ rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6b-io.dtb \ rk3588-evb1-v10.dtb \ diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi new file mode 100644 index 00000000000..6e4b97028d7 --- /dev/null +++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588s-u-boot.dtsi" + +&fspim2_pins { + bootph-all; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + flash@0 { + bootph-pre-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts b/arch/arm/dts/rk3588s-coolpi-4b.dts new file mode 100644 index 00000000000..e037bf9db75 --- /dev/null +++ b/arch/arm/dts/rk3588s-coolpi-4b.dts @@ -0,0 +1,812 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3588s.dtsi" + +/ { + model = "RK3588S CoolPi 4 Model B"; + compatible = "coolpi,pi-4b", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + analog-sound { + compatible = "audio-graph-card"; + dais = <&i2s0_8ch_p0>; + label = "rk3588-es8316"; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_leds>; + + led0: led-green { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led1: led-red { + color = ; + default-state = "off"; + function = LED_FUNCTION_WLAN; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + avdd0v85_pcie20: avdd0v85-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd0v85_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + avdd1v8_pcie20: avdd1v8-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd1v8_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_mipi: vcc3v3-mipi-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_mipi"; + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_u3host_en>; + regulator-name = "vcc5v0_otg"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + }; +}; + +&i2c7 { + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&rtl8111_isolate>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + led { + gpio_leds: gpio-leds { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>, + <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_u3host_en: vcc5v0-u3host-en { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + bt_reset_gpio: bt-reset-pin { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_irq: bt-wake-host-irq { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_pin: wifi-poweren-pin { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + pinctrl-0 = <&pwm2m1_pins>; + status = "okay"; +}; + +&pwm13 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m2_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-sd; + no-mmc; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>,<&wifi_poweren_pin>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* bt */ +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 2bd44bc5872..1604229759d 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -1,3 +1,10 @@ +COOLPI-4B-RK3588S +M: Andy Yan +S: Maintained +F: configs/coolpi-4b-rk3588s_defconfig +F: arch/arm/dts/rk3588s-coolpi-4b.dts +F: arch/arm/dts/rk3588s-coolpi-u-boot.dtsi + EVB-RK3588 M: Kever Yang S: Maintained diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig new file mode 100644 index 00000000000..0dc5c3c716d --- /dev/null +++ b/configs/coolpi-4b-rk3588s_defconfig @@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_SPL_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y From 3e15dee38d45985b2ad666909720df1b4d412a98 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sat, 17 Feb 2024 19:25:00 +0800 Subject: [PATCH 42/91] board: rockchip: Add support for rk3588 based Cool Pi CM5 EVB Cool Pi CM5 EVB works as a mother board connect with CM5. CM5 Specification: - Rockchip RK3588 - LPDDR4 2/4/8/16 GB - TF scard slot - eMMC 8/32/64/128 GB module - SPI Nor 8MB - Gigabit ethernet x 1 with PHY YT8531 - Gigabit ethernet x 1 drived by PCIE with YT6801S CM5 EVB Specification: - HDMI Type A out x 2 - HDMI Type D in x 1 - USB 2.0 Host x 2 - USB 3.0 OTG x 1 - USB 3.0 Host x 1 - PCIE M.2 E Key for Wireless connection - PCIE M.2 M Key for NVME connection - 40 pin header The dts is from linux-6.8 rc1. Signed-off-by: Andy Yan Reviewed-by: Kever Yang [0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/ --- arch/arm/dts/Makefile | 1 + .../arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi | 29 + arch/arm/dts/rk3588-coolpi-cm5-evb.dts | 216 ++++++ arch/arm/dts/rk3588-coolpi-cm5.dtsi | 649 ++++++++++++++++++ board/rockchip/evb_rk3588/MAINTAINERS | 8 + configs/coolpi-cm5-evb-rk3588_defconfig | 113 +++ 6 files changed, 1016 insertions(+) create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb.dts create mode 100644 arch/arm/dts/rk3588-coolpi-cm5.dtsi create mode 100644 configs/coolpi-cm5-evb-rk3588_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1c93cad4fb4..6e049108112 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -192,6 +192,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588s-coolpi-4b.dts \ + rk3588-coolpi-cm5-evb.dts \ rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6b-io.dtb \ rk3588-evb1-v10.dtb \ diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi new file mode 100644 index 00000000000..ed15b14ea0e --- /dev/null +++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&fspim2_pins { + bootph-all; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + flash@0 { + bootph-pre-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts new file mode 100644 index 00000000000..a4946cdc3bb --- /dev/null +++ b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include "rk3588-coolpi-cm5.dtsi" + +/ { + model = "RK3588 CoolPi CM5 EVB"; + compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588"; + + backlight: backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + power-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 25000 0>; + }; + + leds: leds { + compatible = "gpio-leds"; + + green_led: led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_lcd: vcc3v3-lcd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd"; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcdpwr_en>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_usb_host1: vcc5v0_usb_host2: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +/* M.2 E-Key */ +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq &pcie_wake &pcie_rst &wifi_pwron &bt_pwron>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +/* Standard pcie */ +&pcie3x2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +/* M.2 M-Key ssd */ +&pcie3x4 { + num-lanes = <2>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&pinctrl { + lcd { + lcdpwr_en: lcdpwr-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bl_en: bl-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + bt_pwron: bt-pwron { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_clkreq: pcie-clkreq { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_rst: pcie-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_pwron: wifi-pwron { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_wake: pcie-wake { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_usb_host1>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb_host2>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-coolpi-cm5.dtsi b/arch/arm/dts/rk3588-coolpi-cm5.dtsi new file mode 100644 index 00000000000..9cb6d566da6 --- /dev/null +++ b/arch/arm/dts/rk3588-coolpi-cm5.dtsi @@ -0,0 +1,649 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3588.dtsi" + +/ { + compatible = "coolpi,pi-cm5", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + analog-sound { + compatible = "audio-graph-card"; + dais = <&i2s0_8ch_p0>; + label = "rk3588-es8316"; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + avdd0v85_pcie20: avdd0v85-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd0v85_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + avdd1v8_pcie20: avdd1v8-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd1v8_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + avdd0v75_pcie30: avdd0v75-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd0v75_pcie30"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: avdd1v8-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names = "default"; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c7 { + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* YT8531C/H */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&yt8531_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +/* ethernet */ +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&yt6801_isolate>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + yt6801 { + yt6801_isolate: yt6801-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + yt8531 { + yt8531_rst: yt8531-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_2v0_pldo_s3>; + vcc14-supply = <&vcc_2v0_pldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 1604229759d..8ab58e3ce9d 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -5,6 +5,14 @@ F: configs/coolpi-4b-rk3588s_defconfig F: arch/arm/dts/rk3588s-coolpi-4b.dts F: arch/arm/dts/rk3588s-coolpi-u-boot.dtsi +COOLPI-CM5-EVB-RK3588 +M: Andy Yan +S: Maintained +F: configs/coolpi-cm5-evb-rk3588_defconfig +F: arch/arm/dts/rk3588-coolpi-cm5.dtsi +F: arch/arm/dts/rk3588-coolpi-cm5-evb.dts +F: arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi + EVB-RK3588 M: Kever Yang S: Maintained diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig b/configs/coolpi-cm5-evb-rk3588_defconfig new file mode 100644 index 00000000000..a8d8242f705 --- /dev/null +++ b/configs/coolpi-cm5-evb-rk3588_defconfig @@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_SPL_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y From 6d8cdfd15367b9ed0f8c9458a0f9a9962a767000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 17 Feb 2024 12:34:04 +0000 Subject: [PATCH 43/91] rockchip: spl: Enable caches to speed up checksum validation FIT checksum validation is very slow in SPL due to D-cache not being enabled. Enable caches in SPL on ARM64 SoCs to speed up FIT checksum validation, from seconds to milliseconds. This change enables caches in SPL on all Rockchip ARM64 boards, the Kconfig options SPL_SYS_ICACHE_OFF and SPL_SYS_DCACHE_OFF can be used to disable caches for a specific board or SoC if needed. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/spl.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 87280e2ba7c..1586a093fc3 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -3,7 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include +#include #include #include #include @@ -136,6 +136,20 @@ void board_init_f(ulong dummy) } gd->ram_top = gd->ram_base + get_effective_memsize(); gd->ram_top = board_get_usable_ram_top(gd->ram_size); + + if (IS_ENABLED(CONFIG_ARM64) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + gd->relocaddr = gd->ram_top; + arch_reserve_mmu(); + enable_caches(); + } #endif preloader_console_init(); } + +void spl_board_prepare_for_boot(void) +{ + if (!IS_ENABLED(CONFIG_ARM64) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + + cleanup_before_linux(); +} From 803fbdfd1c0214b694eb489b6dac465b697f0f71 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 25 Feb 2024 22:10:19 +0000 Subject: [PATCH 44/91] phy: rockchip-inno-usb2: Write to correct GRF On RK3399 the USB2PHY regs are located in the common GRF, remaining SoCs that is supported by this driver have the USB2PHY regs in a different GRF. When support for RK356x, RK3588 and RK3328 was added this driver was never updated to use correct GRF and have instead incorrectly written to wrong GRF for these SoCs. The default reset values for the USB2PHY have made USB mostly working even when wrong GRF was used, however, following have been observed: scanning bus usb@fd840000 for devices... ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT) (5) ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT) (5) unable to get device descriptor (error=-1) Fix this by using a regmap from rockchip,usbgrf prop and fall back to getting a regmap for parent udevice instead of always getting the common GRF. Also protect against accidental clear of bit 0 in a reg with offset 0, only bind driver to enabled otg/host-ports and remove unused headers. Fixes: 3da15f0b49a2 ("phy: rockchip-inno-usb2: Add USB2 PHY for rk3568") Fixes: cdf9010f6e17 ("phy: rockchip-inno-usb2: add initial support for rk3588 PHY") Fixes: 9aa93d84038b ("phy: rockchip-inno-usb2: Add USB2 PHY for RK3328") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 41 ++++++++++--------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 70e61eccb79..7317128d135 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -6,23 +6,16 @@ * Copyright (C) 2020 Amarula Solutions(India) */ -#include #include #include -#include #include #include #include #include -#include +#include #include -#include -#include -#include #include -DECLARE_GLOBAL_DATA_PTR; - #define usleep_range(a, b) udelay((b)) #define BIT_WRITEABLE_SHIFT 16 @@ -61,30 +54,39 @@ struct rockchip_usb2phy_cfg { }; struct rockchip_usb2phy { - void *reg_base; + struct regmap *reg_base; struct clk phyclk; const struct rockchip_usb2phy_cfg *phy_cfg; }; -static inline int property_enable(void *reg_base, +static inline int property_enable(struct regmap *base, const struct usb2phy_reg *reg, bool en) { unsigned int val, mask, tmp; + if (!reg->offset && !reg->enable && !reg->disable) + return 0; + tmp = en ? reg->enable : reg->disable; mask = GENMASK(reg->bitend, reg->bitstart); val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); - return writel(val, reg_base + reg->offset); + return regmap_write(base, reg->offset, val); } -static inline bool property_enabled(void *reg_base, +static inline bool property_enabled(struct regmap *base, const struct usb2phy_reg *reg) { + int ret; unsigned int tmp, orig; unsigned int mask = GENMASK(reg->bitend, reg->bitstart); - orig = readl(reg_base + reg->offset); + if (!reg->offset && !reg->enable && !reg->disable) + return false; + + ret = regmap_read(base, reg->offset, &orig); + if (ret) + return false; tmp = (orig & mask) >> reg->bitstart; return tmp != reg->disable; @@ -248,7 +250,11 @@ static int rockchip_usb2phy_probe(struct udevice *dev) unsigned int reg; int index, ret; - priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (dev_read_bool(dev, "rockchip,usbgrf")) + priv->reg_base = + syscon_regmap_lookup_by_phandle(dev, "rockchip,usbgrf"); + else + priv->reg_base = syscon_get_regmap(dev_get_parent(dev)); if (IS_ERR(priv->reg_base)) return PTR_ERR(priv->reg_base); @@ -305,11 +311,8 @@ static int rockchip_usb2phy_bind(struct udevice *dev) int ret = 0; dev_for_each_subnode(node, dev) { - if (!ofnode_valid(node)) { - dev_info(dev, "subnode %s not found\n", dev->name); - ret = -ENXIO; - goto bind_fail; - } + if (!ofnode_is_enabled(node)) + continue; name = ofnode_get_name(node); dev_dbg(dev, "subnode %s\n", name); From b055c8952c0f2cc9063f2c6d33bd1bb6aa83b052 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 25 Feb 2024 22:10:20 +0000 Subject: [PATCH 45/91] phy: rockchip-inno-usb2: Limit changes made to regs The USB2PHY regs already contain working default reset values for RK3328 and RK35xx as evidenced by the fact that this driver never has changed a single value for these SoCs. Reduce to only configure utmi_suspend_n and utmi_sel bits similar to what is currently done on RK3399. Also add missing clkout_ctl for RK3588. When enabled utmi_suspend_n is changed to normal mode and utmi_sel to use otg/host controller utmi interface to phy. When disabled utmi_suspend_n is changed to suspend mode and utmi_sel to use GRF utmi interface to phy. Signed-off-by: Jonas Karlman --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 117 +++--------------- 1 file changed, 14 insertions(+), 103 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 7317128d135..d392aed2d4d 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -35,16 +35,6 @@ struct usb2phy_reg { struct rockchip_usb2phy_port_cfg { struct usb2phy_reg phy_sus; - struct usb2phy_reg bvalid_det_en; - struct usb2phy_reg bvalid_det_st; - struct usb2phy_reg bvalid_det_clr; - struct usb2phy_reg ls_det_en; - struct usb2phy_reg ls_det_st; - struct usb2phy_reg ls_det_clr; - struct usb2phy_reg utmi_avalid; - struct usb2phy_reg utmi_bvalid; - struct usb2phy_reg utmi_ls; - struct usb2phy_reg utmi_hstdet; }; struct rockchip_usb2phy_cfg { @@ -131,7 +121,6 @@ static int rockchip_usb2phy_init(struct phy *phy) { struct udevice *parent = dev_get_parent(phy->dev); struct rockchip_usb2phy *priv = dev_get_priv(parent); - const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy); int ret; ret = clk_enable(&priv->phyclk); @@ -140,14 +129,6 @@ static int rockchip_usb2phy_init(struct phy *phy) return ret; } - if (phy->id == USB2PHY_PORT_OTG) { - property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true); - property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true); - } else if (phy->id == USB2PHY_PORT_HOST) { - property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true); - property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true); - } - return 0; } @@ -351,27 +332,13 @@ bind_fail: static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = { { .reg = 0x100, - .clkout_ctl = { 0x108, 4, 4, 1, 0 }, + .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, .port_cfgs = { [USB2PHY_PORT_OTG] = { - .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 }, - .bvalid_det_en = { 0x0110, 3, 2, 0, 3 }, - .bvalid_det_st = { 0x0114, 3, 2, 0, 3 }, - .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 }, - .ls_det_en = { 0x0110, 0, 0, 0, 1 }, - .ls_det_st = { 0x0114, 0, 0, 0, 1 }, - .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, - .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, - .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, - .utmi_ls = { 0x0120, 5, 4, 0, 1 }, + .phy_sus = { 0x0100, 1, 0, 2, 1 }, }, [USB2PHY_PORT_HOST] = { - .phy_sus = { 0x104, 15, 0, 0, 0x1d1 }, - .ls_det_en = { 0x110, 1, 1, 0, 1 }, - .ls_det_st = { 0x114, 1, 1, 0, 1 }, - .ls_det_clr = { 0x118, 1, 1, 0, 1 }, - .utmi_ls = { 0x120, 17, 16, 0, 1 }, - .utmi_hstdet = { 0x120, 19, 19, 0, 1 } + .phy_sus = { 0x0104, 1, 0, 2, 1 }, } }, }, @@ -385,19 +352,9 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { .port_cfgs = { [USB2PHY_PORT_OTG] = { .phy_sus = { 0xe454, 1, 0, 2, 1 }, - .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, - .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, - .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, - .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, - .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, }, [USB2PHY_PORT_HOST] = { - .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, - .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, - .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, - .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, - .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, - .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } + .phy_sus = { 0xe458, 1, 0, 2, 1 }, } }, }, @@ -407,19 +364,9 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { .port_cfgs = { [USB2PHY_PORT_OTG] = { .phy_sus = { 0xe464, 1, 0, 2, 1 }, - .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, - .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, - .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, - .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, - .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, }, [USB2PHY_PORT_HOST] = { - .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, - .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, - .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, - .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, - .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, - .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } + .phy_sus = { 0xe468, 1, 0, 2, 1 }, } }, }, @@ -432,24 +379,10 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, .port_cfgs = { [USB2PHY_PORT_OTG] = { - .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, - .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, - .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, - .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, - .ls_det_en = { 0x0080, 0, 0, 0, 1 }, - .ls_det_st = { 0x0084, 0, 0, 0, 1 }, - .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, - .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, - .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, - .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, + .phy_sus = { 0x0000, 1, 0, 2, 1 }, }, [USB2PHY_PORT_HOST] = { - .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, - .ls_det_en = { 0x0080, 1, 1, 0, 1 }, - .ls_det_st = { 0x0084, 1, 1, 0, 1 }, - .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, - .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, - .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } + .phy_sus = { 0x0004, 1, 0, 2, 1 }, } }, }, @@ -458,20 +391,10 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, .port_cfgs = { [USB2PHY_PORT_OTG] = { - .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, - .ls_det_en = { 0x0080, 0, 0, 0, 1 }, - .ls_det_st = { 0x0084, 0, 0, 0, 1 }, - .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, - .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, - .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } + .phy_sus = { 0x0000, 1, 0, 2, 1 }, }, [USB2PHY_PORT_HOST] = { - .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, - .ls_det_en = { 0x0080, 1, 1, 0, 1 }, - .ls_det_st = { 0x0084, 1, 1, 0, 1 }, - .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, - .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, - .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } + .phy_sus = { 0x0004, 1, 0, 2, 1 }, } }, }, @@ -481,49 +404,37 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { { .reg = 0x0000, + .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, .port_cfgs = { [USB2PHY_PORT_OTG] = { .phy_sus = { 0x000c, 11, 11, 0, 1 }, - .ls_det_en = { 0x0080, 0, 0, 0, 1 }, - .ls_det_st = { 0x0084, 0, 0, 0, 1 }, - .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, - .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, } }, }, { .reg = 0x4000, + .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, .port_cfgs = { [USB2PHY_PORT_OTG] = { - .phy_sus = { 0x000c, 11, 11, 0, 0 }, - .ls_det_en = { 0x0080, 0, 0, 0, 1 }, - .ls_det_st = { 0x0084, 0, 0, 0, 1 }, - .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, - .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, + .phy_sus = { 0x000c, 11, 11, 0, 1 }, } }, }, { .reg = 0x8000, + .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, .port_cfgs = { [USB2PHY_PORT_HOST] = { .phy_sus = { 0x0008, 2, 2, 0, 1 }, - .ls_det_en = { 0x0080, 0, 0, 0, 1 }, - .ls_det_st = { 0x0084, 0, 0, 0, 1 }, - .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, - .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, } }, }, { .reg = 0xc000, + .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, .port_cfgs = { [USB2PHY_PORT_HOST] = { .phy_sus = { 0x0008, 2, 2, 0, 1 }, - .ls_det_en = { 0x0080, 0, 0, 0, 1 }, - .ls_det_st = { 0x0084, 0, 0, 0, 1 }, - .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, - .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, } }, }, From 9fdd9a546986838caf52d03a0cd21029085ce1b7 Mon Sep 17 00:00:00 2001 From: Elon Zhang Date: Mon, 11 Mar 2024 11:57:33 +0800 Subject: [PATCH 46/91] board: rockchip: add Rockchip Toybrick TB-RK3588X board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TB-RK3588X board is a Rockchip Toybrick RK3588 based development board. Specification: Rockchip Rk3588 SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16GB Memory LPDDR4x Mali G610MC4 GPU 2× MIPI-CSI0 Connector 1x 2Lanes PCIe3.0 Connector 1x SATA3.0 Connector 32GB eMMC Module 2x USB 2.0, 2x USB 3.0 1x HDMI Output, 1x HDMI Input 2x Ethernet Port Functions work normally: [1] USB2.0 Host [2] Ethernet0 with PHY RTL8211F More information can be obtained from the following websites: [1] https://t.rock-chips.com/en/wiki/EN/tb-rk3588x_en/index.html [2] http://t.rock-chips.com/ Kernel commits: 8ffe365f8dc7 ("arm64: dts: rockchip: Add devicetree support for TB-RK3588X board") 7140387ff49d ("dt-bindings: arm: rockchip: Add Toybrick TB-RK3588X") Reviewed-by: Weizhao Ouyang Signed-off-by: Elon Zhang Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi | 12 + arch/arm/dts/rk3588-toybrick-x0.dts | 688 ++++++++++++++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 27 +- board/rockchip/toybrick_rk3588/Kconfig | 12 + board/rockchip/toybrick_rk3588/MAINTAINERS | 8 + board/rockchip/toybrick_rk3588/Makefile | 6 + .../toybrick_rk3588/toybrick-rk3588.c | 39 + configs/toybrick-rk3588_defconfig | 82 +++ doc/board/rockchip/rockchip.rst | 1 + include/configs/toybrick_rk3588.h | 15 + 10 files changed, 889 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588-toybrick-x0.dts create mode 100644 board/rockchip/toybrick_rk3588/Kconfig create mode 100644 board/rockchip/toybrick_rk3588/MAINTAINERS create mode 100644 board/rockchip/toybrick_rk3588/Makefile create mode 100644 board/rockchip/toybrick_rk3588/toybrick-rk3588.c create mode 100644 configs/toybrick-rk3588_defconfig create mode 100644 include/configs/toybrick_rk3588.h diff --git a/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi b/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi new file mode 100644 index 00000000000..1aeb5410e43 --- /dev/null +++ b/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci; + }; +}; diff --git a/arch/arm/dts/rk3588-toybrick-x0.dts b/arch/arm/dts/rk3588-toybrick-x0.dts new file mode 100644 index 00000000000..9090c5c99f2 --- /dev/null +++ b/arch/arm/dts/rk3588-toybrick-x0.dts @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model = "Rockchip Toybrick TB-RK3588X Board"; + compatible = "rockchip,rk3588-toybrick-x0", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-vol-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + button-menu { + label = "Menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + button-escape { + label = "Escape"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 25000 0>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names = "default"; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index c6b79b6cd75..82fde4da454 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -182,6 +182,30 @@ config TARGET_TURINGRK1_RK3588 Gigabit Ethernet Size: 69.6mm x 45mm (260-pin SO-DIMM connector) +config TARGET_TOYBRICK_RK3588 + bool "Toybrick TB-RK3588X board" + select BOARD_LATE_INIT + help + Rockchip Toybrick TB-RK3588X is a Rockchip RK3588 based development board. + TB-RK3588X adopts core board and mainboard design. The core board is connected + with the mainboard through the MXM314Pin standard interface, which can form + a complete industry development board. + + Specifications: + + Rockchip RK3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16GB Memory LPDDR4x + Mali G610MC4 GPU + 2× MIPI-CSI0 Connector + 1x 2Lanes PCIe3.0 Connector + 1x SATA3.0 Connector + 32GB eMMC Module + 2x USB2.0, 2x USB3.0 + 1x HDMI Output, 1x HDMI Input + 2x Ethernet Port + + config ROCKCHIP_BOOT_MODE_REG default 0xfd588080 @@ -198,9 +222,10 @@ source board/edgeble/neural-compute-module-6/Kconfig source board/friendlyelec/nanopc-t6-rk3588/Kconfig source board/pine64/quartzpro64-rk3588/Kconfig source board/turing/turing-rk1-rk3588/Kconfig -source board/rockchip/evb_rk3588/Kconfig source board/radxa/rock5a-rk3588s/Kconfig source board/radxa/rock5b-rk3588/Kconfig +source board/rockchip/evb_rk3588/Kconfig +source board/rockchip/toybrick_rk3588/Kconfig source board/theobroma-systems/jaguar_rk3588/Kconfig endif diff --git a/board/rockchip/toybrick_rk3588/Kconfig b/board/rockchip/toybrick_rk3588/Kconfig new file mode 100644 index 00000000000..8e781a18d9d --- /dev/null +++ b/board/rockchip/toybrick_rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TOYBRICK_RK3588 + +config SYS_BOARD + default "toybrick_rk3588" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "toybrick_rk3588" + +endif diff --git a/board/rockchip/toybrick_rk3588/MAINTAINERS b/board/rockchip/toybrick_rk3588/MAINTAINERS new file mode 100644 index 00000000000..cd4401c24f3 --- /dev/null +++ b/board/rockchip/toybrick_rk3588/MAINTAINERS @@ -0,0 +1,8 @@ +TOYBRICK-RK3588 +M: Elon Zhang +S: Maintained +F: board/rockchip/toybrick_rk3588 +F: include/configs/toybrick_rk3588.h +F: configs/toybrick-rk3588_defconfig +F: arch/arm/dts/rk3588-toybrick-x0.dts +F: arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi diff --git a/board/rockchip/toybrick_rk3588/Makefile b/board/rockchip/toybrick_rk3588/Makefile new file mode 100644 index 00000000000..75d4d9438f7 --- /dev/null +++ b/board/rockchip/toybrick_rk3588/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024 Rockchip Electronics Co,. Ltd. +# + +obj-y += toybrick-rk3588.o diff --git a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c new file mode 100644 index 00000000000..e3217f70b50 --- /dev/null +++ b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Rockchip Electronics Co,. Ltd. + */ + +#include +#include + +#ifdef CONFIG_OF_BOARD_SETUP +static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob) +{ + struct fdt_memory gap1 = { + .start = 0x3fc000000, + .end = 0x3fc4fffff, + }; + struct fdt_memory gap2 = { + .start = 0x3fff00000, + .end = 0x3ffffffff, + }; + unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; + int ret; + + /* + * Inject the reserved-memory nodes into the DTS + */ + ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, + NULL, flags); + if (ret) + return ret; + + return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, + NULL, flags); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return rk3588_add_reserved_memory_fdt_nodes(blob); +} +#endif diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig new file mode 100644 index 00000000000..0b6016955d5 --- /dev/null +++ b/configs/toybrick-rk3588_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_ENV_SIZE=0x1f000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_TOYBRICK_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index bfe7aede880..c35f2560882 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -125,6 +125,7 @@ List of mainline supported Rockchip boards: - Turing Machines RK1 (turing-rk1-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) + - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) - Xunlong Orange Pi 5 (orangepi-5-rk3588s) - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) diff --git a/include/configs/toybrick_rk3588.h b/include/configs/toybrick_rk3588.h new file mode 100644 index 00000000000..faa2e6c19c3 --- /dev/null +++ b/include/configs/toybrick_rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#ifndef __TOYBRICK_RK3588_H +#define __TOYBRICK_RK3588_H + +#include + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif From b54c3d0dd69bd68fafb4481d694615a95a935f47 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 31 Jan 2024 22:08:51 +0000 Subject: [PATCH 47/91] rockchip: board: Add minimal generic RK3588S/RK3588 board Add a minimal generic RK3588S/RK3588 board that only have eMMC and SDMMC enabled. This defconfig can be used to boot from eMMC or SD-card on most RK3588S/RK3588 boards that follow reference board design. Also fix the alphabetical order of RK3588 boards listed in Makefile and documentation. Signed-off-by: Jonas Karlman --- arch/arm/dts/Makefile | 5 +- arch/arm/dts/rk3588-generic-u-boot.dtsi | 3 ++ arch/arm/dts/rk3588-generic.dts | 44 ++++++++++++++++ board/rockchip/evb_rk3588/MAINTAINERS | 7 +++ configs/generic-rk3588_defconfig | 68 +++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 3 +- 6 files changed, 127 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/rk3588-generic-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588-generic.dts create mode 100644 configs/generic-rk3588_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6e049108112..951327b527f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -196,14 +196,15 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6b-io.dtb \ rk3588-evb1-v10.dtb \ + rk3588-generic.dtb \ rk3588-jaguar.dtb \ rk3588-nanopc-t6.dtb \ rk3588s-orangepi-5.dtb \ rk3588-orangepi-5-plus.dtb \ rk3588-quartzpro64.dtb \ - rk3588-turing-rk1.dtb \ rk3588s-rock-5a.dtb \ - rk3588-rock-5b.dtb + rk3588-rock-5b.dtb \ + rk3588-turing-rk1.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi new file mode 100644 index 00000000000..853ed58cfe5 --- /dev/null +++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588s-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts new file mode 100644 index 00000000000..e4721d97a87 --- /dev/null +++ b/arch/arm/dts/rk3588-generic.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3588S/RK3588 with eMMC and SD-card enabled + */ + +/dts-v1/; +#include "rk3588s.dtsi" + +/ { + model = "Generic RK3588S/RK3588"; + compatible = "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 8ab58e3ce9d..a858ab163f3 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -22,6 +22,13 @@ F: configs/evb-rk3588_defconfig F: arch/arm/dts/rk3588-evb1-v10.dts F: arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi +GENERIC-RK3588 +M: Jonas Karlman +S: Maintained +F: configs/generic-rk3588_defconfig +F: arch/arm/dts/rk3588-generic.dts +F: arch/arm/dts/rk3588-generic-u-boot.dtsi + ORANGEPI-5-RK3588 M: Jonas Karlman S: Maintained diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig new file mode 100644 index 00000000000..4755b27c1de --- /dev/null +++ b/configs/generic-rk3588_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-generic" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index c35f2560882..93aceb192f3 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -121,12 +121,13 @@ List of mainline supported Rockchip boards: - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588) + - Generic RK3588S/RK3588 (generic-rk3588) - Pine64 QuartzPro64 (quartzpro64-rk3588) - - Turing Machines RK1 (turing-rk1-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) + - Turing Machines RK1 (turing-rk1-rk3588) - Xunlong Orange Pi 5 (orangepi-5-rk3588s) - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) From c60958d44ef8ca1f7c851103dd4f42a938468076 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 4 Feb 2024 17:30:35 +0000 Subject: [PATCH 48/91] board: rockchip: Add Pine64 PineTab2 The Pine64 PineTab2 is a tablet computer based on the Rockchip RK3566 SoC. The table features 4/8 GB LPDDR4 RAM and 64/128 GB eMMC storage. Features tested on a Pine64 PineTab2 8GB v2.0: - SD-card boot - eMMC boot - SPI Flash boot - USB host Device tree is imported from linux maintainer branch v6.9-armsoc/dts64, commit 1b7e19448f8f ("arm64: dts: rockchip: Add devicetree for Pine64 PineTab2"). Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 2 + arch/arm/dts/rk3566-pinetab2-u-boot.dtsi | 44 + arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi | 3 + arch/arm/dts/rk3566-pinetab2-v0.1.dts | 28 + arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi | 3 + arch/arm/dts/rk3566-pinetab2-v2.0.dts | 48 + arch/arm/dts/rk3566-pinetab2.dtsi | 943 ++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 11 + configs/pinetab2-rk3566_defconfig | 119 +++ doc/board/rockchip/rockchip.rst | 1 + 10 files changed, 1202 insertions(+) create mode 100644 arch/arm/dts/rk3566-pinetab2-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-pinetab2-v0.1.dts create mode 100644 arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-pinetab2-v2.0.dts create mode 100644 arch/arm/dts/rk3566-pinetab2.dtsi create mode 100644 configs/pinetab2-rk3566_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 951327b527f..9f932f986e1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -174,6 +174,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ + rk3566-pinetab2-v0.1.dtb \ + rk3566-pinetab2-v2.0.dtb \ rk3566-quartz64-a.dtb \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ diff --git a/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi new file mode 100644 index 00000000000..4aa6ab1c848 --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +&fspi_dual_io_pins { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; + +&i2c0 { + bootph-pre-ram; +}; + +&rk817 { + bootph-pre-ram; + + regulators { + bootph-pre-ram; + }; +}; + +&sdhci { + cap-mmc-highspeed; +}; + +&sdmmc_pwren_l { + bootph-all; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + + flash@0 { + bootph-pre-ram; + }; +}; + +&vcc3v3_sd { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi new file mode 100644 index 00000000000..061dc3c2c37 --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-pinetab2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-pinetab2-v0.1.dts b/arch/arm/dts/rk3566-pinetab2-v0.1.dts new file mode 100644 index 00000000000..5fe6ca5da9d --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-v0.1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinetab2.dtsi" + +/ { + model = "Pine64 PineTab2 v0.1"; + compatible = "pine64,pinetab2-v0.1", "pine64,pinetab2", "rockchip,rk3566"; +}; + +&lcd { + reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>; +}; + +&pinctrl { + lcd0 { + lcd0_rst_l: lcd0-rst-l { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + vmmc-supply = <&vcc3v3_sys>; +}; diff --git a/arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi new file mode 100644 index 00000000000..061dc3c2c37 --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-pinetab2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-pinetab2-v2.0.dts b/arch/arm/dts/rk3566-pinetab2-v2.0.dts new file mode 100644 index 00000000000..9349541cbbd --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-v2.0.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinetab2.dtsi" + +/ { + model = "Pine64 PineTab2 v2.0"; + compatible = "pine64,pinetab2-v2.0", "pine64,pinetab2", "rockchip,rk3566"; +}; + +&gpio_keys { + pinctrl-0 = <&kb_id_det>, <&hall_int_l>; + + event-hall-sensor { + debounce-interval = <20>; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + label = "Hall Sensor"; + linux,code = ; + linux,input-type = ; + wakeup-event-action = ; + wakeup-source; + }; +}; + +&lcd { + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>; +}; + +&pinctrl { + lcd0 { + lcd0_rst_l: lcd0-rst-l { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hall { + hall_int_l: hall-int-l { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + vmmc-supply = <&vcc_sys>; +}; diff --git a/arch/arm/dts/rk3566-pinetab2.dtsi b/arch/arm/dts/rk3566-pinetab2.dtsi new file mode 100644 index 00000000000..db40281eafb --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2.dtsi @@ -0,0 +1,943 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + chassis-type = "tablet"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <25>; + + button-vol-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = <20 220>; + num-interpolated-steps = <200>; + default-brightness-level = <100>; + power-supply = <&vcc_sys>; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <6000000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4300000>; + voltage-max-design-microvolt = <4350000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4322000 100>, <4250000 95>, <4192000 90>, <4136000 85>, + <4080000 80>, <4022000 75>, <3972000 70>, <3928000 65>, + <3885000 60>, <3833000 55>, <3798000 50>, <3780000 45>, + <3776000 40>, <3773000 35>, <3755000 30>, <3706000 25>, + <3640000 20>, <3589000 15>, <3535000 10>, <3492000 5>, + <3400000 0>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&kb_id_det>; + + tablet-mode-switch { + debounce-interval = <20>; + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + label = "Tablet Mode"; + linux,input-type = ; + linux,code = ; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + led-0 { + compatible = "regulator-led"; + vled-supply = <&vcc5v0_flashled>; + color = ; + function = LED_FUNCTION_FLASH; + }; + + rk817-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_l>; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + + simple-audio-card,routing = + "MICR", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amplifier OUTL", + "Internal Speakers", "Speaker Amplifier OUTR", + "Speaker Amplifier INL", "HPOL", + "Speaker Amplifier INR", "HPOR"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + simple-audio-card,aux-devs = <&speaker_amp>; + simple-audio-card,pin-switches = "Internal Speakers"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + }; + + speaker_amp: speaker-amplifier { + compatible = "simple-audio-amplifier"; + pinctrl-names = "default"; + pinctrl-0 = <&spk_ctl>; + enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + sound-name-prefix = "Speaker Amplifier"; + VCC-supply = <&vcc_bat>; + }; + + vcc_3v3: vcc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_sd: vcc3v3-sd-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren_l>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_flashled: vcc5v0-flashled-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_led_en_h>; + regulator-name = "vcc5v0_flashled"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc5v0_usb_host0: vcc5v0-usb-host0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren1_h>; + regulator-name = "vcc5v0_usb_host0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc5v0_usb_host2: vcc5v0-usb-host2-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren2_h>; + regulator-name = "vcc5v0_usb_host2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc_bat: vcc-bat-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_bat"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_bat>; + }; + + vdd1v2_dvp: vdd1v2-dvp-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd1v2_dvp"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_3v3>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, <200000000>, <500000000>; + assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; +}; + +&csi_dphy { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + clock-master; + #address-cells = <1>; + #size-cells = <0>; + + lcd: panel@0 { + compatible = "boe,th101mb31ig002-28a"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + rotation = <90>; + power-supply = <&vcc_3v3>; + + port@0 { + panel_in_dsi: endpoint@0 { + remote-endpoint = <&dsi0_out_con>; + }; + }; + }; +}; + +&dsi0_in { + dsi0_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi0>; + }; +}; + +&dsi0_out { + dsi0_out_con: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; +}; + +&dsi_dphy0 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_npu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9_p>; + avdd-1v8-supply = <&vcc_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc5v_midu>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdda_0v9_p: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9_p"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_midu: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vbus: OTG_SWITCH { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_l_pmuio2>, <&tp_rst_l_pmuio2>; + AVDD28-supply = <&vcc3v3_pmu>; + VDDIO-supply = <&vcca1v8_pmu>; + irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; + + vcm@c { + compatible = "dongwoon,dw9714"; + reg = <0x0c>; + vcc-supply = <&vcc1v8_dvp>; + }; + + camera@36 { + compatible = "ovti,ov5648"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&camerab_pdn_l &camerab_rst_l>; + + clocks = <&cru CLK_CIF_OUT>; + assigned-clocks = <&cru CLK_CIF_OUT>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&vcc2v8_dvp>; + dvdd-supply = <&vdd1v2_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + powerdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + + port { + endpoint { + data-lanes = <1 2>; + remote-endpoint = <0>; + link-frequencies = /bits/ 64 <210000000 168000000>; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + accelerometer@18 { + compatible = "silan,sc7a20"; + reg = <0x18>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int_l>; + st,drdy-int-pin = <1>; + vdd-supply = <&vcc_1v8>; + vddio-supply = <&vcc_1v8>; + mount-matrix = "1", "0", "0", + "0", "0", "1", + "0", "1", "0"; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&pinctrl { + camerab { + camerab_pdn_l: camerab-pdn-l { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + camerab_rst_l: camerab-rst-l { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cameraf { + cameraf_pdn_l: cameraf-pdn-l { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cameraf_rst_l: cameraf-rst-l { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + flash { + flash_led_en_h: flash-led-en-h { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fspi { + fspi_dual_io_pins: fspi-dual-io-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + gsensor { + gsensor_int_l: gsensor-int-l { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + kb { + kb_id_det: kb-id-det { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_pwren_h: lcd-pwren-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_det_l: hp-det-l { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + spk_ctl: spk-ctl { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tp { + tp_int_l_pmuio2: tp-int-l-pmuio2 { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + tp_rst_l_pmuio2: tp-rst-l-pmuio2 { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usbcc_int_l: usbcc-int-l { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren1_h: usb-host-pwren1-h { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren2_h: usb-host-pwren2-h { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + host_wake_wl: host-wake-wl { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs200-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 + &emmc_clk + &emmc_cmd + &emmc_datastrobe + &emmc_rstnout>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 + &sdmmc0_clk + &sdmmc0_cmd + &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 + &sdmmc1_cmd + &sdmmc1_clk>; + sd-uhs-sdr104; + vqmmc-supply = <&vcca1v8_pmu>; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_dual_io_pins>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host0>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host2>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&vp1 { + vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = ; + remote-endpoint = <&dsi0_in_vp1>; + }; +}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 6b75b35a124..37b8c1eb78b 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -21,3 +21,14 @@ F: arch/arm/dts/rk3566-soquartz-cm4.dts F: arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz-model-a.dts F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi + +PINETAB2-RK3566 +M: Jonas Karlman +S: Maintained +F: configs/pinetab2-rk3566_defconfig +F: arch/arm/dts/rk3566-pinetab2.dtsi +F: arch/arm/dts/rk3566-pinetab2-u-boot.dtsi +F: arch/arm/dts/rk3566-pinetab2-v0.1.dts +F: arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi +F: arch/arm/dts/rk3566-pinetab2-v2.0.dts +F: arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig new file mode 100644 index 00000000000..19b396eef97 --- /dev/null +++ b/configs/pinetab2-rk3566_defconfig @@ -0,0 +1,119 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-pinetab2-v2.0" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-pinetab2-v2.0.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_LIST="rk3566-pinetab2-v0.1 rk3566-pinetab2-v2.0" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y +CONFIG_BUTTON_GPIO=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_PRODUCT_NUM=0x350a +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 93aceb192f3..5dd5ea7f1e2 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -98,6 +98,7 @@ List of mainline supported Rockchip boards: * rk3566 - Anbernic RGxx3 (anbernic-rgxx3-rk3566) + - Pine64 PineTab2 (pinetab2-rk3566) - Pine64 Quartz64-A Board (quartz64-a-rk3566) - Pine64 Quartz64-B Board (quartz64-b-rk3566) - Pine64 SOQuartz on Blade (soquartz-blade-rk3566) From 008ba0d56d002f550570faa76c475290ac72721a Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 2 Mar 2024 19:16:11 +0000 Subject: [PATCH 49/91] rockchip: Add common default bss and stack addresses On Rockchip the typical aarch64 boot steps are as follows: - BROM load TPL to SRAM - TPL init full DRAM - use stack in SRAM at TPL_STACK addr - use malloc heap on stack, size is TPL_SYS_MALLOC_F_LEN - TPL jump back to BROM - BROM load SPL to beginning of DRAM - SPL init storage devices - use bss in DRAM at SPL_BSS_START_ADDR, size is SPL_BSS_MAX_SIZE - use stack in DRAM at SPL_STACK addr (or CUSTOM_SYS_INIT_SP_ADDR) - use malloc heap on stack, size is SPL_SYS_MALLOC_F_LEN - SPL load FIT images from storage to DRAM - use stack in DRAM at SPL_STACK_R_ADDR - use new malloc heap on stack, size is SPL_STACK_R_MALLOC_SIMPLE_LEN - SPL jump to TF-A at 0x40000 - (optional) TF-A load OPTEE - TF-A jump to U-Boot proper at TEXT_BASE - U-Boot proper init pre-reloc devices - use stack in DRAM at CUSTOM_SYS_INIT_SP_ADDR - use malloc heap on stack, size is SYS_MALLOC_F_LEN - U-Boot proper relocate to end of usable DRAM - U-Boot proper init devices and complete boot SPL have access to full DRAM, however, current configuration for text base, stack addr and malloc heap size used at the different boot steps are at risk of overlapping, e.g. when U-Boot proper + FDT grows close to 1 MiB on RK3328/RK3399 or when pre-reloc and reloc stack and malloc heap overlap on ROCK 5A. Fix this by defining safe defaults for bss, stack and malloc size and addresses. A range at around [60 MiB, 64 MiB) was chosen to be used for bss and stack until U-Boot proper have been relocated to end of usable DRAM. The range was primarily chosen to be able to accommodate SoCs with a small amount of embedded DRAM, e.g. RK3308G has 64 MiB DRAM. Overiew of the new common memory layout: [ 0, 2M) - SPL / TF-A / reserved [ 2M, +X) - U-Boot proper pre-reloc [ -X, 64M) - bss, stack and malloc heap During SPL pre-reloc phase: [ 0, 256K) - SPL binary is loaded by BROM to beginning of DRAM [ -X, 63M) - SPL pre-reloc stack [ -32K, 63M) - SPL pre-reloc malloc heap [63.5M, +32K) - SPL bss After SPL reloc phase: [ 0, 256K) - SPL binary [ 256K, +X) - TF-A image is loaded by SPL [ 2M, +X) - U-Boot proper + FDT image is loaded by SPL [ -X, 62M) - SPL reloc stack [ 60M, 62M) - SPL reloc malloc heap [ -32K, 63M) - SPL init malloc heap, memory allocated during SPL pre-reloc phase is still in use at reloc phase [63.5M, +32K) - SPL bss During U-Boot proper pre-reloc phase: [ 0, 2M) - TF-A / reserved [ 2M, +X) - U-Boot proper + FDT [ -X, 63M) - U-Boot proper pre-reloc stack (shared addr with SPL) [ -64K, 63M) - U-Boot proper pre-reloc malloc heap After U-Boot proper has relocated to top of memory we should be able to use 2M+ for loading kernel, initrd, scripts etc. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 55 ++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 99e42e5de16..f68a0a48949 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -558,6 +558,21 @@ config ROCKCHIP_SPI_IMAGE config LNX_KRNL_IMG_TEXT_OFFSET_BASE default TEXT_BASE +config ROCKCHIP_COMMON_STACK_ADDR + bool + depends on SPL_SHARES_INIT_SP_ADDR + select HAS_CUSTOM_SYS_INIT_SP_ADDR + imply SPL_LIBCOMMON_SUPPORT if SPL + imply SPL_LIBGENERIC_SUPPORT if SPL + imply SPL_ROCKCHIP_COMMON_BOARD if SPL + imply SPL_SYS_MALLOC_F if SPL + imply SPL_SYS_MALLOC_SIMPLE if SPL + imply TPL_LIBCOMMON_SUPPORT if TPL + imply TPL_LIBGENERIC_SUPPORT if TPL + imply TPL_ROCKCHIP_COMMON_BOARD if TPL + imply TPL_SYS_MALLOC_F if TPL + imply TPL_SYS_MALLOC_SIMPLE if TPL + source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3066/Kconfig" @@ -573,4 +588,44 @@ source "arch/arm/mach-rockchip/rk3568/Kconfig" source "arch/arm/mach-rockchip/rk3588/Kconfig" source "arch/arm/mach-rockchip/rv1108/Kconfig" source "arch/arm/mach-rockchip/rv1126/Kconfig" + +if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR + +config CUSTOM_SYS_INIT_SP_ADDR + default 0x3f00000 + +config SYS_MALLOC_F_LEN + default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config SPL_SYS_MALLOC_F_LEN + default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config TPL_SYS_MALLOC_F_LEN + default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config TEXT_BASE + default 0x00200000 if ARM64 + +config SPL_TEXT_BASE + default 0x0 if ARM64 + +config SPL_HAS_BSS_LINKER_SECTION + default y if ARM64 + +config SPL_BSS_START_ADDR + default 0x3f80000 + +config SPL_BSS_MAX_SIZE + default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000 + +config SPL_STACK_R + default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config SPL_STACK_R_ADDR + default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config SPL_STACK_R_MALLOC_SIMPLE_LEN + default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000 + +endif endif From 41098d2e3ec168eae94a57c3c17f76ca16033a47 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 2 Mar 2024 19:16:12 +0000 Subject: [PATCH 50/91] rockchip: Use common bss and stack addresses on RK3308 Currently the following memory layout is typically used on RK3308: [ 0, 256K) - SPL binary [ 256K, 2M) - TF-A / reserved [ -X, 4M) - SPL pre-reloc stack (SPL_STACK) [ -8K, 4M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN) [ 4M, +8K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE) [ 6M, +X) - U-Boot proper binary (TEXT_BASE) [ -X, 8M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR) [ -8K, 8M) - pre-reloc malloc heap (SYS_MALLOC_F_LEN) [ -X, 12M) - SPL reloc stack (SPL_STACK_R_ADDR) [ 11M, 12M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN) SPL can safely load U-Boot proper + FDT to [6M, 8M-8K) with this layout. Migrate to use common bss, stack and malloc heap size and addresses to remove this size limitation and extend the malloc heap size being used. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- Kconfig | 2 +- arch/arm/mach-rockchip/rk3308/Kconfig | 7 +++++-- configs/evb-rk3308_defconfig | 13 ------------- configs/roc-cc-rk3308_defconfig | 13 ------------- configs/rock-pi-s-rk3308_defconfig | 13 ------------- 5 files changed, 6 insertions(+), 42 deletions(-) diff --git a/Kconfig b/Kconfig index 5710934000f..75f9563ce6c 100644 --- a/Kconfig +++ b/Kconfig @@ -265,7 +265,7 @@ config SYS_MALLOC_F_LEN hex "Size of malloc() pool before relocation" depends on SYS_MALLOC_F default 0x400 if M68K || PPC || ROCKCHIP_PX30 || ROCKCHIP_RK3036 || \ - ROCKCHIP_RK3308 || ROCKCHIP_RV1108 + ROCKCHIP_RV1108 default 0x600 if ARCH_ZYNQMP_R5 || ARCH_ZYNQMP default 0x800 if ARCH_ZYNQ || ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \ ROCKCHIP_RK322X || X86 diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 194353e4cd9..749e9995d91 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -17,8 +17,11 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3308" -config SYS_MALLOC_F_LEN - default 0x400 +config ROCKCHIP_COMMON_STACK_ADDR + default y + +config TEXT_BASE + default 0x00600000 config SPL_SERIAL default y diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 2729060d6e9..d57b2f6b8e5 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -2,19 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00600000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_EVB_RK3308=y -CONFIG_SPL_STACK_R_ADDR=0xc00000 -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF0C0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -28,11 +20,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 7502da5b1e7..5e8f51ec01e 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -2,19 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00600000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_ROC_RK3308_CC=y -CONFIG_SPL_STACK_R_ADDR=0xc00000 -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF0C0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -28,11 +20,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index 9908a4b4f45..1e9cd2c0fc7 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -2,20 +2,12 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00600000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_EVB_RK3308=y -CONFIG_SPL_STACK_R_ADDR=0xc00000 -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF0A0000 CONFIG_DEBUG_UART_CLOCK=24000000 # CONFIG_DEBUG_UART_BOARD_INIT is not set @@ -29,11 +21,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set From f01a3992035be54ebec950cf4187a052ea0516a1 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 2 Mar 2024 19:16:13 +0000 Subject: [PATCH 51/91] rockchip: Use common bss and stack addresses on RK3328 With the stack and text base used by U-Boot SPL and proper on RK3328 there is a high likelihood of overlapping when U-Boot proper + FDT nears or exceeded 1 MiB in size. Currently the following memory layout is typically used on RK3328: [ 0, 256K) - SPL binary [ 256K, 2M) - TF-A / reserved [ 2M, +X) - U-Boot proper binary (TEXT_BASE) [ -X, 3M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR) [ -8K, 3M) - pre-reloc malloc heap (SYS_MALLOC_F_LEN) [ -X, 4M) - SPL pre-reloc stack (SPL_STACK) [ -8K, 4M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN) [ -X, 6M) - SPL reloc stack (SPL_STACK_R_ADDR) [ 5M, 6M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN) [ 32M, +8K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE) SPL can safely load U-Boot proper + FDT to [2M, 4M-8K) with this layout. However, the stack at [-X, 3M) used during U-Boot proper pre-reloc is restricting the safe size of U-Boot proper + FDT to be less than 1 MiB. Migrate to use common bss, stack and malloc heap size and addresses to fix this restriction and allow for a larger U-Boot proper image size. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3328/Kconfig | 11 ++++------- configs/evb-rk3328_defconfig | 17 ----------------- configs/nanopi-r2c-plus-rk3328_defconfig | 15 --------------- configs/nanopi-r2c-rk3328_defconfig | 15 --------------- configs/nanopi-r2s-rk3328_defconfig | 15 --------------- configs/orangepi-r1-plus-lts-rk3328_defconfig | 15 --------------- configs/orangepi-r1-plus-rk3328_defconfig | 15 --------------- configs/roc-cc-rk3328_defconfig | 15 --------------- configs/rock-pi-e-rk3328_defconfig | 17 ----------------- configs/rock64-rk3328_defconfig | 15 --------------- 10 files changed, 4 insertions(+), 146 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index d5cb649ae6b..70770da5fdf 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -21,13 +21,7 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3328" -config SYS_MALLOC_F_LEN - default 0x2000 - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT +config ROCKCHIP_COMMON_STACK_ADDR default y config TPL_LDSCRIPT @@ -39,6 +33,9 @@ config TPL_TEXT_BASE config TPL_STACK default 0xff098000 +config TPL_SYS_MALLOC_F_LEN + default 0x800 + source "board/rockchip/evb_rk3328/Kconfig" endif diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index da422c8ba4e..4fa8a7d365a 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -2,22 +2,12 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y -CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x4000000 -CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -33,16 +23,9 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2000000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig index 25850328f8b..5302fd91a0f 100644 --- a/configs/nanopi-r2c-plus-rk3328_defconfig +++ b/configs/nanopi-r2c-plus-rk3328_defconfig @@ -2,22 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y -CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -33,16 +24,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2000000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index a4cb148246e..5a722c18263 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -2,22 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y -CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -33,16 +24,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2000000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index c5d13788528..985d02475ec 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -2,22 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y -CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -33,16 +24,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2000000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig index 6360f5df386..e9f7a130692 100644 --- a/configs/orangepi-r1-plus-lts-rk3328_defconfig +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -2,23 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y -CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -36,18 +27,12 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2000000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig index 9473a08fe20..6019f33ae3f 100644 --- a/configs/orangepi-r1-plus-rk3328_defconfig +++ b/configs/orangepi-r1-plus-rk3328_defconfig @@ -2,23 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y -CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -36,18 +27,12 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2000000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index c66b1ccba26..191dbff928b 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -2,22 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y -CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -33,16 +24,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2000000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 275ffc3ed8f..e4f2123e0b1 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -2,23 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y -CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x4000000 -CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -34,17 +24,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2000000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 1cb4e6777d4..f38431891bf 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -2,23 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y -CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -36,18 +27,12 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2000000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y From 5e7cd8a119953dc2f466fea81e230d683ee03493 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 2 Mar 2024 19:16:14 +0000 Subject: [PATCH 52/91] rockchip: Use common bss and stack addresses on RK3399 With the stack and text base used by U-Boot SPL and proper on RK3399 there is a high likelihood of overlapping when U-Boot proper + FDT nears or exceeded 1 MiB in size. Currently the following memory layout is typically used on RK3399: [ 0, 256K) - SPL binary [ 256K, 2M) - TF-A / reserved [ 2M, +X) - U-Boot proper binary (TEXT_BASE) [ -X, 3M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR) [ -16K, 3M) - pre-reloc malloc heap (SYS_MALLOC_F_LEN) [ -X, 4M) - SPL pre-reloc stack (SPL_STACK) [ -16K, 4M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN) [ 4M, +8K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE) [ -X, 64M) - SPL reloc stack (SPL_STACK_R_ADDR) [ 63M, 64M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN) SPL can safely load U-Boot proper + FDT to [2M, 4M-16K) with this layout. However, the stack at [-X, 3M) used during U-Boot proper pre-reloc is restricting the safe size of U-Boot proper + FDT to be less than 1 MiB. Migrate to use common bss, stack and malloc heap size and addresses to fix this restriction and allow for a larger U-Boot proper image size. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3399/Kconfig | 7 +++++-- configs/eaidk-610-rk3399_defconfig | 10 ---------- configs/evb-rk3399_defconfig | 10 ---------- configs/firefly-rk3399_defconfig | 10 ---------- configs/khadas-edge-captain-rk3399_defconfig | 10 ---------- configs/khadas-edge-rk3399_defconfig | 10 ---------- configs/khadas-edge-v-rk3399_defconfig | 10 ---------- configs/leez-rk3399_defconfig | 10 ---------- configs/nanopc-t4-rk3399_defconfig | 10 ---------- configs/nanopi-m4-2gb-rk3399_defconfig | 10 ---------- configs/nanopi-m4-rk3399_defconfig | 10 ---------- configs/nanopi-m4b-rk3399_defconfig | 10 ---------- configs/nanopi-neo4-rk3399_defconfig | 10 ---------- configs/nanopi-r4s-rk3399_defconfig | 10 ---------- configs/orangepi-rk3399_defconfig | 10 ---------- configs/pinebook-pro-rk3399_defconfig | 10 ---------- configs/pinephone-pro-rk3399_defconfig | 10 ---------- configs/roc-pc-mezzanine-rk3399_defconfig | 10 ---------- configs/roc-pc-rk3399_defconfig | 10 ---------- configs/rock-4c-plus-rk3399_defconfig | 10 ---------- configs/rock-4se-rk3399_defconfig | 10 ---------- configs/rock-pi-4-rk3399_defconfig | 10 ---------- configs/rock-pi-4c-rk3399_defconfig | 10 ---------- configs/rock-pi-n10-rk3399pro_defconfig | 10 ---------- configs/rock960-rk3399_defconfig | 10 ---------- configs/rockpro64-rk3399_defconfig | 10 ---------- 26 files changed, 5 insertions(+), 252 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index d01063ac98b..38904291dfa 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -138,8 +138,11 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3399" +config ROCKCHIP_COMMON_STACK_ADDR + default y + config SYS_MALLOC_F_LEN - default 0x4000 + default 0x4000 if !SPL_SHARES_INIT_SP_ADDR config SPL_LIBCOMMON_SUPPORT default y @@ -157,7 +160,7 @@ config TPL_TEXT_BASE default 0xff8c2000 config SPL_STACK_R_ADDR - default 0x04000000 + default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR if BOOTCOUNT_LIMIT diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index 0ca4cebc4d9..4d8b495ccfe 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -2,15 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-eaidk-610" CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -19,13 +15,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-eaidk-610.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 1d1e5516229..d81c7f9604e 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -2,17 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -21,13 +17,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 2fe38f81c50..545c047c6df 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -2,17 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -22,13 +18,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 28a59899e1c..310250ed4a5 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -2,15 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-captain" CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -20,13 +16,7 @@ CONFIG_SYS_PBSIZE=1048 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 075e28a509f..3fe5542d125 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -2,15 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge" CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -20,13 +16,7 @@ CONFIG_SYS_PBSIZE=1048 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index c65690ce3da..4b41454d710 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -2,15 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-v" CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -20,13 +16,7 @@ CONFIG_SYS_PBSIZE=1048 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 2122018e7a3..e5088341389 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -2,15 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-leez-p710" CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -19,12 +15,6 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index c1617d74011..cdfacb66e67 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -2,16 +2,12 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopc-t4" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -21,13 +17,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 4d70fde6b14..51596f57ae3 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -2,15 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb" CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -19,13 +15,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index a96fe0306da..2af84fb6ff1 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -2,15 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4" CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -19,13 +15,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index c8faccb233a..1b76f98e0df 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -2,15 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4b" CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -19,13 +15,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 1c4ffbb4404..c176c5a1211 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -2,15 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4" CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -19,13 +15,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index 50dbd7a854d..ea01d323541 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -2,15 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -19,13 +15,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index bc2c4782efb..c6a92b2decf 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -2,15 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi" CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -19,13 +15,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 3083d0a8bb7..57e614c314e 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -2,10 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 @@ -14,7 +11,6 @@ CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_PINEBOOK_PRO_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -28,13 +24,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index 454cb7eec76..49d3d0456b5 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -2,10 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 @@ -14,7 +11,6 @@ CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_PINEPHONE_PRO_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -27,13 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 8d4153ea5f0..1ff4e15c8c1 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -2,11 +2,8 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 @@ -15,7 +12,6 @@ CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROC_PC_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -28,13 +24,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 3824eb22d3d..a41f71d9e16 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -2,11 +2,8 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 @@ -16,7 +13,6 @@ CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROC_PC_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -29,13 +25,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index 67ad54610a7..1652da5b6ca 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -2,17 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -23,13 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index b0993bb8102..e51a074a297 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -2,17 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -25,13 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 2df3cd41e16..6dc60759005 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -2,17 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -25,13 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index bac745202bc..5c71f0bd9e8 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -2,17 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -23,13 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index e86df4b7456..6889cdcbf7d 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -2,17 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399pro-rock-pi-n10" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -24,13 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index a9cae27ccd2..5c0b95f10bd 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -2,15 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCK960_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -22,13 +18,7 @@ CONFIG_SYS_PBSIZE=1052 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="rock960 => " diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index b9c885cfee5..4de3d5b1c7f 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -2,10 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" @@ -13,7 +10,6 @@ CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPRO64_RK3399=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -30,13 +26,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y From 8a94c376f6cb3fa2efe3077491412ac6749e5585 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 2 Mar 2024 19:16:15 +0000 Subject: [PATCH 53/91] rockchip: Use common bss and stack addresses on RK356x Currently the following memory layout is typically used on RK356x: [ 0, 256K) - SPL binary [ 256K, 2M) - TF-A / reserved [ -X, 4M) - SPL pre-reloc stack (SPL_STACK) [-128K, 4M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN) [ -X, 6M) - SPL reloc stack (SPL_STACK_R_ADDR) [ 5M, 6M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN) [ 10M, +X) - U-Boot proper binary (TEXT_BASE) [ -X, 12M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR) [-128K, 12M) - pre-reloc malloc heap (SYS_MALLOC_F_LEN) [ 64M, +16K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE) SPL can safely load U-Boot proper + FDT to [10M, 12M-128K) with this layout. Migrate to use common bss, stack and malloc heap size and addresses to remove this size limitation. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang (Update for pinetab2-rk3566_defconfig) Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3568/Kconfig | 7 +++++-- configs/anbernic-rgxx3-rk3566_defconfig | 13 ------------- configs/bpi-r2-pro-rk3568_defconfig | 13 ------------- configs/evb-rk3568_defconfig | 13 ------------- configs/generic-rk3568_defconfig | 13 ------------- configs/lubancat-2-rk3568_defconfig | 13 ------------- configs/nanopi-r5c-rk3568_defconfig | 13 ------------- configs/nanopi-r5s-rk3568_defconfig | 13 ------------- configs/odroid-m1-rk3568_defconfig | 13 ------------- configs/pinetab2-rk3566_defconfig | 14 -------------- configs/quartz64-a-rk3566_defconfig | 13 ------------- configs/quartz64-b-rk3566_defconfig | 13 ------------- configs/radxa-cm3-io-rk3566_defconfig | 13 ------------- configs/radxa-e25-rk3568_defconfig | 13 ------------- configs/rock-3a-rk3568_defconfig | 13 ------------- configs/soquartz-blade-rk3566_defconfig | 13 ------------- configs/soquartz-cm4-rk3566_defconfig | 13 ------------- configs/soquartz-model-a-rk3566_defconfig | 13 ------------- 18 files changed, 5 insertions(+), 224 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index baa51349f4b..af537d912a6 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -38,8 +38,11 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3568" -config SYS_MALLOC_F_LEN - default 0x20000 +config ROCKCHIP_COMMON_STACK_ADDR + default y + +config TEXT_BASE + default 0x00a00000 source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig index ed6643d9d4f..2b484fcaef5 100644 --- a/configs/anbernic-rgxx3-rk3566_defconfig +++ b/configs/anbernic-rgxx3-rk3566_defconfig @@ -2,22 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_ANBERNIC_RGXX3_RK3566=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -34,13 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_RNG_SEED=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_PWM=y CONFIG_CMD_GPT=y diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig index e6e0e6fc6fa..5cc95241ba4 100644 --- a/configs/bpi-r2-pro-rk3568_defconfig +++ b/configs/bpi-r2-pro-rk3568_defconfig @@ -2,18 +2,10 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -30,12 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="BPI-R2PRO> " CONFIG_CMD_GPIO=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index cb9b87ff12c..6e8061f5f48 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -2,18 +2,10 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -28,12 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig index 8fb79c9b440..e7d5e55bbfd 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -2,18 +2,10 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -28,12 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig index 80ae6ec3a2e..1c50a0ccbe6 100644 --- a/configs/lubancat-2-rk3568_defconfig +++ b/configs/lubancat-2-rk3568_defconfig @@ -2,18 +2,10 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -28,12 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig index f5a472d03d7..0f1a9461a0c 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -3,18 +3,10 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -30,12 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 99692d341f4..4ebf0cc9ee8 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -3,18 +3,10 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -30,12 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig index 3130e341e77..b5ed9e4bc98 100644 --- a/configs/odroid-m1-rk3568_defconfig +++ b/configs/odroid-m1-rk3568_defconfig @@ -2,22 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_ODROID_M1_RK3568=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -36,12 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-odroid-m1.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SPL_ATF=y diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig index 19b396eef97..bc7a77aa52f 100644 --- a/configs/pinetab2-rk3566_defconfig +++ b/configs/pinetab2-rk3566_defconfig @@ -2,24 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="rk3566-pinetab2-v2.0" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_QUARTZ64_RK3566=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -36,12 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-pinetab2-v2.0.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig index ade08867f60..fef80439d89 100644 --- a/configs/quartz64-a-rk3566_defconfig +++ b/configs/quartz64-a-rk3566_defconfig @@ -2,23 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_QUARTZ64_RK3566=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -37,12 +29,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig index 8d01db54407..bb541ed1af6 100644 --- a/configs/quartz64-b-rk3566_defconfig +++ b/configs/quartz64-b-rk3566_defconfig @@ -2,22 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-b" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_QUARTZ64_RK3566=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -36,12 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-b.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig index 4b606dcb8e9..bf61db44d3a 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -2,18 +2,10 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -28,12 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig index fedb137877a..43aa8ec20e4 100644 --- a/configs/radxa-e25-rk3568_defconfig +++ b/configs/radxa-e25-rk3568_defconfig @@ -3,18 +3,10 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -31,12 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index 18372a570eb..c161bc974fb 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -2,21 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -35,12 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig index 9693cc2f9eb..b9ac6b9f33d 100644 --- a/configs/soquartz-blade-rk3566_defconfig +++ b/configs/soquartz-blade-rk3566_defconfig @@ -2,19 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_QUARTZ64_RK3566=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -31,12 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-blade.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig index 9c6b12d2302..e87a6392c52 100644 --- a/configs/soquartz-cm4-rk3566_defconfig +++ b/configs/soquartz-cm4-rk3566_defconfig @@ -2,19 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-cm4" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_QUARTZ64_RK3566=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -31,12 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-cm4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig index fd72d78a47a..b2c1684515e 100644 --- a/configs/soquartz-model-a-rk3566_defconfig +++ b/configs/soquartz-model-a-rk3566_defconfig @@ -2,19 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-model-a" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_QUARTZ64_RK3566=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -31,12 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-model-a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y From b0cadb35da6a69e02f51ceb46d60d643e353986a Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 2 Mar 2024 19:16:16 +0000 Subject: [PATCH 54/91] rockchip: Use common bss and stack addresses on RK3588 Currently the following memory layout is typically used on RK3588: [ 0, 256K) - SPL binary [ 256K, 2M) - TF-A / reserved [ -X, 4M) - SPL pre-reloc stack (SPL_STACK) [ 3.5M, 4M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN) [ -X, 6M) - SPL reloc stack (SPL_STACK_R_ADDR) [ 5M, 6M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN) [ 10M, +X) - U-Boot proper binary (TEXT_BASE) [ -X, 12M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR) [11.5M, 12M) - pre-reloc malloc heap (SYS_MALLOC_F_LEN) [ 64M, +16K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE) SPL can safely load U-Boot proper + FDT to [10M, 11.5M) with this layout. However, on ROCK 5A the SPL stacks is overlapping: [ -X, 16M) - SPL pre-reloc stack (SPL_STACK) [15.5M, 16M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN) [ -X, 16M) - SPL reloc stack (SPL_STACK_R_ADDR) [ 15M, 16M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN) Because bind and probe udevice instanses is allocated on the pre-reloc malloc heap, there is going to be an overlap when reloc malloc heap reaches close to 512 KiB of usage. Migrate to use common bss, stack and malloc heap size and addresses to mitigate these limitations and allow for a larger U-Boot proper size. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang (Update for new boards defconfig) Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3588/Kconfig | 7 +++++-- configs/coolpi-4b-rk3588s_defconfig | 13 ------------- configs/coolpi-cm5-evb-rk3588_defconfig | 13 ------------- configs/evb-rk3588_defconfig | 13 ------------- configs/generic-rk3588_defconfig | 15 --------------- configs/jaguar-rk3588_defconfig | 13 ------------- configs/nanopc-t6-rk3588_defconfig | 13 ------------- configs/neu6a-io-rk3588_defconfig | 13 ------------- configs/neu6b-io-rk3588_defconfig | 13 ------------- configs/orangepi-5-plus-rk3588_defconfig | 13 ------------- configs/orangepi-5-rk3588s_defconfig | 13 ------------- configs/quartzpro64-rk3588_defconfig | 13 ------------- configs/rock5a-rk3588s_defconfig | 13 ------------- configs/rock5b-rk3588_defconfig | 13 ------------- configs/toybrick-rk3588_defconfig | 14 -------------- configs/turing-rk1-rk3588_defconfig | 13 ------------- 16 files changed, 5 insertions(+), 200 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 82fde4da454..d7e4af31f24 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -215,8 +215,11 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3588" -config SYS_MALLOC_F_LEN - default 0x80000 +config ROCKCHIP_COMMON_STACK_ADDR + default y + +config TEXT_BASE + default 0x00a00000 source board/edgeble/neural-compute-module-6/Kconfig source board/friendlyelec/nanopc-t6-rk3588/Kconfig diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig index 0dc5c3c716d..a0fe3708344 100644 --- a/configs/coolpi-4b-rk3588s_defconfig +++ b/configs/coolpi-4b-rk3588s_defconfig @@ -2,22 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3588=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -37,12 +29,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig b/configs/coolpi-cm5-evb-rk3588_defconfig index a8d8242f705..fc17660da2a 100644 --- a/configs/coolpi-cm5-evb-rk3588_defconfig +++ b/configs/coolpi-cm5-evb-rk3588_defconfig @@ -2,22 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3588=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -37,12 +29,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig index 8a6aa91cb29..c8db04c076e 100644 --- a/configs/evb-rk3588_defconfig +++ b/configs/evb-rk3588_defconfig @@ -2,19 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3588=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -30,12 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig index 4755b27c1de..b50f4f8b800 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -2,19 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-generic" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3588=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -30,12 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -52,8 +39,6 @@ CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index f55bfb1c82b..92800dc31e5 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -2,23 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_ENV_SIZE=0x1f000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-jaguar" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_JAGUAR_RK3588=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xfeb50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -35,12 +27,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CYCLIC=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig index 76099322092..5c7bc0b7196 100644 --- a/configs/nanopc-t6-rk3588_defconfig +++ b/configs/nanopc-t6-rk3588_defconfig @@ -3,22 +3,14 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_NANOPCT6_RK3588=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -37,12 +29,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig index d5301c630b2..307a540f424 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -2,19 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_RK3588_NEU6=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -27,12 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6a-io.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig index b13c9b5db1b..9ef2bb21fff 100644 --- a/configs/neu6b-io-rk3588_defconfig +++ b/configs/neu6b-io-rk3588_defconfig @@ -2,19 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_RK3588_NEU6=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -27,12 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6b-io.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig index a58f96d5779..d6e23c154f1 100644 --- a/configs/orangepi-5-plus-rk3588_defconfig +++ b/configs/orangepi-5-plus-rk3588_defconfig @@ -3,22 +3,14 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-orangepi-5-plus" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3588=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -38,12 +30,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-plus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig index a9404c912ea..e6b3da1dc59 100644 --- a/configs/orangepi-5-rk3588s_defconfig +++ b/configs/orangepi-5-rk3588s_defconfig @@ -2,22 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588s-orangepi-5" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3588=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -37,12 +29,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-orangepi-5.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig index 9cc4eb02e08..b2a66d3f2db 100644 --- a/configs/quartzpro64-rk3588_defconfig +++ b/configs/quartzpro64-rk3588_defconfig @@ -3,19 +3,11 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_QUARTZPRO64_RK3588=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -33,12 +25,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig index efa7bcbdcda..ebe2d4a2d81 100644 --- a/configs/rock5a-rk3588s_defconfig +++ b/configs/rock5a-rk3588s_defconfig @@ -2,19 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x1000000 CONFIG_TARGET_ROCK5A_RK3588=y -CONFIG_SPL_STACK=0x1000000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -30,12 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index a0678ff1290..58c7c44fb4f 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -3,22 +3,14 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_ROCK5B_RK3588=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -38,12 +30,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig index 0b6016955d5..6ee92e94313 100644 --- a/configs/toybrick-rk3588_defconfig +++ b/configs/toybrick-rk3588_defconfig @@ -2,20 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -CONFIG_ENV_SIZE=0x1f000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_TOYBRICK_RK3588=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -31,12 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig index 0f903cf6e8b..07f7b848529 100644 --- a/configs/turing-rk1-rk3588_defconfig +++ b/configs/turing-rk1-rk3588_defconfig @@ -3,22 +3,14 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_TURINGRK1_RK3588=y -CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEBC0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -38,12 +30,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y From 8c19275fdb13cdc1b8719436fa9477c294996fab Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 10 Mar 2024 18:50:57 +0000 Subject: [PATCH 55/91] rockchip: Update the default USB Product ID value RK3036 is using the USB product id normally used by RK3066B, and RK3328 is using the product id normally used by RK3368. Fix this and update the default USB_GADGET_PRODUCT_NUM Kconfig option for remaining supported Rockchip SoCs to match the product id used in Maskrom mode. Also remove a reference to an undefined ROCKCHIP_RK3229 Kconfig symbol. Signed-off-by: Jonas Karlman --- drivers/usb/gadget/Kconfig | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index c72a8047635..4621a6fd5e6 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -70,12 +70,21 @@ config USB_GADGET_PRODUCT_NUM hex "Product ID of the USB device" default 0x701a if ARCH_TEGRA default 0x1010 if ARCH_SUNXI - default 0x310a if ROCKCHIP_RK3036 + default 0x110a if ROCKCHIP_RV1108 + default 0x110b if ROCKCHIP_RV1126 default 0x300a if ROCKCHIP_RK3066 + default 0x301a if ROCKCHIP_RK3036 + default 0x310b if ROCKCHIP_RK3188 default 0x310c if ROCKCHIP_RK3128 - default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288 - default 0x330a if ROCKCHIP_RK3328 + default 0x320a if ROCKCHIP_RK3288 + default 0x320b if ROCKCHIP_RK322X + default 0x320c if ROCKCHIP_RK3328 + default 0x330a if ROCKCHIP_RK3368 default 0x330c if ROCKCHIP_RK3399 + default 0x330d if ROCKCHIP_PX30 + default 0x330e if ROCKCHIP_RK3308 + default 0x350a if ROCKCHIP_RK3568 + default 0x350b if ROCKCHIP_RK3588 default 0x0 help Product ID of the USB device emulated, reported to the host device. From 06fac9dd1475fad7016c7ef6c68acdaf48b055b4 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 10 Mar 2024 18:50:58 +0000 Subject: [PATCH 56/91] rockchip: board: Prepare for use of DM_USB_GADGET with DWC2_OTG The board_usb_init() and board_usb_cleanup() functions is always included when USB_GADGET and USB_GADGET_DWC2_OTG is enabled. Prepare for a change to use DM_USB_GADGET with DWC2_OTG by adding an extra ifdef condition. The extra separate ifdef for USB_GADGET prepare for next patch that adds a g_dnl_bind_fixup() function. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/board.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 4f666aee706..9bd5b14d126 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -220,7 +220,8 @@ void enable_caches(void) } #endif -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#if IS_ENABLED(CONFIG_USB_GADGET) +#if IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG) && !IS_ENABLED(CONFIG_DM_USB_GADGET) #include #include #include @@ -296,6 +297,7 @@ int board_usb_cleanup(int index, enum usb_init_type init) return 0; } #endif /* CONFIG_USB_GADGET_DWC2_OTG */ +#endif /* CONFIG_USB_GADGET */ #if IS_ENABLED(CONFIG_FASTBOOT) int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) From 2b6a013caf3ca6daa84a96ee72ea2cb88cf78a8f Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 10 Mar 2024 18:50:59 +0000 Subject: [PATCH 57/91] rockchip: board: Use a common USB Product ID for UMS Change to use the common Product ID 0x0010 when the ums command is used. This matches downstream vendor U-Boot and is a Product ID that tools such as rkdeveloptool and RKDevTool will identify as MSC mode. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/board.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 9bd5b14d126..31a11110f44 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -221,8 +221,23 @@ void enable_caches(void) #endif #if IS_ENABLED(CONFIG_USB_GADGET) -#if IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG) && !IS_ENABLED(CONFIG_DM_USB_GADGET) #include + +#if IS_ENABLED(CONFIG_USB_GADGET_DOWNLOAD) +#define ROCKCHIP_G_DNL_UMS_PRODUCT_NUM 0x0010 + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + if (!strcmp(name, "usb_dnl_ums")) + put_unaligned(ROCKCHIP_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct); + else + put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct); + + return 0; +} +#endif /* CONFIG_USB_GADGET_DOWNLOAD */ + +#if IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG) && !IS_ENABLED(CONFIG_DM_USB_GADGET) #include #include From 1bc4e8eb1d7f0eb49240a5b5ba5714b925147641 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 10 Mar 2024 18:51:00 +0000 Subject: [PATCH 58/91] rockchip: Migrate to use DM_USB_GADGET on RK3328 USB gadget is not working fully as expected on RK3328, it uses a board_usb_init() function to initialize the DWC2 OTG port. The board_usb_init() function does not intgrate with the generic phy framework and as a result the USB phy is not properly configured before or after USB gadget use. Having both USB_DWC2 and DWC2_OTG enabled for the same board is also causing some issues. Trying to use rockusb or ums command after usb stop result in a freeze due to usb stop is putting the phy in a suspended state. => usb start => usb stop => ums 0 mmc 0 --> freeze due to usb phy is suspended <-- Fix this by only using one of USB_DWC2 (host) or DWC2_OTG (peripheral) depending on the most likely usage of the otg port and by migrating to use DM_USB_GADGET instead of a board_usb_init() function. The nanopi-r2 and orangepi-r1-plus variants share OTG and power using a Type-C connector, mark these boards dr_mode as peripheral, the most likely usage is for recovery and image download. The rock64 and roc-cc currently use dr_mode as host, remove the DWC2_OTG driver from these boards to ensure that the USB_DWC2 driver is used. The rock-pi-e board does not enable the usb20_otg node so both USB_DWC2 and DWC2_OTG is removed from this board. Enable RockUSB and UMS on all boards with a otg port in peripheral mode. Also with the migration to DM_USB_GADGET completed the U-Boot specific change to reorder usb nodes in the soc device tree can be reverted. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 4 ++ .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 4 ++ .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 4 ++ arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 4 ++ arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 9 ++++ arch/arm/dts/rk3328-rock64-u-boot.dtsi | 4 ++ arch/arm/dts/rk3328-u-boot.dtsi | 4 -- arch/arm/dts/rk3328.dtsi | 41 ++++++++----------- configs/evb-rk3328_defconfig | 7 +++- configs/nanopi-r2c-plus-rk3328_defconfig | 7 +++- configs/nanopi-r2c-rk3328_defconfig | 7 +++- configs/nanopi-r2s-rk3328_defconfig | 7 +++- configs/orangepi-r1-plus-lts-rk3328_defconfig | 7 +++- configs/orangepi-r1-plus-rk3328_defconfig | 7 +++- configs/roc-cc-rk3328_defconfig | 7 ---- configs/rock-pi-e-rk3328_defconfig | 7 ---- configs/rock64-rk3328_defconfig | 6 --- 17 files changed, 75 insertions(+), 61 deletions(-) diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi index cca4f06145c..4fa170eeaf8 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi @@ -15,6 +15,10 @@ bootph-all; }; +&usb20_otg { + dr_mode = "peripheral"; +}; + &vcc_io_sdio { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi index 0dbe5a01f98..0a9423cd9c7 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi @@ -33,6 +33,10 @@ bootph-pre-ram; }; +&usb20_otg { + dr_mode = "peripheral"; +}; + &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi index 1af75ada1a6..1096821fc5d 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi @@ -33,6 +33,10 @@ bootph-pre-ram; }; +&usb20_otg { + dr_mode = "peripheral"; +}; + &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi index 47d74964fd0..582d6ba49b4 100644 --- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -29,6 +29,10 @@ }; }; +&usb20_otg { + hnp-srp-disable; +}; + &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi index 9ed0aef1ecc..d314bfad6fc 100644 --- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi @@ -29,6 +29,15 @@ }; }; +&u2phy_host { + phy-supply = <&vcc_host_5v>; +}; + +&vcc_host_5v { + /delete-property/ regulator-always-on; + /delete-property/ regulator-boot-on; +}; + &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 85426495c3d..551cff6f24f 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -55,6 +55,10 @@ bootph-pre-ram; }; +&usb20_otg { + hnp-srp-disable; +}; + &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index 4d43fe2fb51..e0c6aee58ab 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -130,10 +130,6 @@ bootph-all; }; -&usb20_otg { - hnp-srp-disable; -}; - #ifdef CONFIG_ROCKCHIP_SPI_IMAGE &binman { simple-bin-spi { diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index fe81b97bbe7..fb5dcf6e932 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -965,6 +965,22 @@ }; }; + usb20_otg: usb@ff580000 { + compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff580000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + usb_host0_ehci: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0x0 0xff5c0000 0x0 0x10000>; @@ -1004,31 +1020,6 @@ status = "disabled"; }; - /* - * U-Boot Specific Change - * - * The OTG controller must come after the USB host pair for it - * to work. This is likely due to lack of support for the USB - * PHYs. This must be manually changed after each device tree - * sync. There is no clean way to handle this in -u-boot.dtsi - * files. - */ - usb20_otg: usb@ff580000 { - compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff580000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - gic: interrupt-controller@ff811000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 4fa8a7d365a..75a0e0f286b 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -31,6 +31,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_REGULATOR=y @@ -83,17 +85,18 @@ CONFIG_SYSINFO=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set -CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig index 5302fd91a0f..beef682a582 100644 --- a/configs/nanopi-r2c-plus-rk3328_defconfig +++ b/configs/nanopi-r2c-plus-rk3328_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_REGULATOR=y @@ -90,17 +92,18 @@ CONFIG_SYSINFO=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set -CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index 5a722c18263..8960c1afaba 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_REGULATOR=y @@ -90,17 +92,18 @@ CONFIG_SYSINFO=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set -CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 985d02475ec..96e67e248d3 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_REGULATOR=y @@ -90,17 +92,18 @@ CONFIG_SYSINFO=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set -CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig index e9f7a130692..5fbbd5fc655 100644 --- a/configs/orangepi-r1-plus-lts-rk3328_defconfig +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -38,6 +38,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_REGULATOR=y @@ -100,17 +102,18 @@ CONFIG_SYSINFO=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set -CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig index 6019f33ae3f..c5afe5ea6e5 100644 --- a/configs/orangepi-r1-plus-rk3328_defconfig +++ b/configs/orangepi-r1-plus-rk3328_defconfig @@ -38,6 +38,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_REGULATOR=y @@ -100,17 +102,18 @@ CONFIG_SYSINFO=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set -CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 191dbff928b..6526d2606e7 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y -# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y @@ -34,7 +33,6 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_REGULATOR=y @@ -55,8 +53,6 @@ CONFIG_SPL_SYSCON=y CONFIG_TPL_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_FASTBOOT_BUF_ADDR=0x800800 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -97,10 +93,7 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y -# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index e4f2123e0b1..23029255bca 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y -# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y @@ -52,8 +51,6 @@ CONFIG_SPL_SYSCON=y CONFIG_TPL_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_FASTBOOT_BUF_ADDR=0x800800 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -92,12 +89,8 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y -# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index f38431891bf..b0be1d1d763 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -16,7 +16,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y -# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y @@ -59,8 +58,6 @@ CONFIG_SPL_SYSCON=y CONFIG_TPL_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_FASTBOOT_BUF_ADDR=0x800800 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -106,10 +103,7 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y -# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y From 710d7f27e29d76e5a387ded95963ecd47dc784a9 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 12 Mar 2024 23:36:11 +0000 Subject: [PATCH 59/91] board: rockchip: rk3399: Add device tree files to MAINTAINERS Update MAINTAINERS files for RK3399 boards to include related device tree files. Also correct a few filenames. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- board/firefly/roc-pc-rk3399/MAINTAINERS | 1 + board/pine64/pinebook-pro-rk3399/MAINTAINERS | 5 ++- board/pine64/pinephone-pro-rk3399/MAINTAINERS | 5 ++- board/pine64/rockpro64_rk3399/MAINTAINERS | 2 +- board/rockchip/evb_rk3399/MAINTAINERS | 35 ++++++++++--------- board/vamrs/rock960_rk3399/MAINTAINERS | 2 ++ 6 files changed, 27 insertions(+), 23 deletions(-) diff --git a/board/firefly/roc-pc-rk3399/MAINTAINERS b/board/firefly/roc-pc-rk3399/MAINTAINERS index 68a5b757d1d..2c0de4432fa 100644 --- a/board/firefly/roc-pc-rk3399/MAINTAINERS +++ b/board/firefly/roc-pc-rk3399/MAINTAINERS @@ -6,3 +6,4 @@ F: board/firefly/roc-pc-rk3399 F: include/configs/roc-pc-rk3399.h F: configs/roc-pc-rk3399_defconfig F: configs/roc-pc-mezzanine-rk3399_defconfig +F: arch/arm/dts/rk3399-roc-pc* diff --git a/board/pine64/pinebook-pro-rk3399/MAINTAINERS b/board/pine64/pinebook-pro-rk3399/MAINTAINERS index 7300ca1b1b8..287ed434605 100644 --- a/board/pine64/pinebook-pro-rk3399/MAINTAINERS +++ b/board/pine64/pinebook-pro-rk3399/MAINTAINERS @@ -2,7 +2,6 @@ PINEBOOK_PRO M: Peter Robinson S: Maintained F: board/pine64/pinebook-pro-rk3399/ -F: include/configs/rk3399-pinebook-pro.h -F: arch/arm/dts/rk3399-pinebook-pro.dts -F: arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +F: include/configs/pinebook-pro-rk3399.h +F: arch/arm/dts/rk3399-pinebook-pro* F: configs/pinebook-pro-rk3399_defconfig diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS index bc2dcdd8d42..959566a877e 100644 --- a/board/pine64/pinephone-pro-rk3399/MAINTAINERS +++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS @@ -2,7 +2,6 @@ PINEPHONE_PRO M: Peter Robinson S: Maintained F: board/pine64/pinephone-pro-rk3399/ -F: include/configs/rk3399-pinephone-pro.h -F: arch/arm/dts/rk3399-pinephone-pro.dts -F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +F: include/configs/pinephone-pro-rk3399.h +F: arch/arm/dts/rk3399-pinephone-pro* F: configs/pinephone-pro-rk3399_defconfig diff --git a/board/pine64/rockpro64_rk3399/MAINTAINERS b/board/pine64/rockpro64_rk3399/MAINTAINERS index 220ee21f230..d9e11f4bab3 100644 --- a/board/pine64/rockpro64_rk3399/MAINTAINERS +++ b/board/pine64/rockpro64_rk3399/MAINTAINERS @@ -3,5 +3,5 @@ M: Jagan Teki S: Maintained F: board/pine64/rockpro64_rk3399 F: include/configs/rockpro64_rk3399.h -F: arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +F: arch/arm/dts/rk3399-rockpro64* F: configs/rockpro64-rk3399_defconfig diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index acdb840f209..f45f81623a3 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -4,48 +4,53 @@ S: Maintained F: board/rockchip/evb_rk3399 F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig +F: arch/arm/dts/rk3399-evb* F: configs/firefly-rk3399_defconfig +F: arch/arm/dts/rk3399-firefly* EAIDK-610 M: Andy Yan S: Maintained F: configs/eaidk-610-rk3399_defconfig -F: arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi +F: arch/arm/dts/rk3399-eaidk-610* KHADAS-EDGE M: Nick Xie S: Maintained F: configs/khadas-edge-rk3399_defconfig +F: arch/arm/dts/rk3399-khadas-edge.dts +F: arch/arm/dts/rk3399-khadas-edge.dtsi F: arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi KHADAS-EDGE-CAPTAIN M: Nick Xie S: Maintained F: configs/khadas-edge-captain-rk3399_defconfig -F: arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi +F: arch/arm/dts/rk3399-khadas-edge-captain* KHADAS-EDGE-V M: Nick Xie S: Maintained F: configs/khadas-edge-v-rk3399_defconfig -F: arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi +F: arch/arm/dts/rk3399-khadas-edge-v* LEEZ-P710 M: Andy Yan S: Maintained -F: arch/arm/dts/rk3399-leez-p710-u-boot.dtsi +F: arch/arm/dts/rk3399-leez-p710* F: configs/leez-rk3399_defconfig NANOPC-T4 M: Jagan Teki S: Maintained F: configs/nanopc-t4-rk3399_defconfig -F: arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi +F: arch/arm/dts/rk3399-nanopc-t4* NANOPI-M4 M: Jagan Teki S: Maintained F: configs/nanopi-m4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-m4.dts F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi NANOPI-M4-2GB @@ -53,55 +58,53 @@ M: Jagan Teki M: Deepak Das S: Maintained F: configs/nanopi-m4-2gb-rk3399_defconfig -F: arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi +F: arch/arm/dts/rk3399-nanopi-m4-2gb* NANOPI-M4B M: Alexandre Vicenzi S: Maintained F: configs/nanopi-m4b-rk3399_defconfig -F: arch/arm/dts/rk3399-nanopi-m4b-u-boot.dtsi +F: arch/arm/dts/rk3399-nanopi-m4b* NANOPI-NEO4 M: Jagan Teki S: Maintained F: configs/nanopi-neo4-rk3399_defconfig -F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi +F: arch/arm/dts/rk3399-nanopi-neo4* NANOPI-R4S M: Xiaobo Tian S: Maintained F: configs/nanopi-r4s-rk3399_defconfig -F: arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi +F: arch/arm/dts/rk3399-nanopi-r4s* ORANGEPI-RK3399 M: Jagan Teki S: Maintained F: configs/orangepi-rk3399_defconfig -F: arch/arm/dts/rk3399-u-boot.dtsi -F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi +F: arch/arm/dts/rk3399-orangepi* ROCK-4C+ M: FUKAUMI Naoki S: Maintained F: configs/rock-4c-plus-rk3399_defconfig -F: arch/arm/dts/rk3399-rock-4c-plus.dts +F: arch/arm/dts/rk3399-rock-4c-plus* ROCK-4SE M: Christopher Obbard S: Maintained F: configs/rock-4se-rk3399_defconfig -F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi +F: arch/arm/dts/rk3399-rock-4se* ROCK-PI-4 M: Jagan Teki S: Maintained F: configs/rock-pi-4-rk3399_defconfig -F: arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi F: configs/rock-pi-4c-rk3399_defconfig -F: arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi +F: arch/arm/dts/rk3399-rock-pi-4* ROCK-PI-N10 M: Jagan Teki S: Maintained F: configs/rock-pi-n10-rk3399pro_defconfig -F: arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi +F: arch/arm/dts/rk3399pro-rock-pi-n10* diff --git a/board/vamrs/rock960_rk3399/MAINTAINERS b/board/vamrs/rock960_rk3399/MAINTAINERS index 8821672a3ab..f2121b19145 100644 --- a/board/vamrs/rock960_rk3399/MAINTAINERS +++ b/board/vamrs/rock960_rk3399/MAINTAINERS @@ -4,8 +4,10 @@ S: Maintained F: board/vamrs/rock960_rk3399/ F: include/configs/rock960_rk3399.h F: configs/rock960-rk3399_defconfig +F: arch/arm/dts/rk3399-rock960* FICUS EE M: Manivannan Sadhasivam S: Maintained F: configs/ficus-rk3399_defconfig +F: arch/arm/dts/rk3399-ficus* From 053c8139261f1814be8cff7ff3a6ca1a12a069cd Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 12 Mar 2024 23:36:12 +0000 Subject: [PATCH 60/91] board: rockchip: rk3399: Add myself as reviewer to MAINTAINERS Add myself as a reviewer for RK3399 boards that I have and can help with review and testing of defconfig and device tree changes. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- board/pine64/pinebook-pro-rk3399/MAINTAINERS | 1 + board/pine64/rockpro64_rk3399/MAINTAINERS | 1 + board/rockchip/evb_rk3399/MAINTAINERS | 3 +++ 3 files changed, 5 insertions(+) diff --git a/board/pine64/pinebook-pro-rk3399/MAINTAINERS b/board/pine64/pinebook-pro-rk3399/MAINTAINERS index 287ed434605..2cafd1a41e5 100644 --- a/board/pine64/pinebook-pro-rk3399/MAINTAINERS +++ b/board/pine64/pinebook-pro-rk3399/MAINTAINERS @@ -1,5 +1,6 @@ PINEBOOK_PRO M: Peter Robinson +R: Jonas Karlman S: Maintained F: board/pine64/pinebook-pro-rk3399/ F: include/configs/pinebook-pro-rk3399.h diff --git a/board/pine64/rockpro64_rk3399/MAINTAINERS b/board/pine64/rockpro64_rk3399/MAINTAINERS index d9e11f4bab3..42084aef0eb 100644 --- a/board/pine64/rockpro64_rk3399/MAINTAINERS +++ b/board/pine64/rockpro64_rk3399/MAINTAINERS @@ -1,5 +1,6 @@ ROCKPRO64 M: Jagan Teki +R: Jonas Karlman S: Maintained F: board/pine64/rockpro64_rk3399 F: include/configs/rockpro64_rk3399.h diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index f45f81623a3..7815ea9ff07 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -86,18 +86,21 @@ F: arch/arm/dts/rk3399-orangepi* ROCK-4C+ M: FUKAUMI Naoki +R: Jonas Karlman S: Maintained F: configs/rock-4c-plus-rk3399_defconfig F: arch/arm/dts/rk3399-rock-4c-plus* ROCK-4SE M: Christopher Obbard +R: Jonas Karlman S: Maintained F: configs/rock-4se-rk3399_defconfig F: arch/arm/dts/rk3399-rock-4se* ROCK-PI-4 M: Jagan Teki +R: Jonas Karlman S: Maintained F: configs/rock-pi-4-rk3399_defconfig F: configs/rock-pi-4c-rk3399_defconfig From 4b6e00454fe37a3ec3304ad88396bbb28066f44c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 12 Mar 2024 23:36:13 +0000 Subject: [PATCH 61/91] board: rockchip: rk3399: Remove unused board_early_init_f functions These functions is excluded from SPL build and BOARD_EARLY_INIT_F is not enabled for any of the affected boards, so this legacy code is not used. Rockchip common board code already enable all regulators flagged as always-on or boot-on in device tree, and fixed/gpio regulators now have basic reference counting support so the original intent of this code is no longer valid. Remove the unneeded and unused code that used to enable usb regulators. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 22 +------------------ .../pinebook-pro-rk3399/pinebook-pro-rk3399.c | 22 ------------------- .../pinephone-pro-rk3399.c | 22 ------------------- board/rockchip/evb_rk3399/evb-rk3399.c | 20 ----------------- 4 files changed, 1 insertion(+), 85 deletions(-) diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c index 93e7d776fb2..590519b32af 100644 --- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c @@ -9,32 +9,12 @@ #include #include #include -#include #include #include #include -#ifndef CONFIG_SPL_BUILD -int board_early_init_f(void) -{ - struct udevice *regulator; - int ret; - - ret = regulator_get_by_platname("vcc5v0_host", ®ulator); - if (ret) { - debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret); - goto out; - } - - ret = regulator_set_enable(regulator, true); - if (ret) - debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret); -out: - return 0; -} - -#else +#ifdef CONFIG_SPL_BUILD #define PMUGRF_BASE 0xff320000 #define GPIO0_BASE 0xff720000 diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c index 5e758ea6cd9..0001022c62a 100644 --- a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c +++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c @@ -11,32 +11,10 @@ #include #include #include -#include #define GRF_IO_VSEL_BT565_SHIFT 0 #define PMUGRF_CON0_VSEL_SHIFT 8 -#ifndef CONFIG_SPL_BUILD -int board_early_init_f(void) -{ - struct udevice *regulator; - int ret; - - ret = regulator_get_by_platname("vcc5v0_usb", ®ulator); - if (ret) { - pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret); - goto out; - } - - ret = regulator_set_enable(regulator, true); - if (ret) - pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret); - -out: - return 0; -} -#endif - #ifdef CONFIG_MISC_INIT_R static void setup_iodomain(void) { diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c index c9b0d5a061d..06dc512c57d 100644 --- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c +++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c @@ -11,33 +11,11 @@ #include #include #include -#include #define GRF_IO_VSEL_BT565_GPIO2AB 1 #define GRF_IO_VSEL_AUDIO_GPIO3D4A 2 #define PMUGRF_CON0_VSEL_SHIFT 8 -#ifndef CONFIG_SPL_BUILD -int board_early_init_f(void) -{ - struct udevice *regulator; - int ret; - - ret = regulator_get_by_platname("vcc5v0_usb", ®ulator); - if (ret) { - pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret); - goto out; - } - - ret = regulator_set_enable(regulator, true); - if (ret) - pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret); - -out: - return 0; -} -#endif - #ifdef CONFIG_MISC_INIT_R static void setup_iodomain(void) { diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index 3c773d0930c..ebdd74a7b97 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -10,7 +10,6 @@ #include #include #include -#include #define ROCKPI4_UPDATABLE_IMAGES 2 @@ -25,25 +24,6 @@ struct efi_capsule_update_info update_info = { #endif #ifndef CONFIG_SPL_BUILD -int board_early_init_f(void) -{ - struct udevice *regulator; - int ret; - - ret = regulator_get_by_platname("vcc5v0_host", ®ulator); - if (ret) { - debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret); - goto out; - } - - ret = regulator_set_enable(regulator, true); - if (ret) - debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret); - -out: - return 0; -} - #if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) static bool board_is_rockpi_4b(void) { From b65850509c9443e8e5fb8fb9c01a9be82441bc35 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 12 Mar 2024 23:36:14 +0000 Subject: [PATCH 62/91] board: rockchip: Add a common ROCK Pi 4 target Move ROCK Pi 4 specific board code from the shared evb_rk3399 target into its own board target and update related defconfigs to use the new TARGET_ROCKPI4_RK3399 option. Signed-off-by: Jonas Karlman Reviewed-by: Christopher Obbard Reviewed-by: Peter Robinson --- arch/arm/mach-rockchip/rk3399/Kconfig | 6 ++++ board/radxa/rockpi4-rk3399/Kconfig | 15 +++++++++ board/radxa/rockpi4-rk3399/MAINTAINERS | 22 +++++++++++++ .../rockpi4-rk3399}/Makefile | 2 +- .../rockpi4-rk3399/rockpi4-rk3399.c} | 13 ++------ board/rockchip/evb_rk3399/MAINTAINERS | 22 ------------- configs/rock-4c-plus-rk3399_defconfig | 2 +- configs/rock-4se-rk3399_defconfig | 2 +- configs/rock-pi-4-rk3399_defconfig | 2 +- configs/rock-pi-4c-rk3399_defconfig | 2 +- include/configs/rk3399_common.h | 16 ---------- include/configs/rockpi4-rk3399.h | 32 +++++++++++++++++++ 12 files changed, 83 insertions(+), 53 deletions(-) create mode 100644 board/radxa/rockpi4-rk3399/Kconfig create mode 100644 board/radxa/rockpi4-rk3399/MAINTAINERS rename board/{rockchip/evb_rk3399 => radxa/rockpi4-rk3399}/Makefile (79%) rename board/{rockchip/evb_rk3399/evb-rk3399.c => radxa/rockpi4-rk3399/rockpi4-rk3399.c} (79%) create mode 100644 include/configs/rockpi4-rk3399.h diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 38904291dfa..04a84e2f6a0 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -89,6 +89,11 @@ config TARGET_ROCK960_RK3399 * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), 1x USB 3.0 type C OTG +config TARGET_ROCKPI4_RK3399 + bool "Radxa ROCK Pi 4 board" + help + Support for ROCK Pi 4 board family by Radxa. + config TARGET_ROCKPRO64_RK3399 bool "Pine64 Rockpro64 board" help @@ -177,6 +182,7 @@ source "board/google/gru/Kconfig" source "board/pine64/pinebook-pro-rk3399/Kconfig" source "board/pine64/pinephone-pro-rk3399/Kconfig" source "board/pine64/rockpro64_rk3399/Kconfig" +source "board/radxa/rockpi4-rk3399/Kconfig" source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" diff --git a/board/radxa/rockpi4-rk3399/Kconfig b/board/radxa/rockpi4-rk3399/Kconfig new file mode 100644 index 00000000000..d82663506b1 --- /dev/null +++ b/board/radxa/rockpi4-rk3399/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ROCKPI4_RK3399 + +config SYS_BOARD + default "rockpi4-rk3399" + +config SYS_VENDOR + default "radxa" + +config SYS_CONFIG_NAME + default "rockpi4-rk3399" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/radxa/rockpi4-rk3399/MAINTAINERS b/board/radxa/rockpi4-rk3399/MAINTAINERS new file mode 100644 index 00000000000..da5273fb9a3 --- /dev/null +++ b/board/radxa/rockpi4-rk3399/MAINTAINERS @@ -0,0 +1,22 @@ +ROCK-PI-4 +M: Jagan Teki +R: Jonas Karlman +S: Maintained +F: board/radxa/rockpi4-rk3399/ +F: configs/rock-pi-4-rk3399_defconfig +F: configs/rock-pi-4c-rk3399_defconfig +F: arch/arm/dts/rk3399-rock-pi-4* + +ROCK-4C+ +M: FUKAUMI Naoki +R: Jonas Karlman +S: Maintained +F: configs/rock-4c-plus-rk3399_defconfig +F: arch/arm/dts/rk3399-rock-4c-plus* + +ROCK-4SE +M: Christopher Obbard +R: Jonas Karlman +S: Maintained +F: configs/rock-4se-rk3399_defconfig +F: arch/arm/dts/rk3399-rock-4se* diff --git a/board/rockchip/evb_rk3399/Makefile b/board/radxa/rockpi4-rk3399/Makefile similarity index 79% rename from board/rockchip/evb_rk3399/Makefile rename to board/radxa/rockpi4-rk3399/Makefile index aaa51c212e5..3d022533227 100644 --- a/board/rockchip/evb_rk3399/Makefile +++ b/board/radxa/rockpi4-rk3399/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += evb-rk3399.o +obj-y += rockpi4-rk3399.o diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c similarity index 79% rename from board/rockchip/evb_rk3399/evb-rk3399.c rename to board/radxa/rockpi4-rk3399/rockpi4-rk3399.c index ebdd74a7b97..a533128b92f 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c @@ -3,13 +3,8 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include #include #include -#include -#include -#include -#include #define ROCKPI4_UPDATABLE_IMAGES 2 @@ -24,17 +19,15 @@ struct efi_capsule_update_info update_info = { #endif #ifndef CONFIG_SPL_BUILD -#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) static bool board_is_rockpi_4b(void) { - return CONFIG_IS_ENABLED(TARGET_EVB_RK3399) && - of_machine_is_compatible("radxa,rockpi4b"); + return of_machine_is_compatible("radxa,rockpi4b"); } static bool board_is_rockpi_4c(void) { - return CONFIG_IS_ENABLED(TARGET_EVB_RK3399) && - of_machine_is_compatible("radxa,rockpi4c"); + return of_machine_is_compatible("radxa,rockpi4c"); } void rockchip_capsule_update_board_setup(void) diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 7815ea9ff07..8dab3fa70f5 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -84,28 +84,6 @@ S: Maintained F: configs/orangepi-rk3399_defconfig F: arch/arm/dts/rk3399-orangepi* -ROCK-4C+ -M: FUKAUMI Naoki -R: Jonas Karlman -S: Maintained -F: configs/rock-4c-plus-rk3399_defconfig -F: arch/arm/dts/rk3399-rock-4c-plus* - -ROCK-4SE -M: Christopher Obbard -R: Jonas Karlman -S: Maintained -F: configs/rock-4se-rk3399_defconfig -F: arch/arm/dts/rk3399-rock-4se* - -ROCK-PI-4 -M: Jagan Teki -R: Jonas Karlman -S: Maintained -F: configs/rock-pi-4-rk3399_defconfig -F: configs/rock-pi-4c-rk3399_defconfig -F: arch/arm/dts/rk3399-rock-pi-4* - ROCK-PI-N10 M: Jagan Teki S: Maintained diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index 1652da5b6ca..bebea4fd069 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -8,7 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y -CONFIG_TARGET_EVB_RK3399=y +CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index e51a074a297..712502517eb 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -8,7 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y -CONFIG_TARGET_EVB_RK3399=y +CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 6dc60759005..bca44beca12 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -8,7 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y -CONFIG_TARGET_EVB_RK3399=y +CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 5c71f0bd9e8..e1adec60017 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -8,7 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y -CONFIG_TARGET_EVB_RK3399=y +CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 96ba19c659b..4e75771055b 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -13,22 +13,6 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 -#define ROCKPI_4B_IDBLOADER_IMAGE_GUID \ - EFI_GUID(0x02f4d760, 0xcfd5, 0x43bd, 0x8e, 0x2d, \ - 0xa4, 0x2a, 0xcb, 0x33, 0xc6, 0x60) - -#define ROCKPI_4B_UBOOT_IMAGE_GUID \ - EFI_GUID(0x4ce292da, 0x1dd8, 0x428d, 0xa1, 0xc2, \ - 0x77, 0x74, 0x3e, 0xf8, 0xb9, 0x6e) - -#define ROCKPI_4C_IDBLOADER_IMAGE_GUID \ - EFI_GUID(0xfd68510c, 0x12d3, 0x4f0a, 0xb8, 0xd3, \ - 0xd8, 0x79, 0xe1, 0xd3, 0xa5, 0x40) - -#define ROCKPI_4C_UBOOT_IMAGE_GUID \ - EFI_GUID(0xb81fb4ae, 0xe4f3, 0x471b, 0x99, 0xb4, \ - 0x0b, 0x3d, 0xa5, 0x49, 0xce, 0x13) - #ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rockpi4-rk3399.h b/include/configs/rockpi4-rk3399.h new file mode 100644 index 00000000000..1936e06ab3c --- /dev/null +++ b/include/configs/rockpi4-rk3399.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __ROCKPI4_RK3399_H +#define __ROCKPI4_RK3399_H + +#define ROCKPI_4B_IDBLOADER_IMAGE_GUID \ + EFI_GUID(0x02f4d760, 0xcfd5, 0x43bd, 0x8e, 0x2d, \ + 0xa4, 0x2a, 0xcb, 0x33, 0xc6, 0x60) + +#define ROCKPI_4B_UBOOT_IMAGE_GUID \ + EFI_GUID(0x4ce292da, 0x1dd8, 0x428d, 0xa1, 0xc2, \ + 0x77, 0x74, 0x3e, 0xf8, 0xb9, 0x6e) + +#define ROCKPI_4C_IDBLOADER_IMAGE_GUID \ + EFI_GUID(0xfd68510c, 0x12d3, 0x4f0a, 0xb8, 0xd3, \ + 0xd8, 0x79, 0xe1, 0xd3, 0xa5, 0x40) + +#define ROCKPI_4C_UBOOT_IMAGE_GUID \ + EFI_GUID(0xb81fb4ae, 0xe4f3, 0x471b, 0x99, 0xb4, \ + 0x0b, 0x3d, 0xa5, 0x49, 0xce, 0x13) + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif From 626dbdd51234f321a0c8d6ba4ca51a71b2b48990 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 12 Mar 2024 23:36:15 +0000 Subject: [PATCH 63/91] rockchip: io-domain: Add support for RK3399 Port the RK3399 part of the Rockchip IO-domain driver from linux. This differs from linux version in that pmu io iodomain bit is enabled in the write ops instead of in an init ops as in linux, this way we can avoid keeping a full state of all supply that have been configured. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/misc/rockchip-io-domain.c | 79 +++++++++++++++++++++++++++++-- 1 file changed, 75 insertions(+), 4 deletions(-) diff --git a/drivers/misc/rockchip-io-domain.c b/drivers/misc/rockchip-io-domain.c index 3f6227f993f..0ffea32ef07 100644 --- a/drivers/misc/rockchip-io-domain.c +++ b/drivers/misc/rockchip-io-domain.c @@ -5,7 +5,6 @@ * Ported from linux drivers/soc/rockchip/io-domain.c */ -#include #include #include #include @@ -28,6 +27,10 @@ #define MAX_VOLTAGE_1_8 1980000 #define MAX_VOLTAGE_3_3 3600000 +#define RK3399_PMUGRF_CON0 0x180 +#define RK3399_PMUGRF_CON0_VSEL BIT(8) +#define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9 + #define RK3568_PMU_GRF_IO_VSEL0 0x0140 #define RK3568_PMU_GRF_IO_VSEL1 0x0144 #define RK3568_PMU_GRF_IO_VSEL2 0x0148 @@ -35,10 +38,10 @@ struct rockchip_iodomain_soc_data { int grf_offset; const char *supply_names[MAX_SUPPLIES]; - int (*write)(struct regmap *grf, int idx, int uV); + int (*write)(struct regmap *grf, uint offset, int idx, int uV); }; -static int rk3568_iodomain_write(struct regmap *grf, int idx, int uV) +static int rk3568_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) { u32 is_3v3 = uV > MAX_VOLTAGE_1_8; u32 val0, val1; @@ -78,6 +81,64 @@ static int rk3568_iodomain_write(struct regmap *grf, int idx, int uV) return 0; } +static int rockchip_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) +{ + u32 val; + + /* set value bit */ + val = (uV > MAX_VOLTAGE_1_8) ? 0 : 1; + val <<= idx; + + /* apply hiword-mask */ + val |= (BIT(idx) << 16); + + return regmap_write(grf, offset, val); +} + +static int rk3399_pmu_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) +{ + int ret = rockchip_iodomain_write(grf, offset, idx, uV); + + if (!ret && idx == RK3399_PMUGRF_VSEL_SUPPLY_NUM) { + /* + * set pmu io iodomain to also use this framework + * instead of a special gpio. + */ + u32 val = RK3399_PMUGRF_CON0_VSEL | (RK3399_PMUGRF_CON0_VSEL << 16); + ret = regmap_write(grf, RK3399_PMUGRF_CON0, val); + } + + return ret; +} + +static const struct rockchip_iodomain_soc_data soc_data_rk3399 = { + .grf_offset = 0xe640, + .supply_names = { + "bt656-supply", /* APIO2_VDD */ + "audio-supply", /* APIO5_VDD */ + "sdmmc-supply", /* SDMMC0_VDD */ + "gpio1830-supply", /* APIO4_VDD */ + }, + .write = rockchip_iodomain_write, +}; + +static const struct rockchip_iodomain_soc_data soc_data_rk3399_pmu = { + .grf_offset = 0x180, + .supply_names = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "pmu1830-supply", /* PMUIO2_VDD */ + }, + .write = rk3399_pmu_iodomain_write, +}; + static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = { .grf_offset = 0x140, .supply_names = { @@ -95,6 +156,14 @@ static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = { }; static const struct udevice_id rockchip_iodomain_ids[] = { + { + .compatible = "rockchip,rk3399-io-voltage-domain", + .data = (ulong)&soc_data_rk3399, + }, + { + .compatible = "rockchip,rk3399-pmu-io-voltage-domain", + .data = (ulong)&soc_data_rk3399_pmu, + }, { .compatible = "rockchip,rk3568-pmu-io-voltage-domain", .data = (ulong)&soc_data_rk3568_pmu, @@ -152,7 +221,9 @@ static int rockchip_iodomain_probe(struct udevice *dev) continue; } - soc_data->write(grf, i, uV); + ret = soc_data->write(grf, soc_data->grf_offset, i, uV); + if (ret) + dev_err(dev, "%s: Couldn't write to GRF\n", supply_name); } return 0; From eaeaf04a3d536a097524f66e26b8157e71e328bb Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 12 Mar 2024 23:36:16 +0000 Subject: [PATCH 64/91] rockchip: pine64: rockpro64: Migrate to use IO-domain driver Switch to use the IO-domain driver to configure IO-domain based on device tree instead of a setup_iodomain() function. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- board/pine64/rockpro64_rk3399/Makefile | 7 ---- .../rockpro64_rk3399/rockpro64-rk3399.c | 39 ------------------- configs/rockpro64-rk3399_defconfig | 1 + 3 files changed, 1 insertion(+), 46 deletions(-) delete mode 100644 board/pine64/rockpro64_rk3399/Makefile delete mode 100644 board/pine64/rockpro64_rk3399/rockpro64-rk3399.c diff --git a/board/pine64/rockpro64_rk3399/Makefile b/board/pine64/rockpro64_rk3399/Makefile deleted file mode 100644 index b015c47e6fa..00000000000 --- a/board/pine64/rockpro64_rk3399/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2019 Vasily Khoruzhick -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += rockpro64-rk3399.o diff --git a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c b/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c deleted file mode 100644 index fd78ad60d14..00000000000 --- a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2019 Vasily Khoruzhick - */ - -#include -#include -#include -#include -#include -#include -#include - -#define GRF_IO_VSEL_BT565_SHIFT 0 -#define PMUGRF_CON0_VSEL_SHIFT 8 - -#ifdef CONFIG_MISC_INIT_R -static void setup_iodomain(void) -{ - struct rk3399_grf_regs *grf = - syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - struct rk3399_pmugrf_regs *pmugrf = - syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - - /* BT565 is in 1.8v domain */ - rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); - - /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ - rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); -} - -int rockchip_early_misc_init_r(void) -{ - setup_iodomain(); - - return 0; -} - -#endif diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 4de3d5b1c7f..d66b4a9d890 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -52,6 +52,7 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y From 9a5d889f6b92823089a3b445393b1beb0230c3b3 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 12 Mar 2024 23:36:17 +0000 Subject: [PATCH 65/91] rockchip: pine64: pinebook-pro: Migrate to use IO-domain driver Switch to use the IO-domain driver to configure IO-domain based on device tree instead of a setup_iodomain() function. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- board/pine64/pinebook-pro-rk3399/Makefile | 1 - .../pinebook-pro-rk3399/pinebook-pro-rk3399.c | 39 ------------------- configs/pinebook-pro-rk3399_defconfig | 1 + 3 files changed, 1 insertion(+), 40 deletions(-) delete mode 100644 board/pine64/pinebook-pro-rk3399/Makefile delete mode 100644 board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c diff --git a/board/pine64/pinebook-pro-rk3399/Makefile b/board/pine64/pinebook-pro-rk3399/Makefile deleted file mode 100644 index 2f692a12a67..00000000000 --- a/board/pine64/pinebook-pro-rk3399/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y += pinebook-pro-rk3399.o diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c deleted file mode 100644 index 0001022c62a..00000000000 --- a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * (C) Copyright 2020 Peter Robinson - */ - -#include -#include -#include -#include -#include -#include -#include - -#define GRF_IO_VSEL_BT565_SHIFT 0 -#define PMUGRF_CON0_VSEL_SHIFT 8 - -#ifdef CONFIG_MISC_INIT_R -static void setup_iodomain(void) -{ - struct rk3399_grf_regs *grf = - syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - struct rk3399_pmugrf_regs *pmugrf = - syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - - /* BT565 is in 1.8v domain */ - rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); - - /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ - rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); -} - -int rockchip_early_misc_init_r(void) -{ - setup_iodomain(); - - return 0; -} -#endif diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 57e614c314e..23ac24a0bff 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -49,6 +49,7 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_SPL_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y From 5566f3a207d7c26b684fb084d7166ce74626584e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 12 Mar 2024 23:36:18 +0000 Subject: [PATCH 66/91] rockchip: pine64: pinephone-pro: Migrate to use IO-domain driver Switch to use the IO-domain driver to configure IO-domain based on device tree instead of a setup_iodomain() function. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- board/pine64/pinephone-pro-rk3399/Makefile | 1 - .../pinephone-pro-rk3399.c | 42 ------------------- configs/pinephone-pro-rk3399_defconfig | 1 + 3 files changed, 1 insertion(+), 43 deletions(-) delete mode 100644 board/pine64/pinephone-pro-rk3399/Makefile delete mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile deleted file mode 100644 index 8d9203053e5..00000000000 --- a/board/pine64/pinephone-pro-rk3399/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y += pinephone-pro-rk3399.o diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c deleted file mode 100644 index 06dc512c57d..00000000000 --- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * (C) Copyright 2022 Peter Robinson - */ - -#include -#include -#include -#include -#include -#include -#include - -#define GRF_IO_VSEL_BT565_GPIO2AB 1 -#define GRF_IO_VSEL_AUDIO_GPIO3D4A 2 -#define PMUGRF_CON0_VSEL_SHIFT 8 - -#ifdef CONFIG_MISC_INIT_R -static void setup_iodomain(void) -{ - struct rk3399_grf_regs *grf = - syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - struct rk3399_pmugrf_regs *pmugrf = - syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - - /* BT565 is in 1.8v domain */ - rk_setreg(&grf->io_vsel, - GRF_IO_VSEL_BT565_GPIO2AB | GRF_IO_VSEL_AUDIO_GPIO3D4A); - - /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ - rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); -} - -int rockchip_early_misc_init_r(void) -{ - setup_iodomain(); - - return 0; - -} -#endif diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index 49d3d0456b5..8c6323f6c51 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -48,6 +48,7 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y From 3bf3d816c67cd8f97d2c6ad33236f4f063005b8c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 12 Mar 2024 23:36:19 +0000 Subject: [PATCH 67/91] rockchip: vamrs: rock960: Migrate to use IO-domain driver Switch to use the IO-domain driver to configure IO-domain based on device tree instead of a setup_iodomain() function. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- board/vamrs/rock960_rk3399/Makefile | 6 ----- board/vamrs/rock960_rk3399/rock960-rk3399.c | 27 --------------------- configs/ficus-rk3399_defconfig | 1 + configs/rock960-rk3399_defconfig | 1 + 4 files changed, 2 insertions(+), 33 deletions(-) delete mode 100644 board/vamrs/rock960_rk3399/Makefile delete mode 100644 board/vamrs/rock960_rk3399/rock960-rk3399.c diff --git a/board/vamrs/rock960_rk3399/Makefile b/board/vamrs/rock960_rk3399/Makefile deleted file mode 100644 index 6c3e475b3a8..00000000000 --- a/board/vamrs/rock960_rk3399/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2018 Manivannan Sadhasivam -# - -obj-y += rock960-rk3399.o diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c deleted file mode 100644 index 876be8ed9e1..00000000000 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Manivannan Sadhasivam - */ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - struct rk3399_grf_regs *grf = - syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - - /** - * Some SSD's to work on rock960 would require explicit - * domain voltage change, so BT565 is in 1.8v domain - */ - rk_setreg(&grf->io_vsel, BIT(0)); - - return 0; -} -#endif diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 90b07d847cc..4859042d6b5 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 5c0b95f10bd..13575c58005 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y From 95a9cb3666c4a513d03a64b7233ab32bfb042f0a Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 12 Mar 2024 23:36:20 +0000 Subject: [PATCH 68/91] rockchip: theobroma-systems: puma: Migrate to use IO-domain driver Switch to use the IO-domain driver to configure IO-domain based on device tree instead of a setup_iodomain() function. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- .../puma_rk3399/puma-rk3399.c | 21 ------------------- configs/puma-rk3399_defconfig | 1 + 2 files changed, 1 insertion(+), 21 deletions(-) diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 8b998ef4556..eeb8a99231e 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -3,31 +3,10 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ -#include -#include -#include -#include -#include -#include #include "../common/common.h" -static void setup_iodomain(void) -{ - const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3; - struct rk3399_grf_regs *grf = - syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - - /* - * Set bit 3 in GRF_IO_VSEL so PCIE_RST# works (pin GPIO4_C6). - * Linux assumes that PCIE_RST# works out of the box as it probes - * PCIe before loading the iodomain driver. - */ - rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT); -} - int rockchip_early_misc_init_r(void) { - setup_iodomain(); setup_boottargets(); return 0; diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 7e76ec5076f..c2759e1a952 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -66,6 +66,7 @@ CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y From 3330c8880c6c5c7292121d71534af31e36ca3345 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 12 Mar 2024 23:36:21 +0000 Subject: [PATCH 69/91] rockchip: google: gru: Migrate to use IO-domain driver Switch to use the IO-domain driver to configure IO-domain based on device tree instead of a setup_iodomain() function. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- board/google/gru/gru.c | 35 ------------------------------ configs/chromebook_bob_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + 3 files changed, 2 insertions(+), 35 deletions(-) diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c index 9cb3a525204..e08cb42c27e 100644 --- a/board/google/gru/gru.c +++ b/board/google/gru/gru.c @@ -3,18 +3,9 @@ * Copyright 2018 Google */ -#include #include #include -#include #include -#include -#include - -#define GRF_IO_VSEL_BT656_SHIFT 0 -#define GRF_IO_VSEL_AUDIO_SHIFT 1 -#define PMUGRF_CON0_VSEL_SHIFT 8 -#define PMUGRF_CON0_VOL_SHIFT 9 #ifdef CONFIG_SPL_BUILD /* provided to defeat compiler optimisation in board_init_f() */ @@ -63,29 +54,3 @@ int board_early_init_r(void) return 0; } #endif - -static void setup_iodomain(void) -{ - struct rk3399_grf_regs *grf = - syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - struct rk3399_pmugrf_regs *pmugrf = - syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - - /* BT656 and audio is in 1.8v domain */ - rk_setreg(&grf->io_vsel, (1 << GRF_IO_VSEL_BT656_SHIFT | - 1 << GRF_IO_VSEL_AUDIO_SHIFT)); - - /* - * Set GPIO1 1.8v/3.0v source select to PMU1830_VOL - * and explicitly configure that PMU1830_VOL to be 1.8V - */ - rk_setreg(&pmugrf->soc_con0, (1 << PMUGRF_CON0_VSEL_SHIFT | - 1 << PMUGRF_CON0_VOL_SHIFT)); -} - -int rockchip_early_misc_init_r(void) -{ - setup_iodomain(); - - return 0; -} diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 989a8211f64..d0321948697 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -66,6 +66,7 @@ CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_I2C_MUX=y CONFIG_CROS_EC_KEYB=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 07a96aa1898..120c11c0497 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -67,6 +67,7 @@ CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_I2C_MUX=y CONFIG_CROS_EC_KEYB=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y From ac58c6f3aa6b5ba6b0c2e226f6349b3480dfdc9e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 12 Mar 2024 23:36:22 +0000 Subject: [PATCH 70/91] rockchip: board: Move gpt_capsule_update_setup() call Move the call to gpt_capsule_update_setup() from the weak function rk_board_late_init() into the main board_late_init() function. Also change to use IS_ENABLED() instead for defined(). Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/board.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 31a11110f44..e9cfba75663 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -34,7 +34,7 @@ #include #include -#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) #define DFU_ALT_BUF_LEN SZ_1K @@ -185,10 +185,6 @@ static void gpt_capsule_update_setup(void) __weak int rk_board_late_init(void) { -#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) - gpt_capsule_update_setup(); -#endif - return 0; } @@ -196,6 +192,10 @@ int board_late_init(void) { setup_boot_mode(); +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) + gpt_capsule_update_setup(); +#endif + return rk_board_late_init(); } From c8545d2bba368feaf317d17df08ab5d780b27326 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 5 Feb 2024 12:58:52 -0600 Subject: [PATCH 71/91] arm: dts: rockchip: rk3566: Remove unnecessary clks from rgxx3 Remove unnecessary clock frequency defines from the RGxx3 u-boot dts. Move the necessary defines to the RGxx3 main dts file. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 31 ------------------- arch/arm/dts/rk3566-anbernic-rgxx3.dts | 7 +++++ 2 files changed, 7 insertions(+), 31 deletions(-) diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi index fa3df73c33d..791f16b206f 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi @@ -14,37 +14,6 @@ }; }; -&cru { - assigned-clocks = - <&pmucru CLK_RTC_32K>, - <&pmucru PLL_PPLL>, - <&pmucru PCLK_PMU>, <&cru PLL_CPLL>, - <&cru PLL_GPLL>, - <&cru ACLK_BUS>, <&cru PCLK_BUS>, - <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, - <&cru HCLK_TOP>, <&cru PCLK_TOP>, - <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>, - <&cru CPLL_500M>, <&cru CPLL_333M>, - <&cru CPLL_250M>, <&cru CPLL_125M>, - <&cru CPLL_100M>, <&cru CPLL_62P5M>, - <&cru CPLL_50M>, <&cru CPLL_25M>; - assigned-clock-rates = - <32768>, - <200000000>, - <100000000>, <1000000000>, - <1188000000>, - <150000000>, <100000000>, - <500000000>, <400000000>, - <150000000>, <100000000>, - <300000000>, <150000000>, - <500000000>, <333333333>, - <250000000>, <125000000>, - <100000000>, <62500000>, - <50000000>, <25000000>; - assigned-clock-parents = - <&pmucru CLK_RTC32K_FRAC>; -}; - &dsi_dphy0 { status = "okay"; }; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts index 404dddfafbf..9e0aa9e63b8 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts @@ -16,3 +16,10 @@ "anbernic,rg353v", "anbernic,rg353vs", "anbernic,rg503", "rockchip,rk3566"; }; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, + <200000000>, <241500000>; +}; From b7202ebcebe1d70de522831a5b6c8ce063629d90 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 5 Feb 2024 12:58:53 -0600 Subject: [PATCH 72/91] board: rockchip: Add support for Powkiddy RGB10MAX3 Add support to the RGxx3 device for the Powkiddy RGB10MAX3. This device is extremely similar to all the other devices and can use the same bootloader with the same detection logic. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- arch/arm/dts/rk3566-anbernic-rgxx3.dts | 9 ++++++--- board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 8 ++++++++ doc/board/anbernic/rgxx3.rst | 1 + 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts index 9e0aa9e63b8..c393c8d07af 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts @@ -12,9 +12,12 @@ * set the correct dtb name for loading mainline Linux automatically. */ model = "RGXX3"; - compatible = "anbernic,rg353m", "anbernic,rg353p", - "anbernic,rg353v", "anbernic,rg353vs", - "anbernic,rg503", "rockchip,rk3566"; + compatible = "anbernic,rg-arc-d", "anbernic,rg-arc-s", + "anbernic,rg353m", "anbernic,rg353p", + "anbernic,rg353ps", "anbernic,rg353v", + "anbernic,rg353vs", "anbernic,rg503", + "powkiddy,rgb10max3", "powkiddy,rgb30", + "powkiddy,rk2023", "rockchip,rk3566"; }; &cru { diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c index d05502f67af..5c57b902d14 100644 --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c @@ -50,6 +50,7 @@ enum rgxx3_device_id { RGB30, RK2023, RGARCD, + RGB10MAX3, /* Devices with duplicate ADC value */ RG353PS, RG353VS, @@ -107,6 +108,13 @@ static const struct rg3xx_model rg3xx_model_details[] = { .fdtfile = DTB_DIR "rk3566-anbernic-rg-arc-d.dtb", .detect_panel = 0, }, + [RGB10MAX3] = { + .adc_value = 765, /* Observed average from device */ + .board = "rk3566-powkiddy-rgb10max3", + .board_name = "Powkiddy RGB10MAX3", + .fdtfile = DTB_DIR "rk3566-powkiddy-rgb10max3.dtb", + .detect_panel = 0, + }, /* Devices with duplicate ADC value */ [RG353PS] = { .adc_value = 860, /* Observed average from device */ diff --git a/doc/board/anbernic/rgxx3.rst b/doc/board/anbernic/rgxx3.rst index d159ed2f762..1e63e6951e2 100644 --- a/doc/board/anbernic/rgxx3.rst +++ b/doc/board/anbernic/rgxx3.rst @@ -17,6 +17,7 @@ This allows U-Boot to boot the following Anbernic devices: Additionally, the following very similar non-Anbernic devices are also supported: + - Powkiddy RGB10MAX3 - Powkiddy RGB30 - Powkiddy RK2023 From 61177bead95d366d3155722eb52db8077829579c Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 5 Feb 2024 12:58:54 -0600 Subject: [PATCH 73/91] configs: Remove unnecessary options from RGxx3 config Based on feedback from the mailing list while adding support for a new device (the Powkiddy X55), correct the config options for the RGxx3 as well to remove unnecessary drivers and increase the SPL stack size. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- configs/anbernic-rgxx3-rk3566_defconfig | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig index 2b484fcaef5..c8c9238f96f 100644 --- a/configs/anbernic-rgxx3-rk3566_defconfig +++ b/configs/anbernic-rgxx3-rk3566_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3" CONFIG_ROCKCHIP_RK3568=y @@ -16,7 +17,9 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb" @@ -24,10 +27,11 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_RNG_SEED=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_CMD_PWM=y CONFIG_CMD_GPT=y @@ -37,8 +41,10 @@ CONFIG_CMD_MMC=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y # CONFIG_NET is not set +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -54,13 +60,13 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y +CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y -CONFIG_DM_REGULATOR_SCMI=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set @@ -76,5 +82,6 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_DW_MIPI=y CONFIG_VIDEO_BRIDGE=y CONFIG_REGEX=y +# CONFIG_RSA is not set CONFIG_ERRNO_STR=y # CONFIG_EFI_LOADER is not set From 41a60d0e5cef54a59596a58940fa7c9cf071034b Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 5 Feb 2024 12:58:55 -0600 Subject: [PATCH 74/91] board: rockchip: Add early ADC button detect for RGxx3 Add ADC button detect for early SPL stage for RGxx3 device. This is important because on at least the RG353P and RG353V a clk pin is not exposed that would allow us to take the eMMC out of the boot path. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c index 5c57b902d14..099eea60c39 100644 --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c @@ -6,12 +6,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -19,6 +21,8 @@ #include #include +#define BOOT_BROM_DOWNLOAD 0xef08a53c + #define GPIO0_BASE 0xfdd60000 #define GPIO4_BASE 0xfe770000 #define GPIO_SWPORT_DR_L 0x0000 @@ -32,6 +36,14 @@ #define GPIO_WRITEMASK(bits) ((bits) << 16) +#define SARADC_BASE 0xfe720000 +#define SARADC_DATA 0x0000 +#define SARADC_STAS 0x0004 +#define SARADC_ADC_STATUS BIT(0) +#define SARADC_CTRL 0x0008 +#define SARADC_INPUT_SRC_MSK 0x7 +#define SARADC_POWER_CTRL BIT(3) + #define DTB_DIR "rockchip/" struct rg3xx_model { @@ -157,12 +169,64 @@ static const struct rg353_panel rg353_panel_details[] = { }, }; +/* + * The device has internal eMMC, and while some devices have an exposed + * clk pin you can ground to force a bypass not all devices do. As a + * result it may be possible for some devices to become a perma-brick + * if a corrupted TPL or SPL stage with a valid header is flashed to + * the internal eMMC. Add functionality to read ADC channel 0 (the func + * button) as early as possible in the boot process to provide some + * protection against this. If we ever get an open TPL stage, we should + * consider moving this function there. + */ +void read_func_button(void) +{ + int ret; + u32 reg; + + /* Turn off SARADC to reset it. */ + writel(0, (SARADC_BASE + SARADC_CTRL)); + + /* Enable channel 0 and power on SARADC. */ + writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL), + (SARADC_BASE + SARADC_CTRL)); + + /* + * Wait for data to be ready. Use timeout of 20000us from + * rockchip_saradc driver. + */ + ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg, + !(reg & SARADC_ADC_STATUS), 20000); + if (ret) { + printf("ADC Timeout"); + return; + } + + /* Read the data from the SARADC. */ + reg = readl((SARADC_BASE + SARADC_DATA)); + + /* Turn the SARADC back off so it's ready to be used again. */ + writel(0, (SARADC_BASE + SARADC_CTRL)); + + /* + * If the value is less than 30 the button is being pressed. + * Reset the device back into Rockchip download mode. + */ + if (reg <= 30) { + printf("download key pressed, entering download mode..."); + writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); + do_reset(NULL, 0, 0, NULL); + } +}; + /* * Start LED very early so user knows device is on. Set color * to red. */ void spl_board_init(void) { + read_func_button(); + /* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */ writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \ (GPIO_C7 | GPIO_C6 | GPIO_C5), From 3b95c03d5706255f39a8f1a0fa02045d4fd981df Mon Sep 17 00:00:00 2001 From: Ben Wolsieffer Date: Thu, 7 Mar 2024 22:00:51 -0500 Subject: [PATCH 75/91] rockchip: load env from boot MMC device Currently, if the environment is stored on an MMC device, the device number is hardcoded by CONFIG_SYS_MMC_ENV_DEV. This is problematic because many boards can choose between booting from an SD card or a removable eMMC. For example, the Rock64 defconfig sets CONFIG_SYS_MMC_ENV_DEV=1, which corresponds to the SD card. If an eMMC is used as the boot device and no SD card is installed, it is impossible to save the environment. To avoid this problem, we can choose the environment MMC device based on the boot device. The theobroma-systems boards already contain code to do this, so this commit simply moves it to the common Rockchip board file, with some refactoring. I also removed another implementation of mmc_get_env_dev() from tinker_rk3288 that performed MMC boot device detection by reading a bootrom register. This has been tested on a Rock64v2. Signed-off-by: Ben Wolsieffer Reviewed-by: Quentin Schulz --- arch/arm/mach-rockchip/board.c | 31 ++++++++++++++++++++ board/rockchip/tinker_rk3288/tinker-rk3288.c | 12 -------- board/theobroma-systems/common/common.c | 30 ------------------- 3 files changed, 31 insertions(+), 42 deletions(-) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index e9cfba75663..cd226844b63 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -503,3 +504,33 @@ __weak int board_rng_seed(struct abuf *buf) return 0; } #endif + +int mmc_get_env_dev(void) +{ + int devnum; + const char *boot_device; + struct udevice *dev; + +#ifdef CONFIG_SYS_MMC_ENV_DEV + devnum = CONFIG_SYS_MMC_ENV_DEV; +#else + devnum = 0; +#endif + + boot_device = ofnode_read_chosen_string("u-boot,spl-boot-device"); + if (!boot_device) { + debug("%s: /chosen/u-boot,spl-boot-device not set\n", __func__); + return devnum; + } + + debug("%s: booted from %s\n", __func__, boot_device); + + if (uclass_find_device_by_ofnode(UCLASS_MMC, ofnode_path(boot_device), &dev)) { + debug("%s: no U-Boot device found for %s\n", __func__, boot_device); + return devnum; + } + + devnum = dev->seq_; + debug("%s: get MMC env from mmc%d\n", __func__, devnum); + return devnum; +} diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c index f85209c6498..eff3a00c30a 100644 --- a/board/rockchip/tinker_rk3288/tinker-rk3288.c +++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c @@ -11,8 +11,6 @@ #include #include #include -#include -#include static int get_ethaddr_from_eeprom(u8 *addr) { @@ -38,13 +36,3 @@ int rk3288_board_late_init(void) return 0; } - -int mmc_get_env_dev(void) -{ - u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); - - if (bootdevice_brom_id == BROM_BOOTSOURCE_EMMC) - return 0; - - return 1; -} diff --git a/board/theobroma-systems/common/common.c b/board/theobroma-systems/common/common.c index 864bcdd46f8..585da438845 100644 --- a/board/theobroma-systems/common/common.c +++ b/board/theobroma-systems/common/common.c @@ -89,36 +89,6 @@ int setup_boottargets(void) return 0; } -int mmc_get_env_dev(void) -{ - const char *boot_device = - ofnode_read_chosen_string("u-boot,spl-boot-device"); - struct udevice *devp; - - if (!boot_device) { - debug("%s: /chosen/u-boot,spl-boot-device not set\n", - __func__); -#ifdef CONFIG_SYS_MMC_ENV_DEV - return CONFIG_SYS_MMC_ENV_DEV; -#else - return 0; -#endif - } - - debug("%s: booted from %s\n", __func__, boot_device); - - if (uclass_find_device_by_ofnode(UCLASS_MMC, ofnode_path(boot_device), &devp)) -#ifdef CONFIG_SYS_MMC_ENV_DEV - return CONFIG_SYS_MMC_ENV_DEV; -#else - return 0; -#endif - - debug("%s: get MMC ENV from mmc%d\n", __func__, devp->seq_); - - return devp->seq_; -} - enum env_location arch_env_get_location(enum env_operation op, int prio) { const char *boot_device = From 3de8f45e6f2f94f4cd11a9cbc78ba1828ce639da Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:14 +0100 Subject: [PATCH 76/91] rockchip: spi: rk_spi: do not write bytes when in read-only mode The read-only mode is currently supported but only for 16b-aligned buffers. For unaligned buffers, the last byte will be read in RW mode right now, which isn't what is desired. Instead, let's put the controller back into RO mode for that last byte and skip any write in the xfer loop. This is required for 3-wire SPI mode where PICO/POCI lanes are shorted on HW level. This incidentally the recommended design for RK806 PMIC for RK3588 products. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/spi/rk_spi.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 7de943356ad..c8694fdff95 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -453,8 +453,17 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, * case of read-only transfers by using the full 16bits of each * FIFO element. */ - if (!out) + if (!out) { ret = rockchip_spi_16bit_reader(dev, &in, &len); + /* + * If "in" isn't 16b-aligned, we need to send the last byte + * ourselves. We however need to have the controller in RO mode + * which differs from the default. + */ + clrsetbits_le32(®s->ctrlr0, + TMOD_MASK << TMOD_SHIFT, + TMOD_RO << TMOD_SHIFT); + } /* This is the original 8bit reader/writer code */ while (len > 0) { @@ -465,12 +474,13 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, rkspi_enable_chip(regs, true); toread = todo; - towrite = todo; + /* Only write if we have something to write */ + towrite = out ? todo : 0; while (toread || towrite) { u32 status = readl(®s->sr); if (towrite && !(status & SR_TF_FULL)) { - writel(out ? *out++ : 0, regs->txdr); + writel(*out++, regs->txdr); towrite--; } if (toread && !(status & SR_RF_EMPT)) { @@ -501,6 +511,10 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, spi_cs_deactivate(dev, slave_plat->cs); rkspi_enable_chip(regs, false); + if (!out) + clrsetbits_le32(®s->ctrlr0, + TMOD_MASK << TMOD_SHIFT, + TMOD_TR << TMOD_SHIFT); return ret; } From 811323ffd460ce6e54846c872df1ea157adf5ea8 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:15 +0100 Subject: [PATCH 77/91] regulator: rk8xx: remove unused functions Those two functions had their last user removed in commit f9c68a566c4d ("rockchip: phycore_rk3288: remove phycore_init() function") part of v2023.01 release, so let's do some cleanup here. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/power/regulator/rk8xx.c | 31 ------------------------------- include/power/rk8xx_pmic.h | 2 -- 2 files changed, 33 deletions(-) diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index e80bd6c3723..97d73ac95e0 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -210,14 +210,6 @@ static const struct rk8xx_reg_info rk818_ldo[] = { }; #endif -static const u16 rk818_chrg_cur_input_array[] = { - 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 -}; - -static const uint rk818_chrg_shutdown_vsel_array[] = { - 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000 -}; - static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, int num, int uvolt) { @@ -1160,26 +1152,3 @@ int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt) return _buck_set_enable(pmic, buck, true); } - -int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma) -{ - uint i; - - for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++) - if (current_ma <= rk818_chrg_cur_input_array[i]) - break; - - return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i); -} - -int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt) -{ - uint i; - - for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++) - if (uvolt <= rk818_chrg_shutdown_vsel_array[i]) - break; - - return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, - i); -} diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h index 3cbfc021956..0db82419d4f 100644 --- a/include/power/rk8xx_pmic.h +++ b/include/power/rk8xx_pmic.h @@ -233,7 +233,5 @@ struct rk8xx_priv { }; int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt); -int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma); -int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt); #endif From d771597fbbade5c45ca6e0956ec3120b2d9bdce0 Mon Sep 17 00:00:00 2001 From: William Wu Date: Thu, 14 Mar 2024 10:36:16 +0100 Subject: [PATCH 78/91] regulator: rk8xx: fix SWITCH enable on RK809 On RK809 in PMIC_POWER_ENX registers, in order to set or clear a bit N, the bit at offset N + 4 needs to be set otherwise nothing is done. This fixes the inability to modify the SWITCH state on RK809. Cc: Quentin Schulz Signed-off-by: William Wu [reworded commit log] Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/power/regulator/rk8xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index 97d73ac95e0..e905df3a800 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -901,7 +901,7 @@ static int switch_set_enable(struct udevice *dev, bool enable) case RK809_ID: mask = (1 << (sw + 2)) | (1 << (sw + 6)); ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask, - enable ? mask : 0); + enable ? mask : (1 << (sw + 6))); break; case RK818_ID: mask = 1 << 6; From f047e4ab97629848963c6266bd8d3437491c651d Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:17 +0100 Subject: [PATCH 79/91] regulator: rk8xx: add indirection level for some ldo callbacks By passing a rk8xx_reg_info directly to the internal get_value, it'd be possible to call this same function with a logic for getting the rk8xx_reg_info different from the current get_ldo_reg, e.g. for NLDO and PLDO support for RK806. No logic change is expected. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/power/regulator/rk8xx.c | 48 ++++++++++++++++++++++++--------- 1 file changed, 36 insertions(+), 12 deletions(-) diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index e905df3a800..212bb752a76 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -780,10 +780,8 @@ static int buck_get_enable(struct udevice *dev) return _buck_get_enable(dev->parent, buck); } -static int ldo_get_value(struct udevice *dev) +static int _ldo_get_value(struct udevice *dev, const struct rk8xx_reg_info *info) { - int ldo = dev->driver_data - 1; - const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); int mask = info->vsel_mask; int ret, val; @@ -797,10 +795,16 @@ static int ldo_get_value(struct udevice *dev) return info->min_uv + val * info->step_uv; } -static int ldo_set_value(struct udevice *dev, int uvolt) +static int ldo_get_value(struct udevice *dev) { int ldo = dev->driver_data - 1; - const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); + const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); + + return _ldo_get_value(dev, info); +} + +static int _ldo_set_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt) +{ int mask = info->vsel_mask; int val; @@ -812,16 +816,22 @@ static int ldo_set_value(struct udevice *dev, int uvolt) else val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; - debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", - __func__, uvolt, ldo + 1, info->vsel_reg, mask, val); + debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n", + __func__, uvolt, info->vsel_reg, mask, val); return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); } -static int ldo_set_suspend_value(struct udevice *dev, int uvolt) +static int ldo_set_value(struct udevice *dev, int uvolt) { int ldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); + + return _ldo_set_value(dev, info, uvolt); +} + +static int _ldo_set_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt) +{ int mask = info->vsel_mask; int val; @@ -833,16 +843,22 @@ static int ldo_set_suspend_value(struct udevice *dev, int uvolt) else val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; - debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", - __func__, uvolt, ldo + 1, info->vsel_sleep_reg, mask, val); + debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n", + __func__, uvolt, info->vsel_sleep_reg, mask, val); return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); } -static int ldo_get_suspend_value(struct udevice *dev) +static int ldo_set_suspend_value(struct udevice *dev, int uvolt) { int ldo = dev->driver_data - 1; - const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); + const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); + + return _ldo_set_suspend_value(dev->parent, info, uvolt); +} + +static int _ldo_get_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info) +{ int mask = info->vsel_mask; int val, ret; @@ -858,6 +874,14 @@ static int ldo_get_suspend_value(struct udevice *dev) return info->min_uv + val * info->step_uv; } +static int ldo_get_suspend_value(struct udevice *dev) +{ + int ldo = dev->driver_data - 1; + const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); + + return _ldo_get_suspend_value(dev->parent, info); +} + static int ldo_set_enable(struct udevice *dev, bool enable) { int ldo = dev->driver_data - 1; From f172575d92cdb53b0f7b99bc76d9d6d09dbbbb8b Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:18 +0100 Subject: [PATCH 80/91] power: rk8xx: add support for RK806 This adds support for RK806, only the SPI variant has been tested. The communication "protocol" over SPI is the following: - write three bytes: - 1 byte: [0:3] length of the payload, [6] Enable CRC, [7] Write - 1 byte: LSB register address - 1 byte: MSB register address - write/read length of payload The CRC is always disabled for now. The RK806 technically supports I2C as well, and this should be able to support it without any change, but it wasn't tested. The DT node name prefix for the buck converters has changed in the Device Tree and is now dcdc-reg. The logic for buck converters is however manageable within the current logic inside the rk8xx regulator driver. The same cannot be said for the NLDO and PLDO. Because pmic_bind_children() parses the DT nodes and extracts the LDO index from the DT node name, NLDO and PLDO will have overlapping indices. Therefore, we need a separate logic from the already-existing ldo callbacks. Let's reuse as much as possible though. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/power/pmic/rk8xx.c | 91 ++++++ drivers/power/regulator/rk8xx.c | 514 +++++++++++++++++++++++++++++++- include/power/rk8xx_pmic.h | 19 ++ 3 files changed, 622 insertions(+), 2 deletions(-) diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 4e3a17337ee..3a8261d1749 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -9,8 +9,10 @@ #include #include #include +#include #include #include +#include #include static int rk8xx_sysreset_request(struct udevice *dev, enum sysreset_t type) @@ -32,6 +34,10 @@ static int rk8xx_sysreset_request(struct udevice *dev, enum sysreset_t type) pmic_clrsetbits(dev->parent, RK817_REG_SYS_CFG3, 0, BIT(0)); break; + case RK806_ID: + pmic_clrsetbits(dev->parent, RK806_REG_SYS_CFG3, 0, + BIT(0)); + break; default: printf("Unknown PMIC RK%x: Cannot shutdown\n", priv->variant); @@ -83,6 +89,11 @@ void rk8xx_off_for_plugin(struct udevice *dev) } } +static struct reg_data rk806_init_reg[] = { + /* RST_FUN */ + { RK806_REG_SYS_CFG3, GENMASK(7, 6), BIT(7)}, +}; + static struct reg_data rk817_init_reg[] = { /* enable the under-voltage protection, * the under-voltage protection will shutdown the LDO3 and reset the PMIC @@ -92,7 +103,10 @@ static struct reg_data rk817_init_reg[] = { static const struct pmic_child_info pmic_children_info[] = { { .prefix = "DCDC_REG", .driver = "rk8xx_buck"}, + { .prefix = "dcdc-reg", .driver = "rk8xx_buck"}, { .prefix = "LDO_REG", .driver = "rk8xx_ldo"}, + { .prefix = "nldo-reg", .driver = "rk8xx_nldo"}, + { .prefix = "pldo-reg", .driver = "rk8xx_pldo"}, { .prefix = "SWITCH_REG", .driver = "rk8xx_switch"}, { }, }; @@ -102,11 +116,51 @@ static int rk8xx_reg_count(struct udevice *dev) return RK808_NUM_OF_REGS; } +#if CONFIG_IS_ENABLED(SPI) && CONFIG_IS_ENABLED(DM_SPI) +struct rk806_cmd { + uint8_t len: 4; /* Payload size in bytes - 1 */ + uint8_t reserved: 2; + uint8_t crc_en: 1; + uint8_t op: 1; /* READ=0; WRITE=1; */ + uint8_t reg_l; +#define REG_L_MASK GENMASK(7, 0) + uint8_t reg_h; +#define REG_H_MASK GENMASK(15, 8) +}; +#endif + static int rk8xx_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { int ret; +#if CONFIG_IS_ENABLED(SPI) && CONFIG_IS_ENABLED(DM_SPI) + if (device_get_uclass_id(dev->parent) == UCLASS_SPI) { + struct spi_slave *spi = dev_get_parent_priv(dev); + struct rk806_cmd cmd = { + .op = 1, + .len = len - 1, + .reg_l = FIELD_GET(REG_L_MASK, reg), + .reg_h = FIELD_GET(REG_H_MASK, reg), + }; + + ret = dm_spi_claim_bus(dev); + if (ret) { + debug("Couldn't claim bus for device: %p!\n", dev); + return ret; + } + + ret = spi_write_then_read(spi, (u8 *)&cmd, sizeof(cmd), buff, NULL, len); + if (ret) + debug("write error to device: %p register: %#x!\n", + dev, reg); + + dm_spi_release_bus(dev); + + return ret; + } +#endif + ret = dm_i2c_write(dev, reg, buff, len); if (ret) { debug("write error to device: %p register: %#x!\n", dev, reg); @@ -120,6 +174,33 @@ static int rk8xx_read(struct udevice *dev, uint reg, uint8_t *buff, int len) { int ret; +#if CONFIG_IS_ENABLED(SPI) && CONFIG_IS_ENABLED(DM_SPI) + if (device_get_uclass_id(dev->parent) == UCLASS_SPI) { + struct spi_slave *spi = dev_get_parent_priv(dev); + struct rk806_cmd cmd = { + .op = 0, + .len = len - 1, + .reg_l = FIELD_GET(REG_L_MASK, reg), + .reg_h = FIELD_GET(REG_H_MASK, reg), + }; + + ret = dm_spi_claim_bus(dev); + if (ret) { + debug("Couldn't claim bus for device: %p!\n", dev); + return ret; + } + + ret = spi_write_then_read(spi, (u8 *)&cmd, sizeof(cmd), NULL, buff, len); + if (ret) + debug("read error to device: %p register: %#x!\n", + dev, reg); + + dm_spi_release_bus(dev); + + return ret; + } +#endif + ret = dm_i2c_read(dev, reg, buff, len); if (ret) { debug("read error from device: %p register: %#x!\n", dev, reg); @@ -181,6 +262,9 @@ static int rk8xx_probe(struct udevice *dev) device_is_compatible(dev, "rockchip,rk809")) { id_msb = RK817_ID_MSB; id_lsb = RK817_ID_LSB; + } else if (device_is_compatible(dev, "rockchip,rk806")) { + id_msb = RK806_ID_MSB; + id_lsb = RK806_ID_LSB; } else { id_msb = ID_MSB; id_lsb = ID_LSB; @@ -221,6 +305,12 @@ static int rk8xx_probe(struct udevice *dev) value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4); pmic_reg_write(dev, RK817_POWER_EN_SAVE1, value); break; + case RK806_ID: + on_source = RK806_ON_SOURCE; + off_source = RK806_OFF_SOURCE; + init_data = rk806_init_reg; + init_data_num = ARRAY_SIZE(rk806_init_reg); + break; default: printf("Unknown PMIC: RK%x!!\n", priv->variant); return -EINVAL; @@ -263,6 +353,7 @@ static struct dm_pmic_ops rk8xx_ops = { static const struct udevice_id rk8xx_ids[] = { { .compatible = "rockchip,rk805" }, + { .compatible = "rockchip,rk806" }, { .compatible = "rockchip,rk808" }, { .compatible = "rockchip,rk809" }, { .compatible = "rockchip,rk816" }, diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index 212bb752a76..1bd4605d43a 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -25,6 +25,19 @@ #define NA 0xff /* Field Definitions */ +#define RK806_BUCK_CONFIG(n) (0x10 + (n) - 1) +#define RK806_BUCK_ON_VSEL(n) (0x1a + (n) - 1) +#define RK806_BUCK_SLP_VSEL(n) (0x24 + (n) - 1) +#define RK806_BUCK_VSEL_MASK 0xff + +#define RK806_NLDO_ON_VSEL(n) (0x43 + (n) - 1) +#define RK806_NLDO_SLP_VSEL(n) (0x48 + (n) - 1) +#define RK806_NLDO_VSEL_MASK 0xff + +#define RK806_PLDO_ON_VSEL(n) (0x4e + (n) - 1) +#define RK806_PLDO_SLP_VSEL(n) (0x54 + (n) - 1) +#define RK806_PLDO_VSEL_MASK 0xff + #define RK808_BUCK_VSEL_MASK 0x3f #define RK808_BUCK4_VSEL_MASK 0xf #define RK808_LDO_VSEL_MASK 0x1f @@ -91,6 +104,49 @@ struct rk8xx_reg_info { u8 max_sel; }; +static const struct rk8xx_reg_info rk806_buck[] = { + /* buck 1 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0x00, 0x9f }, + { 1500000, 25000, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb }, + { 3400000, 0, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xec, 0xff }, + /* buck 2 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0x00, 0x9f }, + { 1500000, 25000, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb }, + { 3400000, 0, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xec, 0xff }, + /* buck 3 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0x00, 0x9f }, + { 1500000, 25000, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb }, + { 3400000, 0, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xec, 0xff }, + /* buck 4 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0x00, 0x9f }, + { 1500000, 25000, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb }, + { 3400000, 0, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xec, 0xff }, + /* buck 5 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0x00, 0x9f }, + { 1500000, 25000, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb }, + { 3400000, 0, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xec, 0xff }, + /* buck 6 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0x00, 0x9f }, + { 1500000, 25000, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb }, + { 3400000, 0, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xec, 0xff }, + /* buck 7 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0x00, 0x9f }, + { 1500000, 25000, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb }, + { 3400000, 0, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xec, 0xff }, + /* buck 8 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0x00, 0x9f }, + { 1500000, 25000, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb }, + { 3400000, 0, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xec, 0xff }, + /* buck 9 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0x00, 0x9f }, + { 1500000, 25000, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb }, + { 3400000, 0, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xec, 0xff }, + /* buck 10 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0x00, 0x9f }, + { 1500000, 25000, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb }, + { 3400000, 0, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xec, 0xff }, +}; + static const struct rk8xx_reg_info rk808_buck[] = { { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f }, { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f }, @@ -148,6 +204,45 @@ static const struct rk8xx_reg_info rk818_buck[] = { }; #ifdef ENABLE_DRIVER +static const struct rk8xx_reg_info rk806_nldo[] = { + /* nldo 1 */ + { 500000, 12500, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0x00, 0xe7}, + { 3400000, 0, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0xe8, 0xff}, + /* nldo 2 */ + { 500000, 12500, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0x00, 0xe7}, + { 3400000, 0, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0xe8, 0xff}, + /* nldo 3 */ + { 500000, 12500, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0x00, 0xe7}, + { 3400000, 0, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0xe8, 0xff}, + /* nldo 4 */ + { 500000, 12500, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0x00, 0xe7}, + { 3400000, 0, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0xe8, 0xff}, + /* nldo 5 */ + { 500000, 12500, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0x00, 0xe7}, + { 3400000, 0, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0xe8, 0xff}, +}; + +static const struct rk8xx_reg_info rk806_pldo[] = { + /* pldo 1 */ + { 500000, 12500, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0x00, 0xe7}, + { 3400000, 0, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0xe8, 0xff}, + /* pldo 2 */ + { 500000, 12500, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0x00, 0xe7}, + { 3400000, 0, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0xe8, 0xff}, + /* pldo 3 */ + { 500000, 12500, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0x00, 0xe7}, + { 3400000, 0, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0xe8, 0xff}, + /* pldo 4 */ + { 500000, 12500, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0x00, 0xe7}, + { 3400000, 0, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0xe8, 0xff}, + /* pldo 5 */ + { 500000, 12500, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0x00, 0xe7}, + { 3400000, 0, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0xe8, 0xff}, + /* pldo 6 */ + { 500000, 12500, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0x00, 0xe7}, + { 3400000, 0, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0xe8, 0xff}, +}; + static const struct rk8xx_reg_info rk808_ldo[] = { { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, @@ -230,7 +325,12 @@ static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, default: return &rk816_buck[num + 4]; } - + case RK806_ID: + if (uvolt < 1500000) + return &rk806_buck[num * 3 + 0]; + else if (uvolt < 3400000) + return &rk806_buck[num * 3 + 1]; + return &rk806_buck[num * 3 + 2]; case RK809_ID: case RK817_ID: switch (num) { @@ -314,7 +414,11 @@ static int _buck_set_enable(struct udevice *pmic, int buck, bool enable) value = ((0 << buck) | (1 << (buck + 4))); ret = pmic_reg_write(pmic, en_reg, value); break; - + case RK806_ID: + value = RK806_POWER_EN_CLRSETBITS(buck % 4, enable); + en_reg = RK806_POWER_EN((buck + 1) / 4); + ret = pmic_reg_write(pmic, en_reg, value); + break; case RK808_ID: case RK818_ID: mask = 1 << buck; @@ -389,6 +493,10 @@ static int _buck_get_enable(struct udevice *pmic, int buck) ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1); } break; + case RK806_ID: + mask = BIT(buck % 4); + ret = pmic_reg_read(pmic, RK806_POWER_EN((buck + 1) / 4)); + break; case RK808_ID: case RK818_ID: mask = 1 << buck; @@ -428,6 +536,20 @@ static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable) ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask, enable ? mask : 0); break; + case RK806_ID: + { + u8 reg; + + if (buck + 1 >= 9) { + reg = RK806_POWER_SLP_EN1; + mask = BIT(buck + 1 - 3); + } else { + reg = RK806_POWER_SLP_EN0; + mask = BIT(buck + 1); + } + ret = pmic_clrsetbits(pmic, reg, mask, enable ? mask : 0); + } + break; case RK808_ID: case RK818_ID: mask = 1 << buck; @@ -465,6 +587,21 @@ static int _buck_get_suspend_enable(struct udevice *pmic, int buck) return val; ret = val & mask ? 1 : 0; break; + case RK806_ID: + { + u8 reg; + + if (buck + 1 >= 9) { + reg = RK806_POWER_SLP_EN1; + mask = BIT(buck + 1 - 3); + } else { + reg = RK806_POWER_SLP_EN0; + mask = BIT(buck + 1); + } + val = pmic_reg_read(pmic, reg); + } + ret = (val & mask) ? 1 : 0; + break; case RK808_ID: case RK818_ID: mask = 1 << buck; @@ -514,6 +651,34 @@ static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, } } +static const struct rk8xx_reg_info *get_nldo_reg(struct udevice *pmic, + int num, int uvolt) +{ + const struct rk8xx_priv *priv = dev_get_priv(pmic); + + switch (priv->variant) { + case RK806_ID: + default: + if (uvolt < 3400000) + return &rk806_nldo[num * 2 + 0]; + return &rk806_nldo[num * 2 + 1]; + } +} + +static const struct rk8xx_reg_info *get_pldo_reg(struct udevice *pmic, + int num, int uvolt) +{ + const struct rk8xx_priv *priv = dev_get_priv(pmic); + + switch (priv->variant) { + case RK806_ID: + default: + if (uvolt < 3400000) + return &rk806_pldo[num * 2 + 0]; + return &rk806_pldo[num * 2 + 1]; + } +} + static int _ldo_get_enable(struct udevice *pmic, int ldo) { struct rk8xx_priv *priv = dev_get_priv(pmic); @@ -561,6 +726,63 @@ static int _ldo_get_enable(struct udevice *pmic, int ldo) return ret & mask ? true : false; } +static int _nldo_get_enable(struct udevice *pmic, int nldo) +{ + struct rk8xx_priv *priv = dev_get_priv(pmic); + uint mask = 0; + int ret = 0; + u8 en_reg = 0; + + switch (priv->variant) { + case RK806_ID: + default: + if (nldo + 1 >= 5) { + mask = BIT(2); + en_reg = RK806_POWER_EN(5); + } else { + mask = BIT(nldo); + en_reg = RK806_POWER_EN(3); + } + ret = pmic_reg_read(pmic, en_reg); + break; + } + + if (ret < 0) + return ret; + + return (ret & mask) ? 1 : 0; +} + +static int _pldo_get_enable(struct udevice *pmic, int pldo) +{ + struct rk8xx_priv *priv = dev_get_priv(pmic); + uint mask = 0; + int ret = 0; + u8 en_reg = 0; + + switch (priv->variant) { + case RK806_ID: + default: + if (pldo + 1 <= 3) { + mask = BIT(pldo + 1); + en_reg = RK806_POWER_EN(4); + } else if (pldo + 1 == 6) { + mask = BIT(0); + en_reg = RK806_POWER_EN(4); + } else { + mask = BIT((pldo + 1) % 4); + en_reg = RK806_POWER_EN(5); + } + ret = pmic_reg_read(pmic, en_reg); + break; + } + + if (ret < 0) + return ret; + + return (ret & mask) ? 1 : 0; +} + static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable) { struct rk8xx_priv *priv = dev_get_priv(pmic); @@ -616,6 +838,62 @@ static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable) return ret; } +static int _nldo_set_enable(struct udevice *pmic, int nldo, bool enable) +{ + struct rk8xx_priv *priv = dev_get_priv(pmic); + uint value, en_reg; + int ret = 0; + + switch (priv->variant) { + case RK806_ID: + default: + if (nldo + 1 >= 5) { + value = RK806_POWER_EN_CLRSETBITS(2, enable); + en_reg = RK806_POWER_EN(5); + } else { + value = RK806_POWER_EN_CLRSETBITS(nldo, enable); + en_reg = RK806_POWER_EN(3); + } + ret = pmic_reg_write(pmic, en_reg, value); + break; + } + + if (enable) + udelay(500); + + return ret; +} + +static int _pldo_set_enable(struct udevice *pmic, int pldo, bool enable) +{ + struct rk8xx_priv *priv = dev_get_priv(pmic); + uint value, en_reg; + int ret = 0; + + switch (priv->variant) { + case RK806_ID: + default: + /* PLDO */ + if (pldo + 1 <= 3) { + value = RK806_POWER_EN_CLRSETBITS(pldo + 1, enable); + en_reg = RK806_POWER_EN(4); + } else if (pldo + 1 == 6) { + value = RK806_POWER_EN_CLRSETBITS(0, enable); + en_reg = RK806_POWER_EN(4); + } else { + value = RK806_POWER_EN_CLRSETBITS((pldo + 1) % 4, enable); + en_reg = RK806_POWER_EN(5); + } + ret = pmic_reg_write(pmic, en_reg, value); + break; + } + + if (enable) + udelay(500); + + return ret; +} + static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable) { struct rk8xx_priv *priv = dev_get_priv(pmic); @@ -652,6 +930,43 @@ static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable) return ret; } +static int _nldo_set_suspend_enable(struct udevice *pmic, int nldo, bool enable) +{ + struct rk8xx_priv *priv = dev_get_priv(pmic); + uint mask; + int ret = 0; + + switch (priv->variant) { + case RK806_ID: + default: + mask = BIT(nldo); + ret = pmic_clrsetbits(pmic, RK806_POWER_SLP_EN1, mask, enable ? mask : 0); + break; + } + + return ret; +} + +static int _pldo_set_suspend_enable(struct udevice *pmic, int pldo, bool enable) +{ + struct rk8xx_priv *priv = dev_get_priv(pmic); + uint mask; + int ret = 0; + + switch (priv->variant) { + case RK806_ID: + default: + if (pldo + 1 >= 6) + mask = BIT(0); + else + mask = BIT(pldo + 1); + ret = pmic_clrsetbits(pmic, RK806_POWER_SLP_EN2, mask, enable ? mask : 0); + break; + } + + return ret; +} + static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo) { struct rk8xx_priv *priv = dev_get_priv(pmic); @@ -696,6 +1011,45 @@ static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo) return ret; } +static int _nldo_get_suspend_enable(struct udevice *pmic, int nldo) +{ + struct rk8xx_priv *priv = dev_get_priv(pmic); + int val, ret = 0; + uint mask; + + switch (priv->variant) { + case RK806_ID: + default: + mask = BIT(nldo); + val = pmic_reg_read(pmic, RK806_POWER_SLP_EN1); + ret = (val & mask) ? 1 : 0; + break; + } + + return ret; +} + +static int _pldo_get_suspend_enable(struct udevice *pmic, int pldo) +{ + struct rk8xx_priv *priv = dev_get_priv(pmic); + int val, ret = 0; + uint mask; + + switch (priv->variant) { + case RK806_ID: + default: + if (pldo + 1 >= 6) + mask = BIT(0); + else + mask = BIT(pldo + 1); + val = pmic_reg_read(pmic, RK806_POWER_SLP_EN2); + ret = (val & mask) ? 1 : 0; + break; + } + + return ret; +} + static int buck_get_value(struct udevice *dev) { int buck = dev->driver_data - 1; @@ -803,6 +1157,22 @@ static int ldo_get_value(struct udevice *dev) return _ldo_get_value(dev, info); } +static int nldo_get_value(struct udevice *dev) +{ + int nldo = dev->driver_data - 1; + const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, 0); + + return _ldo_get_value(dev, info); +} + +static int pldo_get_value(struct udevice *dev) +{ + int pldo = dev->driver_data - 1; + const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, 0); + + return _ldo_get_value(dev, info); +} + static int _ldo_set_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt) { int mask = info->vsel_mask; @@ -830,6 +1200,22 @@ static int ldo_set_value(struct udevice *dev, int uvolt) return _ldo_set_value(dev, info, uvolt); } +static int nldo_set_value(struct udevice *dev, int uvolt) +{ + int nldo = dev->driver_data - 1; + const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, uvolt); + + return _ldo_set_value(dev, info, uvolt); +} + +static int pldo_set_value(struct udevice *dev, int uvolt) +{ + int pldo = dev->driver_data - 1; + const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, uvolt); + + return _ldo_set_value(dev, info, uvolt); +} + static int _ldo_set_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt) { int mask = info->vsel_mask; @@ -857,6 +1243,22 @@ static int ldo_set_suspend_value(struct udevice *dev, int uvolt) return _ldo_set_suspend_value(dev->parent, info, uvolt); } +static int nldo_set_suspend_value(struct udevice *dev, int uvolt) +{ + int nldo = dev->driver_data - 1; + const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, uvolt); + + return _ldo_set_suspend_value(dev->parent, info, uvolt); +} + +static int pldo_set_suspend_value(struct udevice *dev, int uvolt) +{ + int pldo = dev->driver_data - 1; + const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, uvolt); + + return _ldo_set_suspend_value(dev->parent, info, uvolt); +} + static int _ldo_get_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info) { int mask = info->vsel_mask; @@ -882,6 +1284,22 @@ static int ldo_get_suspend_value(struct udevice *dev) return _ldo_get_suspend_value(dev->parent, info); } +static int nldo_get_suspend_value(struct udevice *dev) +{ + int nldo = dev->driver_data - 1; + const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, 0); + + return _ldo_get_suspend_value(dev->parent, info); +} + +static int pldo_get_suspend_value(struct udevice *dev) +{ + int pldo = dev->driver_data - 1; + const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, 0); + + return _ldo_get_suspend_value(dev->parent, info); +} + static int ldo_set_enable(struct udevice *dev, bool enable) { int ldo = dev->driver_data - 1; @@ -889,6 +1307,20 @@ static int ldo_set_enable(struct udevice *dev, bool enable) return _ldo_set_enable(dev->parent, ldo, enable); } +static int nldo_set_enable(struct udevice *dev, bool enable) +{ + int nldo = dev->driver_data - 1; + + return _nldo_set_enable(dev->parent, nldo, enable); +} + +static int pldo_set_enable(struct udevice *dev, bool enable) +{ + int pldo = dev->driver_data - 1; + + return _pldo_set_enable(dev->parent, pldo, enable); +} + static int ldo_set_suspend_enable(struct udevice *dev, bool enable) { int ldo = dev->driver_data - 1; @@ -896,6 +1328,20 @@ static int ldo_set_suspend_enable(struct udevice *dev, bool enable) return _ldo_set_suspend_enable(dev->parent, ldo, enable); } +static int nldo_set_suspend_enable(struct udevice *dev, bool enable) +{ + int nldo = dev->driver_data - 1; + + return _nldo_set_suspend_enable(dev->parent, nldo, enable); +} + +static int pldo_set_suspend_enable(struct udevice *dev, bool enable) +{ + int pldo = dev->driver_data - 1; + + return _pldo_set_suspend_enable(dev->parent, pldo, enable); +} + static int ldo_get_suspend_enable(struct udevice *dev) { int ldo = dev->driver_data - 1; @@ -903,6 +1349,20 @@ static int ldo_get_suspend_enable(struct udevice *dev) return _ldo_get_suspend_enable(dev->parent, ldo); } +static int nldo_get_suspend_enable(struct udevice *dev) +{ + int nldo = dev->driver_data - 1; + + return _nldo_get_suspend_enable(dev->parent, nldo); +} + +static int pldo_get_suspend_enable(struct udevice *dev) +{ + int pldo = dev->driver_data - 1; + + return _pldo_get_suspend_enable(dev->parent, pldo); +} + static int ldo_get_enable(struct udevice *dev) { int ldo = dev->driver_data - 1; @@ -910,6 +1370,20 @@ static int ldo_get_enable(struct udevice *dev) return _ldo_get_enable(dev->parent, ldo); } +static int nldo_get_enable(struct udevice *dev) +{ + int nldo = dev->driver_data - 1; + + return _nldo_get_enable(dev->parent, nldo); +} + +static int pldo_get_enable(struct udevice *dev) +{ + int pldo = dev->driver_data - 1; + + return _pldo_get_enable(dev->parent, pldo); +} + static int switch_set_enable(struct udevice *dev, bool enable) { struct rk8xx_priv *priv = dev_get_priv(dev->parent); @@ -1133,6 +1607,28 @@ static const struct dm_regulator_ops rk8xx_ldo_ops = { .get_suspend_enable = ldo_get_suspend_enable, }; +static const struct dm_regulator_ops rk8xx_nldo_ops = { + .get_value = nldo_get_value, + .set_value = nldo_set_value, + .set_suspend_value = nldo_set_suspend_value, + .get_suspend_value = nldo_get_suspend_value, + .get_enable = nldo_get_enable, + .set_enable = nldo_set_enable, + .set_suspend_enable = nldo_set_suspend_enable, + .get_suspend_enable = nldo_get_suspend_enable, +}; + +static const struct dm_regulator_ops rk8xx_pldo_ops = { + .get_value = pldo_get_value, + .set_value = pldo_set_value, + .set_suspend_value = pldo_set_suspend_value, + .get_suspend_value = pldo_get_suspend_value, + .get_enable = pldo_get_enable, + .set_enable = pldo_set_enable, + .set_suspend_enable = pldo_set_suspend_enable, + .get_suspend_enable = pldo_get_suspend_enable, +}; + static const struct dm_regulator_ops rk8xx_switch_ops = { .get_value = switch_get_value, .set_value = switch_set_value, @@ -1158,6 +1654,20 @@ U_BOOT_DRIVER(rk8xx_ldo) = { .probe = rk8xx_ldo_probe, }; +U_BOOT_DRIVER(rk8xx_nldo) = { + .name = "rk8xx_nldo", + .id = UCLASS_REGULATOR, + .ops = &rk8xx_nldo_ops, + .probe = rk8xx_ldo_probe, +}; + +U_BOOT_DRIVER(rk8xx_pldo) = { + .name = "rk8xx_pldo", + .id = UCLASS_REGULATOR, + .ops = &rk8xx_pldo_ops, + .probe = rk8xx_ldo_probe, +}; + U_BOOT_DRIVER(rk8xx_switch) = { .name = "rk8xx_switch", .id = UCLASS_REGULATOR, diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h index 0db82419d4f..31221aa46b6 100644 --- a/include/power/rk8xx_pmic.h +++ b/include/power/rk8xx_pmic.h @@ -182,8 +182,19 @@ enum { RK816_REG_LDO_EN2, }; +enum { + RK806_POWER_SLP_EN0 = 0x06, + RK806_POWER_SLP_EN1, + RK806_POWER_SLP_EN2, + RK806_REG_SYS_CFG3 = 0x72, + RK806_WDT_REG, + RK806_ON_SOURCE, + RK806_OFF_SOURCE +}; + enum { RK805_ID = 0x8050, + RK806_ID = 0x8060, RK808_ID = 0x0000, RK809_ID = 0x8090, RK816_ID = 0x8160, @@ -201,6 +212,14 @@ enum { #define RK817_POWER_EN_SAVE0 0x99 #define RK817_POWER_EN_SAVE1 0xa4 +#define RK806_POWER_EN(x) (0x00 + (x)) +/* POWER_ENx register lower 4 bits are write-protected unless the associated top bit is set */ +#define RK806_POWER_EN_CLRSETBITS(bit, val) (((val) << (bit)) | (1 << ((bit) + 4))) + +#define RK806_POWER_SLP_EN(x) (0x06 + (x)) + +#define RK806_ID_MSB 0x5a +#define RK806_ID_LSB 0x5b #define RK817_ID_MSB 0xed #define RK817_ID_LSB 0xee #define RK8XX_ID_MSK 0xfff0 From 808156189b92be4dcbf021b1c2ad75ef3ba45c2c Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:19 +0100 Subject: [PATCH 81/91] pmic: reword help text Reword the help text for the pmic read and pmic write commands to better match what's expected from the user. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- cmd/pmic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmd/pmic.c b/cmd/pmic.c index 49a405fa297..c9e9730adf9 100644 --- a/cmd/pmic.c +++ b/cmd/pmic.c @@ -225,6 +225,6 @@ U_BOOT_CMD(pmic, CONFIG_SYS_MAXARGS, 1, do_pmic, "list - list pmic devices\n" "pmic dev [name] - show or [set] operating PMIC device\n" "pmic dump - dump registers\n" - "pmic read address - read byte of register at address\n" - "pmic write address - write byte to register at address\n" + "pmic read - read byte of 'reg' register\n" + "pmic write - write 'byte' byte to 'reg' register\n" ); From 0707bfdf233b755c7f1b5547e32ede92264790a0 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:20 +0100 Subject: [PATCH 82/91] rockchip: adc: rockchip-saradc: use union for preparing for v2 The registers are entirely different between SARADC v1 and SARADC v2, so let's prepare to add another struct for accessing v2 registers by adding a union. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/adc/rockchip-saradc.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index 03caca78b5f..4a842556a60 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -23,13 +23,16 @@ #define SARADC_TIMEOUT (100 * 1000) -struct rockchip_saradc_regs { +struct rockchip_saradc_regs_v1 { unsigned int data; unsigned int stas; unsigned int ctrl; unsigned int dly_pu_soc; }; +union rockchip_saradc_regs { + struct rockchip_saradc_regs_v1 *v1; +}; struct rockchip_saradc_data { int num_bits; int num_channels; @@ -37,7 +40,7 @@ struct rockchip_saradc_data { }; struct rockchip_saradc_priv { - struct rockchip_saradc_regs *regs; + union rockchip_saradc_regs regs; int active_channel; const struct rockchip_saradc_data *data; }; @@ -53,16 +56,16 @@ int rockchip_saradc_channel_data(struct udevice *dev, int channel, return -EINVAL; } - if ((readl(&priv->regs->ctrl) & SARADC_CTRL_IRQ_STATUS) != + if ((readl(&priv->regs.v1->ctrl) & SARADC_CTRL_IRQ_STATUS) != SARADC_CTRL_IRQ_STATUS) return -EBUSY; /* Read value */ - *data = readl(&priv->regs->data); + *data = readl(&priv->regs.v1->data); *data &= uc_pdata->data_mask; /* Power down adc */ - writel(0, &priv->regs->ctrl); + writel(0, &priv->regs.v1->ctrl); return 0; } @@ -77,11 +80,11 @@ int rockchip_saradc_start_channel(struct udevice *dev, int channel) } /* 8 clock periods as delay between power up and start cmd */ - writel(8, &priv->regs->dly_pu_soc); + writel(8, &priv->regs.v1->dly_pu_soc); /* Select the channel to be used and trigger conversion */ writel(SARADC_CTRL_POWER_CTRL | (channel & SARADC_CTRL_CHN_MASK) | - SARADC_CTRL_IRQ_ENABLE, &priv->regs->ctrl); + SARADC_CTRL_IRQ_ENABLE, &priv->regs.v1->ctrl); priv->active_channel = channel; @@ -93,7 +96,7 @@ int rockchip_saradc_stop(struct udevice *dev) struct rockchip_saradc_priv *priv = dev_get_priv(dev); /* Power down adc */ - writel(0, &priv->regs->ctrl); + writel(0, &priv->regs.v1->ctrl); priv->active_channel = -1; @@ -146,8 +149,8 @@ int rockchip_saradc_of_to_plat(struct udevice *dev) struct rockchip_saradc_data *data; data = (struct rockchip_saradc_data *)dev_get_driver_data(dev); - priv->regs = dev_read_addr_ptr(dev); - if (!priv->regs) { + priv->regs.v1 = dev_read_addr_ptr(dev); + if (!priv->regs.v1) { pr_err("Dev: %s - can't get address!", dev->name); return -EINVAL; } From 7da3065afdc810d37344dc8bda1bb74e79a742c5 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:21 +0100 Subject: [PATCH 83/91] rockchip: adc: rockchip-saradc: factor out channel_data callback SARADC v1 and v2 have a different way of reading data, therefore let's abstract this function so that it can be provided from the udevice.data pointer. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/adc/rockchip-saradc.c | 39 +++++++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index 4a842556a60..1cc57beecc2 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -37,6 +37,7 @@ struct rockchip_saradc_data { int num_bits; int num_channels; unsigned long clk_rate; + int (*channel_data)(struct udevice *dev, int channel, unsigned int *data); }; struct rockchip_saradc_priv { @@ -45,16 +46,10 @@ struct rockchip_saradc_priv { const struct rockchip_saradc_data *data; }; -int rockchip_saradc_channel_data(struct udevice *dev, int channel, - unsigned int *data) +int rockchip_saradc_channel_data_v1(struct udevice *dev, int channel, + unsigned int *data) { struct rockchip_saradc_priv *priv = dev_get_priv(dev); - struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); - - if (channel != priv->active_channel) { - pr_err("Requested channel is not active!"); - return -EINVAL; - } if ((readl(&priv->regs.v1->ctrl) & SARADC_CTRL_IRQ_STATUS) != SARADC_CTRL_IRQ_STATUS) @@ -62,7 +57,6 @@ int rockchip_saradc_channel_data(struct udevice *dev, int channel, /* Read value */ *data = readl(&priv->regs.v1->data); - *data &= uc_pdata->data_mask; /* Power down adc */ writel(0, &priv->regs.v1->ctrl); @@ -70,6 +64,30 @@ int rockchip_saradc_channel_data(struct udevice *dev, int channel, return 0; } +int rockchip_saradc_channel_data(struct udevice *dev, int channel, + unsigned int *data) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); + int ret; + + if (channel != priv->active_channel) { + pr_err("Requested channel is not active!"); + return -EINVAL; + } + + ret = priv->data->channel_data(dev, channel, data); + if (ret) { + if (ret != -EBUSY) + pr_err("Error reading channel data, %d!", ret); + return ret; + } + + *data &= uc_pdata->data_mask; + + return 0; +} + int rockchip_saradc_start_channel(struct udevice *dev, int channel) { struct rockchip_saradc_priv *priv = dev_get_priv(dev); @@ -174,18 +192,21 @@ static const struct rockchip_saradc_data saradc_data = { .num_bits = 10, .num_channels = 3, .clk_rate = 1000000, + .channel_data = rockchip_saradc_channel_data_v1, }; static const struct rockchip_saradc_data rk3066_tsadc_data = { .num_bits = 12, .num_channels = 2, .clk_rate = 50000, + .channel_data = rockchip_saradc_channel_data_v1, }; static const struct rockchip_saradc_data rk3399_saradc_data = { .num_bits = 10, .num_channels = 6, .clk_rate = 1000000, + .channel_data = rockchip_saradc_channel_data_v1, }; static const struct udevice_id rockchip_saradc_ids[] = { From 257752551229f04567ac6ddde651b407c8c74e8f Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:22 +0100 Subject: [PATCH 84/91] rockchip: adc: rockchip-saradc: factor out start_channel callback SARADC v1 and v2 have a different way of starting a channel, therefore let's abstract this function so that it can be provided from the udevice.data pointer. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/adc/rockchip-saradc.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index 1cc57beecc2..607d10b5b70 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -38,6 +38,7 @@ struct rockchip_saradc_data { int num_channels; unsigned long clk_rate; int (*channel_data)(struct udevice *dev, int channel, unsigned int *data); + int (*start_channel)(struct udevice *dev, int channel); }; struct rockchip_saradc_priv { @@ -88,15 +89,10 @@ int rockchip_saradc_channel_data(struct udevice *dev, int channel, return 0; } -int rockchip_saradc_start_channel(struct udevice *dev, int channel) +int rockchip_saradc_start_channel_v1(struct udevice *dev, int channel) { struct rockchip_saradc_priv *priv = dev_get_priv(dev); - if (channel < 0 || channel >= priv->data->num_channels) { - pr_err("Requested channel is invalid!"); - return -EINVAL; - } - /* 8 clock periods as delay between power up and start cmd */ writel(8, &priv->regs.v1->dly_pu_soc); @@ -104,6 +100,25 @@ int rockchip_saradc_start_channel(struct udevice *dev, int channel) writel(SARADC_CTRL_POWER_CTRL | (channel & SARADC_CTRL_CHN_MASK) | SARADC_CTRL_IRQ_ENABLE, &priv->regs.v1->ctrl); + return 0; +} + +int rockchip_saradc_start_channel(struct udevice *dev, int channel) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + int ret; + + if (channel < 0 || channel >= priv->data->num_channels) { + pr_err("Requested channel is invalid!"); + return -EINVAL; + } + + ret = priv->data->start_channel(dev, channel); + if (ret) { + pr_err("Error starting channel, %d!", ret); + return ret; + } + priv->active_channel = channel; return 0; @@ -193,6 +208,7 @@ static const struct rockchip_saradc_data saradc_data = { .num_channels = 3, .clk_rate = 1000000, .channel_data = rockchip_saradc_channel_data_v1, + .start_channel = rockchip_saradc_start_channel_v1, }; static const struct rockchip_saradc_data rk3066_tsadc_data = { @@ -200,6 +216,7 @@ static const struct rockchip_saradc_data rk3066_tsadc_data = { .num_channels = 2, .clk_rate = 50000, .channel_data = rockchip_saradc_channel_data_v1, + .start_channel = rockchip_saradc_start_channel_v1, }; static const struct rockchip_saradc_data rk3399_saradc_data = { @@ -207,6 +224,7 @@ static const struct rockchip_saradc_data rk3399_saradc_data = { .num_channels = 6, .clk_rate = 1000000, .channel_data = rockchip_saradc_channel_data_v1, + .start_channel = rockchip_saradc_start_channel_v1, }; static const struct udevice_id rockchip_saradc_ids[] = { From d63c57e104fd3ae37108fb4d502d41d7380770ee Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:23 +0100 Subject: [PATCH 85/91] rockchip: adc: rockchip-saradc: factor out stop callback SARADC v2 doesn't have a stop mechanism once in single mode. In series conversion, the logic is different anyway. Therefore, let's abstract this function so that it can be provided from the udevice.data pointer. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/adc/rockchip-saradc.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index 607d10b5b70..b5df58fe3eb 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -39,6 +39,7 @@ struct rockchip_saradc_data { unsigned long clk_rate; int (*channel_data)(struct udevice *dev, int channel, unsigned int *data); int (*start_channel)(struct udevice *dev, int channel); + int (*stop)(struct udevice *dev); }; struct rockchip_saradc_priv { @@ -124,13 +125,29 @@ int rockchip_saradc_start_channel(struct udevice *dev, int channel) return 0; } -int rockchip_saradc_stop(struct udevice *dev) +int rockchip_saradc_stop_v1(struct udevice *dev) { struct rockchip_saradc_priv *priv = dev_get_priv(dev); /* Power down adc */ writel(0, &priv->regs.v1->ctrl); + return 0; +} + +int rockchip_saradc_stop(struct udevice *dev) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + + if (priv->data->stop) { + int ret = priv->data->stop(dev); + + if (ret) { + pr_err("Error stopping channel, %d!", ret); + return ret; + } + } + priv->active_channel = -1; return 0; @@ -209,6 +226,7 @@ static const struct rockchip_saradc_data saradc_data = { .clk_rate = 1000000, .channel_data = rockchip_saradc_channel_data_v1, .start_channel = rockchip_saradc_start_channel_v1, + .stop = rockchip_saradc_stop_v1, }; static const struct rockchip_saradc_data rk3066_tsadc_data = { @@ -217,6 +235,7 @@ static const struct rockchip_saradc_data rk3066_tsadc_data = { .clk_rate = 50000, .channel_data = rockchip_saradc_channel_data_v1, .start_channel = rockchip_saradc_start_channel_v1, + .stop = rockchip_saradc_stop_v1, }; static const struct rockchip_saradc_data rk3399_saradc_data = { @@ -225,6 +244,7 @@ static const struct rockchip_saradc_data rk3399_saradc_data = { .clk_rate = 1000000, .channel_data = rockchip_saradc_channel_data_v1, .start_channel = rockchip_saradc_start_channel_v1, + .stop = rockchip_saradc_stop_v1, }; static const struct udevice_id rockchip_saradc_ids[] = { From 38f47eb468234f989dcef6b86bb44bf937c4857e Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:24 +0100 Subject: [PATCH 86/91] rockchip: adc: rockchip-saradc: add support for RK3588 This adds support for the SARADCv2 found on RK3588. There is no stop callback as it is currently configured in single conversion mode, where the ADC is powered down after a single conversion has been made. Due to what seems to be a silicon bug, a controller reset needs to be issued before starting a channel conversion otherwise Rockchip says that channel 1 will error whatever that means. This is aligned with upstream and downstream Linux kernel as well as downstream U-Boot. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/adc/rockchip-saradc.c | 102 +++++++++++++++++++++++++++++++++- 1 file changed, 101 insertions(+), 1 deletion(-) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index b5df58fe3eb..10ded1b088f 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -10,12 +10,17 @@ #include #include #include -#include +#include +#include +#include #include +#include #include #include #include +#define usleep_range(a, b) udelay((b)) + #define SARADC_CTRL_CHN_MASK GENMASK(2, 0) #define SARADC_CTRL_POWER_CTRL BIT(3) #define SARADC_CTRL_IRQ_ENABLE BIT(5) @@ -30,8 +35,37 @@ struct rockchip_saradc_regs_v1 { unsigned int dly_pu_soc; }; +struct rockchip_saradc_regs_v2 { + unsigned int conv_con; +#define SARADC2_SINGLE_MODE BIT(5) +#define SARADC2_START BIT(4) +#define SARADC2_CONV_CHANNELS GENMASK(3, 0) + unsigned int t_pd_soc; + unsigned int t_as_soc; + unsigned int t_das_soc; + unsigned int t_sel_soc; + unsigned int high_comp[16]; + unsigned int low_comp[16]; + unsigned int debounce; + unsigned int ht_int_en; + unsigned int lt_int_en; + unsigned int reserved[24]; + unsigned int mt_int_en; + unsigned int end_int_en; +#define SARADC2_EN_END_INT BIT(0) + unsigned int st_con; + unsigned int status; + unsigned int end_int_st; + unsigned int ht_int_st; + unsigned int lt_int_st; + unsigned int mt_int_st; + unsigned int data[16]; + unsigned int auto_ch_en; +}; + union rockchip_saradc_regs { struct rockchip_saradc_regs_v1 *v1; + struct rockchip_saradc_regs_v2 *v2; }; struct rockchip_saradc_data { int num_bits; @@ -46,6 +80,7 @@ struct rockchip_saradc_priv { union rockchip_saradc_regs regs; int active_channel; const struct rockchip_saradc_data *data; + struct reset_ctl *reset; }; int rockchip_saradc_channel_data_v1(struct udevice *dev, int channel, @@ -66,6 +101,22 @@ int rockchip_saradc_channel_data_v1(struct udevice *dev, int channel, return 0; } +int rockchip_saradc_channel_data_v2(struct udevice *dev, int channel, + unsigned int *data) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + + if (!(readl(&priv->regs.v2->end_int_st) & SARADC2_EN_END_INT)) + return -EBUSY; + + /* Read value */ + *data = readl(&priv->regs.v2->data[channel]); + + /* Acknowledge the interrupt */ + writel(SARADC2_EN_END_INT, &priv->regs.v2->end_int_st); + + return 0; +} int rockchip_saradc_channel_data(struct udevice *dev, int channel, unsigned int *data) { @@ -104,6 +155,40 @@ int rockchip_saradc_start_channel_v1(struct udevice *dev, int channel) return 0; } +static void rockchip_saradc_reset_controller(struct reset_ctl *reset) +{ + reset_assert(reset); + usleep_range(10, 20); + reset_deassert(reset); +} + +int rockchip_saradc_start_channel_v2(struct udevice *dev, int channel) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + + /* + * Downstream says + * """If read other chn at anytime, then chn1 will error, assert + * controller as a workaround.""" + */ + if (priv->reset) + rockchip_saradc_reset_controller(priv->reset); + + writel(0xc, &priv->regs.v2->t_das_soc); + writel(0x20, &priv->regs.v2->t_pd_soc); + + /* Acknowledge any previous interrupt */ + writel(SARADC2_EN_END_INT, &priv->regs.v2->end_int_st); + + rk_clrsetreg(&priv->regs.v2->conv_con, + SARADC2_CONV_CHANNELS | SARADC2_START | SARADC2_SINGLE_MODE, + FIELD_PREP(SARADC2_CONV_CHANNELS, channel) | + FIELD_PREP(SARADC2_START, 1) | + FIELD_PREP(SARADC2_SINGLE_MODE, 1)); + + return 0; +} + int rockchip_saradc_start_channel(struct udevice *dev, int channel) { struct rockchip_saradc_priv *priv = dev_get_priv(dev); @@ -162,6 +247,8 @@ int rockchip_saradc_probe(struct udevice *dev) int vref_uv; int ret; + priv->reset = devm_reset_control_get_optional(dev, "saradc-apb"); + ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret; @@ -178,6 +265,9 @@ int rockchip_saradc_probe(struct udevice *dev) return ret; } + if (priv->reset) + rockchip_saradc_reset_controller(priv->reset); + vref_uv = regulator_get_value(vref); if (vref_uv < 0) { printf("can't get vref-supply value: %d\n", vref_uv); @@ -247,6 +337,14 @@ static const struct rockchip_saradc_data rk3399_saradc_data = { .stop = rockchip_saradc_stop_v1, }; +static const struct rockchip_saradc_data rk3588_saradc_data = { + .num_bits = 12, + .num_channels = 8, + .clk_rate = 1000000, + .channel_data = rockchip_saradc_channel_data_v2, + .start_channel = rockchip_saradc_start_channel_v2, +}; + static const struct udevice_id rockchip_saradc_ids[] = { { .compatible = "rockchip,saradc", .data = (ulong)&saradc_data }, @@ -254,6 +352,8 @@ static const struct udevice_id rockchip_saradc_ids[] = { .data = (ulong)&rk3066_tsadc_data }, { .compatible = "rockchip,rk3399-saradc", .data = (ulong)&rk3399_saradc_data }, + { .compatible = "rockchip,rk3588-saradc", + .data = (ulong)&rk3588_saradc_data }, { } }; From 1fb75f7ee4bb5ec5d0db95f5edbdf1d2531ca378 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:25 +0100 Subject: [PATCH 87/91] power: pmic: rk8xx: fix duplicate prompt SPL_PMIC_RK8XX and PMIC_RK8XX both share the same prompt making it difficult to know at first glance in menuconfig what's for what, let's fix this by adding "in SPL" at the end of the prompt for the SPL symbol. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/power/pmic/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 9b61b18e11f..562c1a3b122 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -250,7 +250,7 @@ config PMIC_RK8XX This driver implements register read/write operations. config SPL_PMIC_RK8XX - bool "Enable support for Rockchip PMIC RK8XX" + bool "Enable support for Rockchip PMIC RK8XX in SPL" depends on SPL_DM_PMIC ---help--- The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, From 768636c371482268cb9580f2056ec8a4f8099f96 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:26 +0100 Subject: [PATCH 88/91] rockchip: jaguar-rk3588: enable SARADC and derivatives The SARADC is used on Jaguar for multiple things: - channel 0 is used (at runtime) as a BIOS button, - channel 2 is exposed on the Mezzanine connector for customer specific logic, - channel 5 and 6 are used for identification, Since the SARADC requires a vref-supply provided by the RK806 PMIC, its support and the support for its regulators are also enabled. The button, adc, pmic and regulator commands are also enabled for CLI use in U-Boot for debugging and scripting purposes. The RK806 PMIC on Jaguar being routed on the SPI bus, let's enable Rockchip SPI controller driver. Finally, the SARADC channel 1 on Jaguar is hardwired so will never change in the lifetime of a unit, for that reason, disable the Rockchip Download Mode check by setting ROCKCHIP_BOOT_MODE_REG symbol to 0. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- configs/jaguar-rk3588_defconfig | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 92800dc31e5..3233b75cee9 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -9,6 +9,7 @@ CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_ENV_SIZE=0x1f000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-jaguar" CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0 CONFIG_SPL_SERIAL=y CONFIG_TARGET_JAGUAR_RK3588=y CONFIG_DEBUG_UART_BASE=0xfeb50000 @@ -34,6 +35,7 @@ CONFIG_SPL_ATF=y # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set +CONFIG_CMD_ADC=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -46,6 +48,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_MII is not set # CONFIG_CMD_BLOCK_CACHE is not set # CONFIG_CMD_EFICONFIG is not set +CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EROFS=y CONFIG_CMD_SQUASHFS=y @@ -60,7 +63,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y -# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y CONFIG_SPL_CLK=y CONFIG_CLK_GPIO=y CONFIG_ROCKCHIP_GPIO=y @@ -88,10 +92,14 @@ CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y CONFIG_SPL_RAM=y CONFIG_SCSI=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y From 1606bcb0b806e1da98372b2a2b0536e1bb5b4a16 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:27 +0100 Subject: [PATCH 89/91] adc: add missing depends on ADC for controller drivers The ADC controller drivers are obviously all depending on ADC symbol being selected. While they don't seem to fail to build without, they won't be useful without that symbol selected, so let's make sure the options aren't shown in menuconfig when ADC isn't selected. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/adc/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index a01d73846b7..c9cdbe6942d 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -13,6 +13,7 @@ config ADC config ADC_EXYNOS bool "Enable Exynos 54xx ADC driver" + depends on ADC help This enables basic driver for Exynos ADC compatible with Exynos54xx. It provides: @@ -22,6 +23,7 @@ config ADC_EXYNOS config ADC_SANDBOX bool "Enable Sandbox ADC test driver" + depends on ADC help This enables driver for Sandbox ADC device emulation. It provides: @@ -31,6 +33,7 @@ config ADC_SANDBOX config SARADC_MESON bool "Enable Amlogic Meson SARADC driver" + depends on ADC imply REGMAP help This enables driver for Amlogic Meson SARADC. @@ -41,6 +44,7 @@ config SARADC_MESON config SARADC_ROCKCHIP bool "Enable Rockchip SARADC driver" + depends on ADC help This enables driver for Rockchip SARADC. It provides: From 759ae818ba760e97a895bdaa1cd7a86f8972ea93 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:28 +0100 Subject: [PATCH 90/91] button: add missing ADC dependency for BUTTON_ADC The BUTTON_ADC symbol guards the compilation of button-adc driver whose name very well makes it explicit that it requires ADC support to be enabled. Fix build issue of button-adc driver when ADC support isn't enabled by making sure it cannot be built without ADC support. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/button/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/button/Kconfig b/drivers/button/Kconfig index 097b05f822e..3918b05ae03 100644 --- a/drivers/button/Kconfig +++ b/drivers/button/Kconfig @@ -12,6 +12,7 @@ config BUTTON config BUTTON_ADC bool "Button adc" depends on BUTTON + depends on ADC help Enable support for buttons which are connected to Analog to Digital Converter device. The ADC driver must use driver model. Buttons are From 12bc1a5462a22f6dc5b91ecbf092cbaf94e66820 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 14 Mar 2024 10:36:29 +0100 Subject: [PATCH 91/91] rockchip: boot_mode: fix rockchip_dnl_key_pressed requiring ADC support ADC support is implied by the Rockchip arch Kconfig but that means it should be possible to disable ADC support and still be able to build. However the weak implementation of rockchip_dnl_key_pressed() currently blindly use functions from the ADC subsystem which do not exist when ADC is not enabled, failing the build. Therefore, let's encapsulate this logic with a check on the ADC symbol being selected. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- arch/arm/mach-rockchip/boot_mode.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index eb8f65ae4e9..f9be396aa55 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -40,6 +40,7 @@ void set_back_to_bootrom_dnl_flag(void) __weak int rockchip_dnl_key_pressed(void) { +#if CONFIG_IS_ENABLED(ADC) unsigned int val; struct udevice *dev; struct uclass *uc; @@ -69,6 +70,9 @@ __weak int rockchip_dnl_key_pressed(void) return true; else return false; +#else + return false; +#endif } void rockchip_dnl_mode_check(void)