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arm: vf610: Add clock support for DSPI
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
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@ -198,6 +198,11 @@ static u32 get_i2c_clk(void)
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return get_ipg_clk();
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}
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static u32 get_dspi_clk(void)
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{
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return get_ipg_clk();
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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@ -215,6 +220,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
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return get_fec_clk();
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case MXC_I2C_CLK:
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return get_i2c_clk();
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case MXC_DSPI_CLK:
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return get_dspi_clk();
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default:
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break;
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}
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@ -17,6 +17,7 @@ enum mxc_clock {
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MXC_ESDHC_CLK,
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MXC_FEC_CLK,
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MXC_I2C_CLK,
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MXC_DSPI_CLK,
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};
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void enable_ocotp_clk(unsigned char enable);
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@ -189,6 +189,8 @@ struct anadig_reg {
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#define CCM_REG_CTRL_MASK 0xffffffff
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#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
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#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
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#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24)
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#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
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#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
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#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
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#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
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@ -206,6 +208,8 @@ struct anadig_reg {
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#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
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#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
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#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
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#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24)
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#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26)
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#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
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#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
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#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)
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