mirrors/u-boot
0
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2024-11-26 13:44:29 +08:00
Code Issues Packages Projects Releases Wiki Activity

usb: xhci-dwc3: Add USB2 PHY configuration

Browse Source 
Configure USB2 PHY register based on "phy_type" property and
handle all the quirks that are relevant for Rockchip RK3399 SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Mark Kettenis 2019-06-30 18:01:55 +02:00 committed by Kever Yang
parent aaa8d6b149
commit 062790f461
1 changed files with 20 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/usb/host/xhci-dwc3.c
View File

@ -118,6 +118,8 @@ static int xhci_dwc3_probe(struct udevice *dev)
struct dwc3 *dwc3_reg;
enum usb_dr_mode dr_mode;
struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
const char *phy;
u32 reg;
int ret;
hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
@ -132,6 +134,24 @@ static int xhci_dwc3_probe(struct udevice *dev)
dwc3_core_init(dwc3_reg);
/* Set dwc3 usb2 phy config */
reg = readl(&dwc3_reg->g_usb2phycfg[0]);
phy = dev_read_string(dev, "phy_type");
if (phy && strcmp(phy, "utmi_wide") == 0) {
reg |= DWC3_GUSB2PHYCFG_PHYIF;
reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
}
if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
writel(reg, &dwc3_reg->g_usb2phycfg[0]);
dr_mode = usb_get_dr_mode(dev_of_offset(dev));
if (dr_mode == USB_DR_MODE_UNKNOWN)
/* by default set dual role mode to HOST */