arm: octeontx2: Add headers for OcteonTX2

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>

arch/arm/include/asm/arch-octeontx2/board.h

@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier:    GPL-2.0
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <asm/arch/soc.h>
+
+/** Reg offsets */
+#define RST_BOOT		0x87E006001600ULL
+
+#define CPC_BOOT_OWNERX(a)	0x86D000000160ULL + (8 * (a))
+
+/** Structure definitions */
+/**
+ * Register (NCB32b) cpc_boot_owner#
+ *
+ * CPC Boot Owner Registers These registers control an external arbiter
+ * for the boot device (SPI/eMMC) across multiple external devices. There
+ * is a register for each requester: _ \<0\> - SCP          - reset on
+ * SCP reset _ \<1\> - MCP          - reset on MCP reset _ \<2\> - AP
+ * Secure    - reset on core reset _ \<3\> - AP Nonsecure - reset on core
+ * reset  These register is only writable to the corresponding
+ * requestor(s) permitted with CPC_PERMIT.
+ */
+union cpc_boot_ownerx {
+	u32 u;
+	struct cpc_boot_ownerx_s {
+		u32 boot_req		: 1;
+		u32 reserved_1_7	: 7;
+		u32 boot_wait		: 1;
+		u32 reserved_9_31	: 23;
+	} s;
+};
+
+/**
+ * Register (RSL) rst_boot
+ *
+ * RST Boot Register This register is not accessible through ROM scripts;
+ * see SCR_WRITE32_S[ADDR].
+ */
+union rst_boot {
+	u64 u;
+	struct rst_boot_s {
+		u64 rboot_pin                        : 1;
+		u64 rboot                            : 1;
+		u64 reserved_2_32                    : 31;
+		u64 pnr_mul                          : 6;
+		u64 reserved_39                      : 1;
+		u64 c_mul                            : 7;
+		u64 reserved_47_52                   : 6;
+		u64 gpio_ejtag                       : 1;
+		u64 mcp_jtagdis                      : 1;
+		u64 dis_scan                         : 1;
+		u64 dis_huk                          : 1;
+		u64 vrm_err                          : 1;
+		u64 jt_tstmode                       : 1;
+		u64 ckill_ppdis                      : 1;
+		u64 trusted_mode                     : 1;
+		u64 reserved_61_62                   : 2;
+		u64 chipkill                         : 1;
+	} s;
+	struct rst_boot_cn96xx {
+		u64 rboot_pin                        : 1;
+		u64 rboot                            : 1;
+		u64 reserved_2_23                    : 22;
+		u64 cpt_mul                          : 7;
+		u64 reserved_31_32                   : 2;
+		u64 pnr_mul                          : 6;
+		u64 reserved_39                      : 1;
+		u64 c_mul                            : 7;
+		u64 reserved_47_52                   : 6;
+		u64 gpio_ejtag                       : 1;
+		u64 mcp_jtagdis                      : 1;
+		u64 dis_scan                         : 1;
+		u64 dis_huk                          : 1;
+		u64 vrm_err                          : 1;
+		u64 reserved_58_59                   : 2;
+		u64 trusted_mode                     : 1;
+		u64 scp_jtagdis                      : 1;
+		u64 jtagdis                          : 1;
+		u64 chipkill                         : 1;
+	} cn96xx;
+	struct rst_boot_cnf95xx {
+		u64 rboot_pin                        : 1;
+		u64 rboot                            : 1;
+		u64 reserved_2_7                     : 6;
+		u64 bphy_mul                         : 7;
+		u64 reserved_15                      : 1;
+		u64 dsp_mul                          : 7;
+		u64 reserved_23                      : 1;
+		u64 cpt_mul                          : 7;
+		u64 reserved_31_32                   : 2;
+		u64 pnr_mul                          : 6;
+		u64 reserved_39                      : 1;
+		u64 c_mul                            : 7;
+		u64 reserved_47_52                   : 6;
+		u64 gpio_ejtag                       : 1;
+		u64 mcp_jtagdis                      : 1;
+		u64 dis_scan                         : 1;
+		u64 dis_huk                          : 1;
+		u64 vrm_err                          : 1;
+		u64 reserved_58_59                   : 2;
+		u64 trusted_mode                     : 1;
+		u64 scp_jtagdis                      : 1;
+		u64 jtagdis                          : 1;
+		u64 chipkill                         : 1;
+	} cnf95xx;
+};
+
+extern unsigned long fdt_base_addr;
+
+/** Function definitions */
+void mem_map_fill(void);
+int fdt_get_board_mac_cnt(void);
+u64 fdt_get_board_mac_addr(void);
+const char *fdt_get_board_model(void);
+const char *fdt_get_board_serial(void);
+const char *fdt_get_board_revision(void);
+void octeontx2_board_get_mac_addr(u8 index, u8 *mac_addr);
+void board_acquire_flash_arb(bool acquire);
+void cgx_intf_shutdown(void);
+
+#endif /* __BOARD_H__ */

arch/arm/include/asm/arch-octeontx2/clock.h

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier:    GPL-2.0
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __CLOCK_H__
+
+/** System PLL reference clock */
+#define PLL_REF_CLK                     50000000        /* 50 MHz */
+#define NS_PER_REF_CLK_TICK             (1000000000 / PLL_REF_CLK)
+
+/**
+ * Returns the I/O clock speed in Hz
+ */
+u64 octeontx_get_io_clock(void);
+
+/**
+ * Returns the core clock speed in Hz
+ */
+u64 octeontx_get_core_clock(void);
+
+#endif /* __CLOCK_H__ */

arch/arm/include/asm/arch-octeontx2/csrs/csrs-lmt.h

@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier:    GPL-2.0
+ *
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+#ifndef __CSRS_LMT_H__
+#define __CSRS_LMT_H__
+
+/**
+ * @file
+ *
+ * Configuration and status register (CSR) address and type definitions for
+ * LMT.
+ *
+ * This file is auto generated.  Do not edit.
+ *
+ */
+
+/**
+ * Register (RVU_PFVF_BAR2) lmt_lf_lmtcancel
+ *
+ * RVU VF LMT Cancel Register
+ */
+union lmt_lf_lmtcancel {
+	u64 u;
+	struct lmt_lf_lmtcancel_s {
+		u64 data                             : 64;
+	} s;
+	/* struct lmt_lf_lmtcancel_s cn; */
+};
+
+static inline u64 LMT_LF_LMTCANCEL(void)
+	__attribute__ ((pure, always_inline));
+static inline u64 LMT_LF_LMTCANCEL(void)
+{
+	return 0x400;
+}
+
+/**
+ * Register (RVU_PFVF_BAR2) lmt_lf_lmtline#
+ *
+ * RVU VF LMT Line Registers
+ */
+union lmt_lf_lmtlinex {
+	u64 u;
+	struct lmt_lf_lmtlinex_s {
+		u64 data                             : 64;
+	} s;
+	/* struct lmt_lf_lmtlinex_s cn; */
+};
+
+static inline u64 LMT_LF_LMTLINEX(u64 a)
+	__attribute__ ((pure, always_inline));
+static inline u64 LMT_LF_LMTLINEX(u64 a)
+{
+	return 0 + 8 * a;
+}
+
+#endif /* __CSRS_LMT_H__ */

arch/arm/include/asm/arch-octeontx2/gpio.h

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier:    GPL-2.0
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */

arch/arm/include/asm/arch-octeontx2/smc-id.h

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier:    GPL-2.0
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __SMC_ID_H__
+#define __SMC_ID_H__
+
+/* SMC function IDs for general purpose queries */
+
+#define OCTEONTX2_SVC_CALL_COUNT	0xc200ff00
+#define OCTEONTX2_SVC_UID		0xc200ff01
+
+#define OCTEONTX2_SVC_VERSION		0xc200ff03
+
+/* OcteonTX Service Calls version numbers */
+#define OCTEONTX2_VERSION_MAJOR	0x1
+#define OCTEONTX2_VERSION_MINOR	0x0
+
+/* x1 - node number */
+#define OCTEONTX2_DRAM_SIZE		0xc2000301
+#define OCTEONTX2_NODE_COUNT		0xc2000601
+#define OCTEONTX2_DISABLE_RVU_LFS	0xc2000b01
+
+#define OCTEONTX2_CONFIG_OOO		0xc2000b04
+
+/* fail safe */
+#define OCTEONTX2_FSAFE_PR_BOOT_SUCCESS	0xc2000b02
+
+#endif /* __SMC_ID_H__ */

arch/arm/include/asm/arch-octeontx2/smc.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier:    GPL-2.0
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __SMC_H__
+#define __SMC_H__
+
+#include <asm/arch/smc-id.h>
+
+ssize_t smc_configure_ooo(unsigned int val);
+ssize_t smc_dram_size(unsigned int node);
+ssize_t smc_disable_rvu_lfs(unsigned int node);
+ssize_t smc_flsf_fw_booted(void);
+
+#endif

arch/arm/include/asm/arch-octeontx2/soc.h

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier:    GPL-2.0
+ *
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+/* Product PARTNUM */
+#define CN81XX	0xA2
+#define CN83XX	0xA3
+#define CN96XX	0xB2
+#define CN95XX	0xB3
+
+/* Register defines */
+
+#define otx_is_soc(soc)	(read_partnum() == (soc))
+#define otx_is_board(model) (!strcmp(read_board_name(), model))
+#define otx_is_platform(platform) (read_platform() == (platform))
+
+enum platform_t {
+	PLATFORM_HW = 0,
+	PLATFORM_EMULATOR = 1,
+	PLATFORM_ASIM = 3,
+};
+
+int read_platform(void);
+u8 read_partnum(void);
+const char *read_board_name(void);
+
+#endif /* __SOC_H */