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arm64: zynqmp: Remove low level UART setting cont

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There is no reason to do serial initialization. Uart driver does it already
based on DT. Good effect is that it is clear which interface is console.
The same change was done in past by commit 84d2bbf082 ("arm64: zynqmp:
Remove low level UART setting").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/91a73f292bafc4b64ed09954cc23780496da4b65.1648125082.git.michal.simek@xilinx.com
This commit is contained in:
Michal Simek 2022-03-24 13:31:26 +01:00
parent 7ce9d921bd
commit 0302a207c3
7 changed files with 0 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
board/xilinx/zynqmp/zynqmp-dlc21-revA/psu_init_gpl.c
View File

@ -509,10 +509,6 @@ static unsigned long psu_peripherals_init_data(void)
psu_mask_write(0xFF5E0238, 0x00000008U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);

4
board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c
View File

@ -521,10 +521,6 @@ static unsigned long psu_peripherals_init_data(void)
psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);

8
board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c
View File

@ -522,14 +522,6 @@ static unsigned long psu_peripherals_init_data(void)
psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);

8
board/xilinx/zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c
View File

@ -516,14 +516,6 @@ static unsigned long psu_peripherals_init_data(void)
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
psu_mask_write(0xFF000034, 0x000000FFU, 0x0000000CU);
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000003EU);
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF010034, 0x000000FFU, 0x0000000CU);
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000003EU);
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);

8
board/xilinx/zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c
View File

@ -512,14 +512,6 @@ static unsigned long psu_peripherals_init_data(void)
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);

4
board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c
View File

@ -513,10 +513,6 @@ static unsigned long psu_peripherals_init_data(void)
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);

4
board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c
View File

@ -513,10 +513,6 @@ static unsigned long psu_peripherals_init_data(void)
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);