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ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL
The commit
f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Jassi Brar
Tom Rini
parent
c71b4dd2da
commit
02c41535b6
@ -418,55 +418,6 @@ static void setup_dplls(void)
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#endif
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}
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#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
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static void setup_non_essential_dplls(void)
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{
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u32 abe_ref_clk;
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const struct dpll_params *params;
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/* IVA */
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clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
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CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
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params = get_iva_dpll_params(*dplls_data);
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do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
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/* Configure ABE dpll */
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params = get_abe_dpll_params(*dplls_data);
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
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if (omap_revision() == DRA752_ES1_0)
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/* Select the sys clk for dpll_abe */
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clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
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CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
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CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
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#else
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abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
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/*
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* We need to enable some additional options to achieve
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* 196.608MHz from 32768 Hz
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*/
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setbits_le32((*prcm)->cm_clkmode_dpll_abe,
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CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
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CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
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CM_CLKMODE_DPLL_LPMODE_EN_MASK|
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CM_CLKMODE_DPLL_REGM4XEN_MASK);
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/* Spend 4 REFCLK cycles at each stage */
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clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
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CM_CLKMODE_DPLL_RAMP_RATE_MASK,
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1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
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#endif
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/* Select the right reference clk */
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clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
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CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
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abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
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/* Lock the dpll */
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do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
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}
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#endif
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u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
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{
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u32 offset_code;
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@ -760,10 +711,6 @@ void prcm_init(void)
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timer_init();
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scale_vcores(*omap_vcores);
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setup_dplls();
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#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
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setup_non_essential_dplls();
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enable_non_essential_clocks();
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#endif
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setup_warmreset_time();
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break;
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default:
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@ -399,91 +399,6 @@ void enable_basic_uboot_clocks(void)
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1);
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}
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/*
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* Enable non-essential clock domains, modules and
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* do some additional special settings needed
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*/
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void enable_non_essential_clocks(void)
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{
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u32 const clk_domains_non_essential[] = {
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(*prcm)->cm_mpu_m3_clkstctrl,
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(*prcm)->cm_ivahd_clkstctrl,
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(*prcm)->cm_dsp_clkstctrl,
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(*prcm)->cm_dss_clkstctrl,
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(*prcm)->cm_sgx_clkstctrl,
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(*prcm)->cm1_abe_clkstctrl,
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(*prcm)->cm_c2c_clkstctrl,
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(*prcm)->cm_cam_clkstctrl,
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(*prcm)->cm_dss_clkstctrl,
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(*prcm)->cm_sdma_clkstctrl,
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0
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};
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u32 const clk_modules_hw_auto_non_essential[] = {
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(*prcm)->cm_l3instr_l3_3_clkctrl,
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(*prcm)->cm_l3instr_l3_instr_clkctrl,
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(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
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(*prcm)->cm_l3init_hsi_clkctrl,
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0
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};
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u32 const clk_modules_explicit_en_non_essential[] = {
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(*prcm)->cm1_abe_aess_clkctrl,
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(*prcm)->cm1_abe_pdm_clkctrl,
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(*prcm)->cm1_abe_dmic_clkctrl,
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(*prcm)->cm1_abe_mcasp_clkctrl,
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(*prcm)->cm1_abe_mcbsp1_clkctrl,
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(*prcm)->cm1_abe_mcbsp2_clkctrl,
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(*prcm)->cm1_abe_mcbsp3_clkctrl,
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(*prcm)->cm1_abe_slimbus_clkctrl,
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(*prcm)->cm1_abe_timer5_clkctrl,
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(*prcm)->cm1_abe_timer6_clkctrl,
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(*prcm)->cm1_abe_timer7_clkctrl,
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(*prcm)->cm1_abe_timer8_clkctrl,
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(*prcm)->cm1_abe_wdt3_clkctrl,
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(*prcm)->cm_l4per_gptimer9_clkctrl,
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(*prcm)->cm_l4per_gptimer10_clkctrl,
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(*prcm)->cm_l4per_gptimer11_clkctrl,
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(*prcm)->cm_l4per_gptimer3_clkctrl,
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(*prcm)->cm_l4per_gptimer4_clkctrl,
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(*prcm)->cm_l4per_hdq1w_clkctrl,
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(*prcm)->cm_l4per_mcbsp4_clkctrl,
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(*prcm)->cm_l4per_mcspi2_clkctrl,
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(*prcm)->cm_l4per_mcspi3_clkctrl,
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(*prcm)->cm_l4per_mcspi4_clkctrl,
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(*prcm)->cm_l4per_mmcsd3_clkctrl,
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(*prcm)->cm_l4per_mmcsd4_clkctrl,
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(*prcm)->cm_l4per_mmcsd5_clkctrl,
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(*prcm)->cm_l4per_uart1_clkctrl,
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(*prcm)->cm_l4per_uart2_clkctrl,
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(*prcm)->cm_l4per_uart4_clkctrl,
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(*prcm)->cm_wkup_keyboard_clkctrl,
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(*prcm)->cm_wkup_wdtimer2_clkctrl,
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(*prcm)->cm_cam_iss_clkctrl,
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(*prcm)->cm_cam_fdif_clkctrl,
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(*prcm)->cm_dss_dss_clkctrl,
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(*prcm)->cm_sgx_sgx_clkctrl,
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0
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};
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/* Enable optional functional clock for ISS */
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setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
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/* Enable all optional functional clocks of DSS */
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setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
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do_enable_clocks(clk_domains_non_essential,
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clk_modules_hw_auto_non_essential,
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clk_modules_explicit_en_non_essential,
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0);
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/* Put camera module in no sleep mode */
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clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
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MODULE_CLKCTRL_MODULEMODE_MASK,
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CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
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MODULE_CLKCTRL_MODULEMODE_SHIFT);
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}
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void hw_data_init(void)
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{
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u32 omap_rev = omap_revision();
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@ -486,94 +486,6 @@ void enable_basic_uboot_clocks(void)
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1);
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}
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/*
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* Enable non-essential clock domains, modules and
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* do some additional special settings needed
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*/
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void enable_non_essential_clocks(void)
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{
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u32 const clk_domains_non_essential[] = {
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(*prcm)->cm_mpu_m3_clkstctrl,
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(*prcm)->cm_ivahd_clkstctrl,
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(*prcm)->cm_dsp_clkstctrl,
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(*prcm)->cm_dss_clkstctrl,
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(*prcm)->cm_sgx_clkstctrl,
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(*prcm)->cm1_abe_clkstctrl,
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(*prcm)->cm_c2c_clkstctrl,
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(*prcm)->cm_cam_clkstctrl,
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(*prcm)->cm_dss_clkstctrl,
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(*prcm)->cm_sdma_clkstctrl,
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0
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};
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u32 const clk_modules_hw_auto_non_essential[] = {
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(*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
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(*prcm)->cm_ivahd_ivahd_clkctrl,
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(*prcm)->cm_ivahd_sl2_clkctrl,
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(*prcm)->cm_dsp_dsp_clkctrl,
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(*prcm)->cm_l3instr_l3_3_clkctrl,
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(*prcm)->cm_l3instr_l3_instr_clkctrl,
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(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
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(*prcm)->cm_l3init_hsi_clkctrl,
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(*prcm)->cm_l4per_hdq1w_clkctrl,
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0
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};
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u32 const clk_modules_explicit_en_non_essential[] = {
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(*prcm)->cm1_abe_aess_clkctrl,
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(*prcm)->cm1_abe_pdm_clkctrl,
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(*prcm)->cm1_abe_dmic_clkctrl,
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(*prcm)->cm1_abe_mcasp_clkctrl,
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(*prcm)->cm1_abe_mcbsp1_clkctrl,
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(*prcm)->cm1_abe_mcbsp2_clkctrl,
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(*prcm)->cm1_abe_mcbsp3_clkctrl,
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(*prcm)->cm1_abe_slimbus_clkctrl,
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(*prcm)->cm1_abe_timer5_clkctrl,
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(*prcm)->cm1_abe_timer6_clkctrl,
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(*prcm)->cm1_abe_timer7_clkctrl,
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(*prcm)->cm1_abe_timer8_clkctrl,
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(*prcm)->cm1_abe_wdt3_clkctrl,
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(*prcm)->cm_l4per_gptimer9_clkctrl,
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(*prcm)->cm_l4per_gptimer10_clkctrl,
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(*prcm)->cm_l4per_gptimer11_clkctrl,
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(*prcm)->cm_l4per_gptimer3_clkctrl,
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(*prcm)->cm_l4per_gptimer4_clkctrl,
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(*prcm)->cm_l4per_mcspi2_clkctrl,
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(*prcm)->cm_l4per_mcspi3_clkctrl,
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(*prcm)->cm_l4per_mcspi4_clkctrl,
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(*prcm)->cm_l4per_mmcsd3_clkctrl,
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(*prcm)->cm_l4per_mmcsd4_clkctrl,
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(*prcm)->cm_l4per_mmcsd5_clkctrl,
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(*prcm)->cm_l4per_uart1_clkctrl,
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(*prcm)->cm_l4per_uart2_clkctrl,
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(*prcm)->cm_l4per_uart4_clkctrl,
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(*prcm)->cm_wkup_keyboard_clkctrl,
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(*prcm)->cm_wkup_wdtimer2_clkctrl,
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(*prcm)->cm_cam_iss_clkctrl,
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(*prcm)->cm_cam_fdif_clkctrl,
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(*prcm)->cm_dss_dss_clkctrl,
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(*prcm)->cm_sgx_sgx_clkctrl,
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0
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};
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/* Enable optional functional clock for ISS */
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setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
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/* Enable all optional functional clocks of DSS */
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setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
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do_enable_clocks(clk_domains_non_essential,
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clk_modules_hw_auto_non_essential,
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clk_modules_explicit_en_non_essential,
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0);
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/* Put camera module in no sleep mode */
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clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
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MODULE_CLKCTRL_MODULEMODE_MASK,
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CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
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MODULE_CLKCTRL_MODULEMODE_SHIFT);
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}
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const struct ctrl_ioregs ioregs_omap5430 = {
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.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
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.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
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@ -567,7 +567,6 @@ u32 omap_ddr_clk(void);
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u32 get_sys_clk_index(void);
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void enable_basic_clocks(void);
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void enable_basic_uboot_clocks(void);
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void enable_non_essential_clocks(void);
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void scale_vcores(struct vcores_data const *);
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u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
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void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
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