2016-04-07 22:00:11 +08:00
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CONFIG_ARM=y
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CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
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CONFIG_ARCH_ZYNQMP=y
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2016-06-03 17:35:17 +08:00
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CONFIG_SYS_MALLOC_F_LEN=0x8000
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2016-07-29 18:01:47 +08:00
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CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
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2016-04-07 22:00:11 +08:00
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CONFIG_SYS_TEXT_BASE=0x8000000
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CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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2016-05-17 14:38:53 +08:00
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CONFIG_SPL_LOAD_FIT=y
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2016-09-13 13:18:22 +08:00
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CONFIG_SPL=y
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y
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2016-04-22 19:04:42 +08:00
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CONFIG_HUSH_PARSER=y
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2016-04-07 22:00:11 +08:00
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CONFIG_SYS_PROMPT="ZynqMP> "
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# CONFIG_CMD_IMLS is not set
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CONFIG_CMD_MEMTEST=y
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# CONFIG_CMD_FLASH is not set
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2016-04-25 05:29:26 +08:00
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CONFIG_CMD_MMC=y
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2016-04-13 14:49:03 +08:00
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CONFIG_CMD_I2C=y
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2016-04-07 22:00:11 +08:00
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CONFIG_CMD_TFTPPUT=y
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CONFIG_CMD_DHCP=y
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2016-04-25 05:29:26 +08:00
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CONFIG_CMD_MII=y
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2016-04-07 22:00:11 +08:00
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CONFIG_CMD_PING=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_TIMER=y
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2016-04-25 05:29:26 +08:00
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
|
2016-07-15 14:41:46 +08:00
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CONFIG_SPL_OF_CONTROL=y
|
2016-04-07 22:00:11 +08:00
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CONFIG_OF_EMBED=y
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2016-07-27 21:08:03 +08:00
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CONFIG_SPL_DM=y
|
2016-07-15 14:41:46 +08:00
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CONFIG_SPL_DM_SEQ_ALIAS=y
|
2016-08-01 14:49:12 +08:00
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CONFIG_BLK=y
|
2016-01-13 18:55:37 +08:00
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQMPPL=y
|
2016-09-09 04:11:59 +08:00
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|
CONFIG_DM_GPIO=y
|
2016-07-27 21:08:03 +08:00
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|
|
CONFIG_DM_I2C=y
|
2016-04-13 14:49:03 +08:00
|
|
|
CONFIG_SYS_I2C_CADENCE=y
|
2016-04-07 22:00:11 +08:00
|
|
|
CONFIG_DM_MMC=y
|
2016-08-01 14:49:12 +08:00
|
|
|
CONFIG_DM_MMC_OPS=y
|
2016-04-07 22:00:11 +08:00
|
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|
CONFIG_ZYNQ_SDHCI=y
|
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|
|
CONFIG_DM_ETH=y
|
2016-05-12 00:25:49 +08:00
|
|
|
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|