2014-07-30 13:08:14 +08:00
|
|
|
menu "ARC architecture"
|
|
|
|
depends on ARC
|
|
|
|
|
|
|
|
config SYS_ARCH
|
|
|
|
default "arc"
|
|
|
|
|
2014-12-25 23:47:45 +08:00
|
|
|
config SYS_CPU
|
2015-01-13 23:35:46 +08:00
|
|
|
default "arcv1" if ISA_ARCOMPACT
|
|
|
|
default "arcv2" if ISA_ARCV2
|
|
|
|
|
|
|
|
choice
|
|
|
|
prompt "ARC Instruction Set"
|
|
|
|
default ISA_ARCOMPACT
|
|
|
|
|
|
|
|
config ISA_ARCOMPACT
|
|
|
|
bool "ARCompact ISA"
|
|
|
|
help
|
|
|
|
The original ARC ISA of ARC600/700 cores
|
|
|
|
|
|
|
|
config ISA_ARCV2
|
|
|
|
bool "ARC ISA v2"
|
|
|
|
help
|
|
|
|
ISA for the Next Generation ARC-HS cores
|
|
|
|
|
|
|
|
endchoice
|
2014-12-25 23:47:45 +08:00
|
|
|
|
2015-02-03 18:58:11 +08:00
|
|
|
choice
|
|
|
|
prompt "CPU selection"
|
2015-01-13 23:35:46 +08:00
|
|
|
default CPU_ARC770D if ISA_ARCOMPACT
|
|
|
|
default CPU_ARCHS38 if ISA_ARCV2
|
2015-02-03 18:58:11 +08:00
|
|
|
|
|
|
|
config CPU_ARC750D
|
|
|
|
bool "ARC 750D"
|
2015-01-13 23:35:46 +08:00
|
|
|
depends on ISA_ARCOMPACT
|
2018-07-23 21:55:15 +08:00
|
|
|
select ARC_MMU_V2
|
2015-02-03 18:58:11 +08:00
|
|
|
help
|
|
|
|
Choose this option to build an U-Boot for ARC750D CPU.
|
|
|
|
|
|
|
|
config CPU_ARC770D
|
|
|
|
bool "ARC 770D"
|
2015-01-13 23:35:46 +08:00
|
|
|
depends on ISA_ARCOMPACT
|
2018-07-23 21:55:15 +08:00
|
|
|
select ARC_MMU_V3
|
2015-02-03 18:58:11 +08:00
|
|
|
help
|
|
|
|
Choose this option to build an U-Boot for ARC770D CPU.
|
|
|
|
|
2015-01-13 23:35:46 +08:00
|
|
|
config CPU_ARCEM6
|
|
|
|
bool "ARC EM6"
|
|
|
|
depends on ISA_ARCV2
|
2018-07-23 21:55:15 +08:00
|
|
|
select ARC_MMU_ABSENT
|
2015-01-13 23:35:46 +08:00
|
|
|
help
|
|
|
|
Next Generation ARC Core based on ISA-v2 ISA without MMU.
|
|
|
|
|
|
|
|
config CPU_ARCHS36
|
|
|
|
bool "ARC HS36"
|
|
|
|
depends on ISA_ARCV2
|
2018-07-23 21:55:15 +08:00
|
|
|
select ARC_MMU_ABSENT
|
2015-01-13 23:35:46 +08:00
|
|
|
help
|
|
|
|
Next Generation ARC Core based on ISA-v2 ISA without MMU.
|
|
|
|
|
|
|
|
config CPU_ARCHS38
|
|
|
|
bool "ARC HS38"
|
|
|
|
depends on ISA_ARCV2
|
2018-07-23 21:55:15 +08:00
|
|
|
select ARC_MMU_V4
|
2015-01-13 23:35:46 +08:00
|
|
|
help
|
|
|
|
Next Generation ARC Core based on ISA-v2 ISA with MMU.
|
|
|
|
|
2015-02-03 18:58:11 +08:00
|
|
|
endchoice
|
|
|
|
|
|
|
|
choice
|
|
|
|
prompt "MMU Version"
|
|
|
|
default ARC_MMU_V3 if CPU_ARC770D
|
|
|
|
default ARC_MMU_V2 if CPU_ARC750D
|
2015-01-13 23:35:46 +08:00
|
|
|
default ARC_MMU_ABSENT if CPU_ARCEM6
|
|
|
|
default ARC_MMU_ABSENT if CPU_ARCHS36
|
|
|
|
default ARC_MMU_V4 if CPU_ARCHS38
|
|
|
|
|
|
|
|
config ARC_MMU_ABSENT
|
|
|
|
bool "No MMU"
|
|
|
|
help
|
|
|
|
No MMU
|
2015-02-03 18:58:11 +08:00
|
|
|
|
|
|
|
config ARC_MMU_V2
|
|
|
|
bool "MMU v2"
|
|
|
|
depends on CPU_ARC750D
|
|
|
|
help
|
|
|
|
Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
|
|
|
|
when 2 D-TLB and 1 I-TLB entries index into same 2way set.
|
|
|
|
|
|
|
|
config ARC_MMU_V3
|
|
|
|
bool "MMU v3"
|
|
|
|
depends on CPU_ARC770D
|
|
|
|
help
|
|
|
|
Introduced with ARC700 4.10: New Features
|
|
|
|
Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
|
|
|
|
Shared Address Spaces (SASID)
|
|
|
|
|
2015-01-13 23:35:46 +08:00
|
|
|
config ARC_MMU_V4
|
|
|
|
bool "MMU v4"
|
|
|
|
depends on CPU_ARCHS38
|
|
|
|
help
|
|
|
|
Introduced as a part of ARC HS38 release.
|
|
|
|
|
2015-02-03 18:58:11 +08:00
|
|
|
endchoice
|
|
|
|
|
2015-02-03 18:58:14 +08:00
|
|
|
config CPU_BIG_ENDIAN
|
|
|
|
bool "Enable Big Endian Mode"
|
|
|
|
default n
|
|
|
|
help
|
|
|
|
Build kernel for Big Endian Mode of ARC CPU
|
|
|
|
|
2015-02-03 18:58:13 +08:00
|
|
|
config SYS_ICACHE_OFF
|
2019-05-03 21:40:59 +08:00
|
|
|
bool "Do not enable icache"
|
2015-02-03 18:58:13 +08:00
|
|
|
default n
|
2019-05-03 21:40:59 +08:00
|
|
|
help
|
|
|
|
Do not enable instruction cache in U-Boot.
|
2015-02-03 18:58:13 +08:00
|
|
|
|
2019-05-03 21:41:00 +08:00
|
|
|
config SPL_SYS_ICACHE_OFF
|
|
|
|
bool "Do not enable icache in SPL"
|
|
|
|
depends on SPL
|
|
|
|
default SYS_ICACHE_OFF
|
|
|
|
help
|
|
|
|
Do not enable instruction cache in SPL.
|
|
|
|
|
2015-02-03 18:58:13 +08:00
|
|
|
config SYS_DCACHE_OFF
|
2019-05-03 21:40:59 +08:00
|
|
|
bool "Do not enable dcache"
|
2015-02-03 18:58:13 +08:00
|
|
|
default n
|
2019-05-03 21:40:59 +08:00
|
|
|
help
|
|
|
|
Do not enable data cache in U-Boot.
|
2015-02-03 18:58:13 +08:00
|
|
|
|
2019-05-03 21:41:00 +08:00
|
|
|
config SPL_SYS_DCACHE_OFF
|
|
|
|
bool "Do not enable dcache in SPL"
|
|
|
|
depends on SPL
|
|
|
|
default SYS_DCACHE_OFF
|
|
|
|
help
|
|
|
|
Do not enable data cache in SPL.
|
|
|
|
|
2018-03-21 20:58:59 +08:00
|
|
|
menuconfig ARC_DBG
|
|
|
|
bool "ARC debugging"
|
|
|
|
default n
|
|
|
|
|
|
|
|
if ARC_DBG
|
|
|
|
|
|
|
|
config ARC_DBG_IOC_ENABLE
|
|
|
|
bool "Enable IO coherency unit"
|
|
|
|
depends on CPU_ARCHS38
|
|
|
|
default n
|
|
|
|
help
|
|
|
|
Enable IO coherency unit to debug problems with caches and
|
|
|
|
DMA peripherals.
|
|
|
|
NOTE: as of today linux will not work properly if this option
|
|
|
|
is enabled in u-boot!
|
|
|
|
|
|
|
|
endif
|
|
|
|
|
2014-07-30 13:08:14 +08:00
|
|
|
choice
|
|
|
|
prompt "Target select"
|
2017-03-21 19:49:48 +08:00
|
|
|
default TARGET_AXS103
|
2014-07-30 13:08:14 +08:00
|
|
|
|
|
|
|
config TARGET_TB100
|
|
|
|
bool "Support tb100"
|
|
|
|
|
2016-08-04 19:35:01 +08:00
|
|
|
config TARGET_NSIM
|
|
|
|
bool "Support standalone nSIM & Free nSIM"
|
2014-07-30 13:08:14 +08:00
|
|
|
|
2017-03-21 19:49:48 +08:00
|
|
|
config TARGET_AXS101
|
|
|
|
bool "Support Synopsys Designware SDP board AXS101"
|
2018-12-01 05:13:25 +08:00
|
|
|
select BOUNCE_BUFFER if CMD_NAND
|
2017-03-21 19:49:48 +08:00
|
|
|
|
|
|
|
config TARGET_AXS103
|
|
|
|
bool "Support Synopsys Designware SDP board AXS103"
|
2018-12-01 05:13:25 +08:00
|
|
|
select BOUNCE_BUFFER if CMD_NAND
|
2014-07-30 13:08:14 +08:00
|
|
|
|
2018-10-18 14:54:58 +08:00
|
|
|
config TARGET_EMSDP
|
|
|
|
bool "Synopsys EM Software Development Platform"
|
2018-05-28 20:27:43 +08:00
|
|
|
select CPU_ARCEM6
|
|
|
|
|
2016-11-25 21:23:43 +08:00
|
|
|
config TARGET_HSDK
|
|
|
|
bool "Support Synpsys HS DevelopmentKit board"
|
|
|
|
|
arc: Add support for IoT development kit
The DesignWare ARC IoT Development Kit is a versatile platform
that includes the necessary hardware and software to accelerate
software development and debugging of sensor fusion,
voice recognition and face detection designs.
More information is avaialble here [1] and here [2].
The board is based on real silicon with
ARC EM9D-based Data Fusion IP Subsystem.
It sports a rich set of I/O including
* DW USB OTG
* DW MobileStorage (used for micro SD-card)
* GPIO
* multiple serial interface including DW APB UART
* ADC, PWM and eFlash, SRAM and SPI Flash memory
* Real-Time Clock (RTC)
* Bluetooth module with worldwide regulatory compliance
(FCC, IC, CE, ETSI, TELEC)
* On-board 9-axis sensor (gyro, accelerometer and compass)
Extensible with Arduino, Pmod, mikroBUS connectors and a 2x18
extension header.
One of the most interesting features for developers is built-in
Digilent USB JTAG probe so only micro-USB cable is needed!
[1] https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit
[2] https://www.synopsys.com/dw/doc.php/ds/cc/iot_dev_kit.pdf
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-25 02:37:14 +08:00
|
|
|
config TARGET_IOT_DEVKIT
|
|
|
|
bool "Synopsys Brite IoT Development kit"
|
|
|
|
select CPU_ARCEM6
|
|
|
|
|
2014-07-30 13:08:14 +08:00
|
|
|
endchoice
|
|
|
|
|
|
|
|
source "board/abilis/tb100/Kconfig"
|
|
|
|
source "board/synopsys/Kconfig"
|
2016-08-04 20:00:35 +08:00
|
|
|
source "board/synopsys/axs10x/Kconfig"
|
2018-10-18 14:54:58 +08:00
|
|
|
source "board/synopsys/emsdp/Kconfig"
|
2016-11-25 21:23:43 +08:00
|
|
|
source "board/synopsys/hsdk/Kconfig"
|
arc: Add support for IoT development kit
The DesignWare ARC IoT Development Kit is a versatile platform
that includes the necessary hardware and software to accelerate
software development and debugging of sensor fusion,
voice recognition and face detection designs.
More information is avaialble here [1] and here [2].
The board is based on real silicon with
ARC EM9D-based Data Fusion IP Subsystem.
It sports a rich set of I/O including
* DW USB OTG
* DW MobileStorage (used for micro SD-card)
* GPIO
* multiple serial interface including DW APB UART
* ADC, PWM and eFlash, SRAM and SPI Flash memory
* Real-Time Clock (RTC)
* Bluetooth module with worldwide regulatory compliance
(FCC, IC, CE, ETSI, TELEC)
* On-board 9-axis sensor (gyro, accelerometer and compass)
Extensible with Arduino, Pmod, mikroBUS connectors and a 2x18
extension header.
One of the most interesting features for developers is built-in
Digilent USB JTAG probe so only micro-USB cable is needed!
[1] https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit
[2] https://www.synopsys.com/dw/doc.php/ds/cc/iot_dev_kit.pdf
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-25 02:37:14 +08:00
|
|
|
source "board/synopsys/iot_devkit/Kconfig"
|
2014-07-30 13:08:14 +08:00
|
|
|
|
|
|
|
endmenu
|