2018-11-15 10:07:49 +08:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* MediaTek BootROM header definitions
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*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _MTK_IMAGE_H
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#define _MTK_IMAGE_H
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2019-10-27 20:19:41 +08:00
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/* Device header definitions, all fields are little-endian */
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2018-11-15 10:07:49 +08:00
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/* Header for NOR/SD/eMMC */
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union gen_boot_header {
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struct {
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char name[12];
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2019-10-27 20:19:41 +08:00
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uint32_t version;
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uint32_t size;
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2018-11-15 10:07:49 +08:00
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};
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uint8_t pad[0x200];
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};
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#define EMMC_BOOT_NAME "EMMC_BOOT"
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#define SF_BOOT_NAME "SF_BOOT"
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#define SDMMC_BOOT_NAME "SDMMC_BOOT"
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/* BootROM layout header */
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struct brom_layout_header {
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char name[8];
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2019-10-27 20:19:41 +08:00
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uint32_t version;
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uint32_t header_size;
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uint32_t total_size;
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uint32_t magic;
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uint32_t type;
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uint32_t header_size_2;
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uint32_t total_size_2;
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uint32_t unused;
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2018-11-15 10:07:49 +08:00
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};
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#define BRLYT_NAME "BRLYT"
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#define BRLYT_MAGIC 0x42424242
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enum brlyt_img_type {
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BRLYT_TYPE_INVALID = 0,
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BRLYT_TYPE_NAND = 0x10002,
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BRLYT_TYPE_EMMC = 0x10005,
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BRLYT_TYPE_NOR = 0x10007,
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BRLYT_TYPE_SDMMC = 0x10008,
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BRLYT_TYPE_SNAND = 0x10009
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};
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/* Combined device header for NOR/SD/eMMC */
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struct gen_device_header {
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union gen_boot_header boot;
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union {
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struct brom_layout_header brlyt;
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uint8_t brlyt_pad[0x400];
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};
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};
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/* BootROM header definitions */
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struct gfh_common_header {
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uint8_t magic[3];
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uint8_t version;
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2019-10-27 20:19:41 +08:00
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uint16_t size;
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uint16_t type;
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2018-11-15 10:07:49 +08:00
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};
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#define GFH_HEADER_MAGIC "MMM"
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#define GFH_TYPE_FILE_INFO 0
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#define GFH_TYPE_BL_INFO 1
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#define GFH_TYPE_BROM_CFG 7
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#define GFH_TYPE_BL_SEC_KEY 3
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#define GFH_TYPE_ANTI_CLONE 2
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#define GFH_TYPE_BROM_SEC_CFG 8
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struct gfh_file_info {
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struct gfh_common_header gfh;
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char name[12];
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uint32_t unused;
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uint16_t file_type;
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2018-11-15 10:07:49 +08:00
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uint8_t flash_type;
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uint8_t sig_type;
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2019-10-27 20:19:41 +08:00
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uint32_t load_addr;
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uint32_t total_size;
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uint32_t max_size;
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uint32_t hdr_size;
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uint32_t sig_size;
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uint32_t jump_offset;
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uint32_t processed;
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2018-11-15 10:07:49 +08:00
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};
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#define GFH_FILE_INFO_NAME "FILE_INFO"
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#define GFH_FLASH_TYPE_GEN 5
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#define GFH_FLASH_TYPE_NAND 2
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#define GFH_SIG_TYPE_NONE 0
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#define GFH_SIG_TYPE_SHA256 1
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struct gfh_bl_info {
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struct gfh_common_header gfh;
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2019-10-27 20:19:41 +08:00
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uint32_t attr;
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2018-11-15 10:07:49 +08:00
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};
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struct gfh_brom_cfg {
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struct gfh_common_header gfh;
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2019-10-27 20:19:41 +08:00
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uint32_t cfg_bits;
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uint32_t usbdl_by_auto_detect_timeout_ms;
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2020-10-17 01:52:37 +08:00
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uint8_t unused[0x45];
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uint8_t jump_bl_arm64;
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uint8_t unused2[2];
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2019-10-27 20:19:41 +08:00
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uint32_t usbdl_by_kcol0_timeout_ms;
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uint32_t usbdl_by_flag_timeout_ms;
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2018-11-15 10:07:49 +08:00
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uint32_t pad;
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};
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#define GFH_BROM_CFG_USBDL_BY_AUTO_DETECT_TIMEOUT_EN 0x02
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#define GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS 0x10
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#define GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN 0x80
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#define GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN 0x100
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2020-10-17 01:52:37 +08:00
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#define GFH_BROM_CFG_JUMP_BL_ARM64_EN 0x1000
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#define GFH_BROM_CFG_JUMP_BL_ARM64 0x64
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2018-11-15 10:07:49 +08:00
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struct gfh_bl_sec_key {
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struct gfh_common_header gfh;
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uint8_t pad[0x20c];
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};
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struct gfh_anti_clone {
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struct gfh_common_header gfh;
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uint8_t ac_b2k;
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uint8_t ac_b2c;
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uint16_t pad;
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2019-10-27 20:19:41 +08:00
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uint32_t ac_offset;
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uint32_t ac_len;
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2018-11-15 10:07:49 +08:00
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};
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struct gfh_brom_sec_cfg {
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struct gfh_common_header gfh;
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2019-10-27 20:19:41 +08:00
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uint32_t cfg_bits;
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2018-11-15 10:07:49 +08:00
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char customer_name[0x20];
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2019-10-27 20:19:41 +08:00
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uint32_t pad;
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2018-11-15 10:07:49 +08:00
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};
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#define BROM_SEC_CFG_JTAG_EN 1
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#define BROM_SEC_CFG_UART_EN 2
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struct gfh_header {
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struct gfh_file_info file_info;
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struct gfh_bl_info bl_info;
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struct gfh_brom_cfg brom_cfg;
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struct gfh_bl_sec_key bl_sec_key;
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struct gfh_anti_clone anti_clone;
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struct gfh_brom_sec_cfg brom_sec_cfg;
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};
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/* LK image header */
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union lk_hdr {
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struct {
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2019-10-27 20:19:41 +08:00
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uint32_t magic;
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uint32_t size;
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2018-11-15 10:07:49 +08:00
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char name[32];
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2019-10-27 20:19:41 +08:00
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uint32_t loadaddr;
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uint32_t mode;
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2018-11-15 10:07:49 +08:00
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};
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uint8_t data[512];
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};
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#define LK_PART_MAGIC 0x58881688
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2022-05-20 11:24:10 +08:00
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/* MT7621 NAND SPL image header */
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#define MT7621_IH_NMLEN 12
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#define MT7621_IH_CRC_POLYNOMIAL 0x04c11db7
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struct mt7621_nand_header {
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char ih_name[MT7621_IH_NMLEN];
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uint32_t nand_ac_timing;
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uint32_t ih_stage_offset;
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uint32_t ih_bootloader_offset;
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uint32_t nand_info_1_data;
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uint32_t crc;
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};
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struct mt7621_stage1_header {
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uint32_t jump_insn[2];
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uint32_t ep;
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uint32_t stage_size;
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uint32_t has_stage2;
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uint32_t next_ep;
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uint32_t next_size;
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uint32_t next_offset;
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};
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2018-11-15 10:07:49 +08:00
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#endif /* _MTK_IMAGE_H */
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