2013-07-30 02:15:16 +08:00
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/*
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2015-09-02 14:09:45 +08:00
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* (C) Copyright 2013 Xilinx, Inc.
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2015-06-27 03:21:31 +08:00
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* (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
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2013-07-30 02:15:16 +08:00
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*
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* Xilinx Zynq PS SPI controller driver (master mode only)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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2015-06-27 03:21:31 +08:00
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#include <dm.h>
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2013-07-30 02:15:16 +08:00
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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2015-06-27 03:21:34 +08:00
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DECLARE_GLOBAL_DATA_PTR;
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2013-07-30 02:15:16 +08:00
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/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
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2015-10-22 23:10:16 +08:00
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#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
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#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
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2015-10-22 23:36:37 +08:00
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#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
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#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
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2015-10-22 23:10:16 +08:00
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#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
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#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
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#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
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#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
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#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
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2015-10-22 23:36:37 +08:00
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#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
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2015-10-22 23:10:16 +08:00
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#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
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2013-07-30 02:15:16 +08:00
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2015-08-17 20:55:03 +08:00
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#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
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#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
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#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
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2013-07-30 02:15:16 +08:00
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#define ZYNQ_SPI_FIFO_DEPTH 128
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#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
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#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
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#endif
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/* zynq spi register set */
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struct zynq_spi_regs {
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u32 cr; /* 0x00 */
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u32 isr; /* 0x04 */
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u32 ier; /* 0x08 */
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u32 idr; /* 0x0C */
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u32 imr; /* 0x10 */
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u32 enr; /* 0x14 */
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u32 dr; /* 0x18 */
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u32 txdr; /* 0x1C */
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u32 rxdr; /* 0x20 */
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};
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2015-06-27 03:21:31 +08:00
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/* zynq spi platform data */
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struct zynq_spi_platdata {
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struct zynq_spi_regs *regs;
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u32 frequency; /* input frequency */
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2013-07-30 02:15:16 +08:00
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u32 speed_hz;
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};
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2015-06-27 03:21:31 +08:00
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/* zynq spi priv */
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struct zynq_spi_priv {
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struct zynq_spi_regs *regs;
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2015-08-17 21:01:39 +08:00
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u8 cs;
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2015-06-27 03:21:31 +08:00
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u8 mode;
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u8 fifo_depth;
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u32 freq; /* required frequency */
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};
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2013-07-30 02:15:16 +08:00
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2015-06-27 03:21:31 +08:00
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static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
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2013-07-30 02:15:16 +08:00
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{
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2015-06-27 03:21:31 +08:00
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struct zynq_spi_platdata *plat = bus->platdata;
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2015-06-27 03:21:34 +08:00
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const void *blob = gd->fdt_blob;
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int node = bus->of_offset;
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2015-08-11 22:33:29 +08:00
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plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus);
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2015-06-27 03:21:31 +08:00
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2015-06-27 03:21:34 +08:00
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/* FIXME: Use 250MHz as a suitable default */
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plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
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250000000);
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2015-06-27 03:21:31 +08:00
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plat->speed_hz = plat->frequency / 2;
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2015-07-21 13:54:11 +08:00
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debug("%s: regs=%p max-frequency=%d\n", __func__,
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2015-06-27 03:21:34 +08:00
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plat->regs, plat->frequency);
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2015-06-27 03:21:31 +08:00
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return 0;
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}
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static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
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{
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struct zynq_spi_regs *regs = priv->regs;
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2013-07-30 02:15:16 +08:00
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u32 confr;
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/* Disable SPI */
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2016-09-01 18:51:27 +08:00
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confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
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writel(~confr, ®s->enr);
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2013-07-30 02:15:16 +08:00
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/* Disable Interrupts */
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2015-06-27 03:21:31 +08:00
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writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->idr);
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2013-07-30 02:15:16 +08:00
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/* Clear RX FIFO */
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2015-06-27 03:21:31 +08:00
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while (readl(®s->isr) &
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2013-07-30 02:15:16 +08:00
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ZYNQ_SPI_IXR_RXNEMPTY_MASK)
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2015-06-27 03:21:31 +08:00
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readl(®s->rxdr);
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2013-07-30 02:15:16 +08:00
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/* Clear Interrupts */
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2015-06-27 03:21:31 +08:00
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writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->isr);
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2013-07-30 02:15:16 +08:00
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/* Manual slave select and Auto start */
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confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
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ZYNQ_SPI_CR_MSTREN_MASK;
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confr &= ~ZYNQ_SPI_CR_MSA_MASK;
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2015-06-27 03:21:31 +08:00
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writel(confr, ®s->cr);
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2013-07-30 02:15:16 +08:00
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/* Enable SPI */
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2015-06-27 03:21:31 +08:00
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writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
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2013-07-30 02:15:16 +08:00
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}
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2015-06-27 03:21:31 +08:00
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static int zynq_spi_probe(struct udevice *bus)
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2013-07-30 02:15:16 +08:00
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{
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2015-06-27 03:21:31 +08:00
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struct zynq_spi_platdata *plat = dev_get_platdata(bus);
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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priv->regs = plat->regs;
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priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
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/* init the zynq spi hw */
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zynq_spi_init_hw(priv);
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return 0;
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2013-07-30 02:15:16 +08:00
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}
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2015-08-17 21:01:39 +08:00
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static void spi_cs_activate(struct udevice *dev)
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2013-07-30 02:15:16 +08:00
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{
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2015-06-27 03:21:31 +08:00
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struct udevice *bus = dev->parent;
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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2013-07-30 02:15:16 +08:00
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u32 cr;
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2015-06-27 03:21:31 +08:00
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clrbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK);
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cr = readl(®s->cr);
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2013-07-30 02:15:16 +08:00
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/*
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* CS cal logic: CS[13:10]
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* xxx0 - cs0
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* xx01 - cs1
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* x011 - cs2
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*/
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2015-08-17 21:01:39 +08:00
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cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
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2015-06-27 03:21:31 +08:00
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writel(cr, ®s->cr);
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2013-07-30 02:15:16 +08:00
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}
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2015-06-27 03:21:31 +08:00
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static void spi_cs_deactivate(struct udevice *dev)
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2013-07-30 02:15:16 +08:00
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{
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2015-06-27 03:21:31 +08:00
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struct udevice *bus = dev->parent;
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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2013-07-30 02:15:16 +08:00
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2015-06-27 03:21:31 +08:00
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setbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK);
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2013-07-30 02:15:16 +08:00
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}
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2015-06-27 03:21:31 +08:00
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static int zynq_spi_claim_bus(struct udevice *dev)
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2013-07-30 02:15:16 +08:00
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{
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2015-06-27 03:21:31 +08:00
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struct udevice *bus = dev->parent;
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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2013-07-30 02:15:16 +08:00
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2015-06-27 03:21:31 +08:00
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writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
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2013-07-30 02:15:16 +08:00
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2015-06-27 03:21:31 +08:00
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return 0;
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2013-07-30 02:15:16 +08:00
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}
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2015-06-27 03:21:31 +08:00
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static int zynq_spi_release_bus(struct udevice *dev)
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2013-07-30 02:15:16 +08:00
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{
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2015-06-27 03:21:31 +08:00
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struct udevice *bus = dev->parent;
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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2016-09-01 18:51:27 +08:00
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u32 confr;
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2013-07-30 02:15:16 +08:00
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2016-09-01 18:51:27 +08:00
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confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
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writel(~confr, ®s->enr);
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2013-07-30 02:15:16 +08:00
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return 0;
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}
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2015-06-27 03:21:31 +08:00
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static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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2013-07-30 02:15:16 +08:00
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{
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2015-06-27 03:21:31 +08:00
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struct udevice *bus = dev->parent;
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
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2013-07-30 02:15:16 +08:00
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u32 len = bitlen / 8;
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u32 tx_len = len, rx_len = len, tx_tvl;
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const u8 *tx_buf = dout;
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u8 *rx_buf = din, buf;
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u32 ts, status;
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debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
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2015-06-27 03:21:31 +08:00
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bus->seq, slave_plat->cs, bitlen, len, flags);
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2013-07-30 02:15:16 +08:00
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if (bitlen % 8) {
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debug("spi_xfer: Non byte aligned SPI transfer\n");
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return -1;
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}
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2015-08-17 21:01:39 +08:00
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priv->cs = slave_plat->cs;
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2013-07-30 02:15:16 +08:00
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if (flags & SPI_XFER_BEGIN)
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2015-08-17 21:01:39 +08:00
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spi_cs_activate(dev);
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2013-07-30 02:15:16 +08:00
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while (rx_len > 0) {
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/* Write the data into TX FIFO - tx threshold is fifo_depth */
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tx_tvl = 0;
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2015-06-27 03:21:31 +08:00
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while ((tx_tvl < priv->fifo_depth) && tx_len) {
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2013-07-30 02:15:16 +08:00
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if (tx_buf)
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buf = *tx_buf++;
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else
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buf = 0;
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2015-06-27 03:21:31 +08:00
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writel(buf, ®s->txdr);
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2013-07-30 02:15:16 +08:00
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tx_len--;
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tx_tvl++;
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}
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/* Check TX FIFO completion */
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ts = get_timer(0);
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2015-06-27 03:21:31 +08:00
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status = readl(®s->isr);
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2013-07-30 02:15:16 +08:00
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while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
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if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
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printf("spi_xfer: Timeout! TX FIFO not full\n");
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return -1;
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}
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2015-06-27 03:21:31 +08:00
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status = readl(®s->isr);
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2013-07-30 02:15:16 +08:00
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}
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/* Read the data from RX FIFO */
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2015-06-27 03:21:31 +08:00
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status = readl(®s->isr);
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2016-07-31 05:28:24 +08:00
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while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
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2015-06-27 03:21:31 +08:00
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buf = readl(®s->rxdr);
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2013-07-30 02:15:16 +08:00
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if (rx_buf)
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*rx_buf++ = buf;
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2015-06-27 03:21:31 +08:00
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status = readl(®s->isr);
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2013-07-30 02:15:16 +08:00
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rx_len--;
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}
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}
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if (flags & SPI_XFER_END)
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2015-06-27 03:21:31 +08:00
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spi_cs_deactivate(dev);
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return 0;
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}
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static int zynq_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct zynq_spi_platdata *plat = bus->platdata;
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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uint32_t confr;
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u8 baud_rate_val = 0;
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if (speed > plat->frequency)
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speed = plat->frequency;
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/* Set the clock frequency */
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confr = readl(®s->cr);
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if (speed == 0) {
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/* Set baudrate x8, if the freq is 0 */
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baud_rate_val = 0x2;
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} else if (plat->speed_hz != speed) {
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2015-08-17 20:55:03 +08:00
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while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
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2015-06-27 03:21:31 +08:00
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((plat->frequency /
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(2 << baud_rate_val)) > speed))
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baud_rate_val++;
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plat->speed_hz = speed / (2 << baud_rate_val);
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}
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2015-08-17 20:57:47 +08:00
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confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
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2015-08-17 20:55:03 +08:00
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confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
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2015-06-27 03:21:31 +08:00
|
|
|
|
|
|
|
writel(confr, ®s->cr);
|
|
|
|
priv->freq = speed;
|
|
|
|
|
2015-09-08 04:08:50 +08:00
|
|
|
debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
|
|
|
|
priv->regs, priv->freq);
|
2015-06-27 03:21:31 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int zynq_spi_set_mode(struct udevice *bus, uint mode)
|
|
|
|
{
|
|
|
|
struct zynq_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynq_spi_regs *regs = priv->regs;
|
|
|
|
uint32_t confr;
|
|
|
|
|
|
|
|
/* Set the SPI Clock phase and polarities */
|
|
|
|
confr = readl(®s->cr);
|
|
|
|
confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
|
|
|
|
|
2015-09-08 04:08:50 +08:00
|
|
|
if (mode & SPI_CPHA)
|
2015-06-27 03:21:31 +08:00
|
|
|
confr |= ZYNQ_SPI_CR_CPHA_MASK;
|
2015-09-08 04:08:50 +08:00
|
|
|
if (mode & SPI_CPOL)
|
2015-06-27 03:21:31 +08:00
|
|
|
confr |= ZYNQ_SPI_CR_CPOL_MASK;
|
|
|
|
|
|
|
|
writel(confr, ®s->cr);
|
|
|
|
priv->mode = mode;
|
|
|
|
|
|
|
|
debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
|
2013-07-30 02:15:16 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2015-06-27 03:21:31 +08:00
|
|
|
|
|
|
|
static const struct dm_spi_ops zynq_spi_ops = {
|
|
|
|
.claim_bus = zynq_spi_claim_bus,
|
|
|
|
.release_bus = zynq_spi_release_bus,
|
|
|
|
.xfer = zynq_spi_xfer,
|
|
|
|
.set_speed = zynq_spi_set_speed,
|
|
|
|
.set_mode = zynq_spi_set_mode,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct udevice_id zynq_spi_ids[] = {
|
2015-07-22 16:47:33 +08:00
|
|
|
{ .compatible = "xlnx,zynq-spi-r1p6" },
|
2015-12-07 20:06:54 +08:00
|
|
|
{ .compatible = "cdns,spi-r1p6" },
|
2015-06-27 03:21:31 +08:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(zynq_spi) = {
|
|
|
|
.name = "zynq_spi",
|
|
|
|
.id = UCLASS_SPI,
|
|
|
|
.of_match = zynq_spi_ids,
|
|
|
|
.ops = &zynq_spi_ops,
|
|
|
|
.ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
|
|
|
|
.platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
|
|
|
|
.priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
|
|
|
|
.probe = zynq_spi_probe,
|
|
|
|
};
|