2010-04-30 11:34:16 +08:00
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/*
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* Altera SPI driver
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*
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* based on bfin_spi.c
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* Copyright (c) 2005-2008 Analog Devices Inc.
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* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
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*
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2013-10-14 16:01:24 +08:00
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* SPDX-License-Identifier: GPL-2.0+
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2010-04-30 11:34:16 +08:00
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <spi.h>
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2014-10-23 03:55:58 +08:00
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struct altera_spi_regs {
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u32 rxdata;
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u32 txdata;
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u32 status;
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u32 control;
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u32 _reserved;
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u32 slave_sel;
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};
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2010-04-30 11:34:16 +08:00
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2014-10-23 03:55:59 +08:00
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#define ALTERA_SPI_STATUS_ROE_MSK (1 << 3)
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#define ALTERA_SPI_STATUS_TOE_MSK (1 << 4)
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#define ALTERA_SPI_STATUS_TMT_MSK (1 << 5)
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#define ALTERA_SPI_STATUS_TRDY_MSK (1 << 6)
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#define ALTERA_SPI_STATUS_RRDY_MSK (1 << 7)
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#define ALTERA_SPI_STATUS_E_MSK (1 << 8)
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2010-04-30 11:34:16 +08:00
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2014-10-23 03:55:59 +08:00
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#define ALTERA_SPI_CONTROL_IROE_MSK (1 << 3)
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#define ALTERA_SPI_CONTROL_ITOE_MSK (1 << 4)
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#define ALTERA_SPI_CONTROL_ITRDY_MSK (1 << 6)
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#define ALTERA_SPI_CONTROL_IRRDY_MSK (1 << 7)
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#define ALTERA_SPI_CONTROL_IE_MSK (1 << 8)
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#define ALTERA_SPI_CONTROL_SSO_MSK (1 << 10)
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2010-04-30 11:34:16 +08:00
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#ifndef CONFIG_SYS_ALTERA_SPI_LIST
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#define CONFIG_SYS_ALTERA_SPI_LIST { CONFIG_SYS_SPI_BASE }
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#endif
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static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST;
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struct altera_spi_slave {
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2014-10-23 03:55:58 +08:00
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struct spi_slave slave;
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struct altera_spi_regs *regs;
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2010-04-30 11:34:16 +08:00
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};
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#define to_altera_spi_slave(s) container_of(s, struct altera_spi_slave, slave)
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2014-10-23 03:56:00 +08:00
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__weak int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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2010-04-30 11:34:16 +08:00
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{
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return bus < ARRAY_SIZE(altera_spi_base_list) && cs < 32;
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}
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2014-10-23 03:56:00 +08:00
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__weak void spi_cs_activate(struct spi_slave *slave)
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2010-04-30 11:34:16 +08:00
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{
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struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
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2014-10-23 03:55:58 +08:00
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writel(1 << slave->cs, &altspi->regs->slave_sel);
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writel(ALTERA_SPI_CONTROL_SSO_MSK, &altspi->regs->control);
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2010-04-30 11:34:16 +08:00
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}
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2014-10-23 03:56:00 +08:00
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__weak void spi_cs_deactivate(struct spi_slave *slave)
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2010-04-30 11:34:16 +08:00
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{
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struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
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2014-10-23 03:55:58 +08:00
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writel(0, &altspi->regs->control);
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writel(0, &altspi->regs->slave_sel);
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2010-04-30 11:34:16 +08:00
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}
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void spi_init(void)
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{
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}
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2010-12-27 09:30:17 +08:00
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void spi_set_speed(struct spi_slave *slave, uint hz)
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{
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/* altera spi core does not support programmable speed */
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}
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2010-04-30 11:34:16 +08:00
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct altera_spi_slave *altspi;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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2013-03-19 03:23:40 +08:00
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altspi = spi_alloc_slave(struct altera_spi_slave, bus, cs);
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2010-04-30 11:34:16 +08:00
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if (!altspi)
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return NULL;
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2014-10-23 03:55:58 +08:00
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altspi->regs = (struct altera_spi_regs *)altera_spi_base_list[bus];
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2014-10-23 03:56:00 +08:00
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debug("%s: bus:%i cs:%i base:%p\n", __func__, bus, cs, altspi->regs);
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2010-04-30 11:34:16 +08:00
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return &altspi->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
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free(altspi);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
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2014-10-23 03:55:58 +08:00
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writel(0, &altspi->regs->control);
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writel(0, &altspi->regs->slave_sel);
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2010-04-30 11:34:16 +08:00
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
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2014-10-23 03:55:58 +08:00
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writel(0, &altspi->regs->slave_sel);
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2010-04-30 11:34:16 +08:00
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}
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#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
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# define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
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#endif
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
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/* assume spi core configured to do 8 bit transfers */
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uint bytes = bitlen / 8;
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const uchar *txp = dout;
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uchar *rxp = din;
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2014-10-23 03:56:01 +08:00
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uint32_t reg, start;
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2010-04-30 11:34:16 +08:00
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debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
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2014-10-23 03:56:00 +08:00
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slave->bus, slave->cs, bitlen, bytes, flags);
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2010-04-30 11:34:16 +08:00
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if (bitlen == 0)
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goto done;
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if (bitlen % 8) {
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flags |= SPI_XFER_END;
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goto done;
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}
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/* empty read buffer */
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2014-10-23 03:55:58 +08:00
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if (readl(&altspi->regs->status) & ALTERA_SPI_STATUS_RRDY_MSK)
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readl(&altspi->regs->rxdata);
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2014-10-23 03:56:00 +08:00
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2010-04-30 11:34:16 +08:00
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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while (bytes--) {
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uchar d = txp ? *txp++ : CONFIG_ALTERA_SPI_IDLE_VAL;
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2014-10-23 03:56:00 +08:00
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2010-04-30 11:34:16 +08:00
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debug("%s: tx:%x ", __func__, d);
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2014-10-23 03:55:58 +08:00
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writel(d, &altspi->regs->txdata);
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2014-10-23 03:56:00 +08:00
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2014-10-23 03:56:01 +08:00
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start = get_timer(0);
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while (1) {
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reg = readl(&altspi->regs->status);
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if (reg & ALTERA_SPI_STATUS_RRDY_MSK)
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break;
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if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
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printf("%s: Transmission timed out!\n", __func__);
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goto done;
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}
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}
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2014-10-23 03:56:00 +08:00
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2014-10-23 03:55:58 +08:00
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d = readl(&altspi->regs->rxdata);
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2010-04-30 11:34:16 +08:00
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if (rxp)
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*rxp++ = d;
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2014-10-23 03:56:00 +08:00
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2010-04-30 11:34:16 +08:00
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debug("rx:%x\n", d);
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}
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2014-10-23 03:56:00 +08:00
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done:
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2010-04-30 11:34:16 +08:00
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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return 0;
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}
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