mirrors/u-boot
0
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2024-12-11 21:53:29 +08:00
Code Issues Packages Projects Releases Wiki Activity
72d7a302f6
u-boot/configs/phycore-imx8mm_defconfig

134 lines
3.3 KiB
Plaintext
Raw Normal View History

board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-01 20:19:22 +08:00
CONFIG_SYS_MALLOC_LEN=0x2000000
Rename GPIO_SUPPORT to GPIO Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-11 11:14:30 +08:00
CONFIG_SPL_GPIO=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-06-28 22:17:29 +08:00
CONFIG_DEFAULT_DEVICE_TREE="phycore-imx8mm"
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PHYCORE_IMX8MM=y
mmc: Rename MMC_SUPPORT to MMC Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> [trini: Fixup some incorrect renames] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-09 02:20:09 +08:00
CONFIG_SPL_MMC=y
serial: Rename SERIAL_SUPPORT to SERIAL Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-09 02:20:12 +08:00
CONFIG_SPL_SERIAL=y
Rename DRIVERS_MISC_SUPPORT to DRIVERS_MISC Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-11 11:14:31 +08:00
CONFIG_SPL_DRIVERS_MISC=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3E0000
Convert CONFIG_SYS_LOAD_ADDR to Kconfig Now that we have consistent usage, migrate this symbol to Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-23 22:25:31 +08:00
CONFIG_SYS_LOAD_ADDR=0x40480000
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
board: phytec: imx8mm-phycore: Switch to binman Use binman for image creation. Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-06 17:56:54 +08:00
# CONFIG_USE_SPL_FIT_GENERATOR is not set
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_OF_SYSTEM_SETUP=y
Convert CONFIG_USE_BOOTCOMMAND et al to Kconfig This converts the following to Kconfig: CONFIG_USE_BOOTCOMMAND CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND CONFIG_NFSBOOTCOMMAND Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-10 22:11:40 +08:00
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
Convert CONFIG_SPL_PAD_TO et al to Kconfig This converts the following to Kconfig: CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE CONFIG_TPL_PAD_TO CONFIG_TPL_MAX_SIZE Note that we need to make TPL_MAX_SIZE be hex, and so move and convert the existing places. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-17 05:20:26 +08:00
CONFIG_SPL_MAX_SIZE=0x25000
Convert CONFIG_SPL_BSS_START_ADDR to Kconfig This converts the following to Kconfig: CONFIG_SPL_BSS_START_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-27 22:19:45 +08:00
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
Convert CONFIG_SPL_BSS_MAX_SIZE et al to Kconfig This converts the following to Kconfig: CONFIG_SPL_BSS_MAX_SIZE CONFIG_SPL_MAX_FOOTPRINT Note that the da850evm platforms were violating the "only use one" rule here, and so now hard-code their BSS limit. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-20 03:09:22 +08:00
CONFIG_SPL_BSS_MAX_SIZE=0x2000
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_SPL_BOARD_INIT=y
Convert CONFIG_SPL_STACK to Kconfig This converts the following to Kconfig: CONFIG_SPL_STACK Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-27 01:13:21 +08:00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x920000
Convert CONFIG_SYS_SPL_MALLOC_SIZE et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_SPL_MALLOC_START We introduce a default value here as well, and CONFIG_SYS_SPL_MALLOC to control if we have a malloc pool or not. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-28 00:48:32 +08:00
CONFIG_SYS_SPL_MALLOC=y
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
Convert CONFIG_CONS_INDEX et al to Kconfig This converts the following to Kconfig: CONFIG_CONS_INDEX CONFIG_DEBUG_UART_CLOCK CONFIG_FSL_TZPC_BP147 CONFIG_GENERIC_ATMEL_MCI CONFIG_IDENT_STRING CONFIG_LIBATA CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_LPC32XX_GPIO CONFIG_MP CONFIG_MPC8XXX_GPIO CONFIG_MTD_PARTITIONS CONFIG_MVGBE CONFIG_MXC_GPIO CONFIG_NR_DRAM_BANKS CONFIG_OF_BOARD_SETUP CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_OF_SYSTEM_SETUP CONFIG_PREBOOT CONFIG_ROCKCHIP_SERIAL CONFIG_RTC_ENABLE_32KHZ_OUTPUT CONFIG_RTC_MV CONFIG_SCSI_AHCI CONFIG_SF_DEFAULT_BUS CONFIG_SF_DEFAULT_CS CONFIG_SF_DEFAULT_SPEED CONFIG_SOFT_SPI CONFIG_SPI_FLASH_EON CONFIG_SPI_FLASH_MACRONIX CONFIG_SPI_FLASH_MTD CONFIG_SPI_FLASH_SPANSION CONFIG_SPI_FLASH_SST CONFIG_SPI_FLASH_STMICRO CONFIG_SUPPORT_RAW_INITRD CONFIG_SYS_ARCH_TIMER CONFIG_SYS_BOARD CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE CONFIG_SYS_DCACHE_OFF CONFIG_SYS_FDT_SAVE_ADDRESS CONFIG_SYS_FLASH_CFI CONFIG_SYS_FSL_ERRATUM_ESDHC135 CONFIG_SYS_HAS_SERDES CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_LITTLE_ENDIAN CONFIG_SYS_LOAD_ADDR CONFIG_SYS_MMCSD_FS_BOOT_PARTITION CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR CONFIG_SYS_NS16550 CONFIG_SYS_PLLFIN CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_TIMER_SYS_TICK_CH CONFIG_USB_EHCI_FSL CONFIG_U_QE CONFIG_VERSION_VARIABLE Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-12 03:55:51 +08:00
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
i2c: Rename SPL/TPL_I2C_SUPPORT to I2C Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-11 11:14:36 +08:00
CONFIG_SPL_I2C=y
Rename SPL_POWER_SUPPORT to SPL_POWER Rename this option so that CONFIG_IS_ENABLED can be used with it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-11 11:14:24 +08:00
CONFIG_SPL_POWER=y
board: phytec: phycore-imx8mm: Add SPI-NOR flash support Adds SPI-NOR flash support to erase, read and write in bootloader. Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-06 17:56:52 +08:00
CONFIG_SPL_SPI_FLASH_MTD=y
Rename SPL_WATCHDOG_SUPPORT to SPL_WATCHDOG Rename this option so that CONFIG_IS_ENABLED can be used with it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-11 11:14:28 +08:00
CONFIG_SPL_WATCHDOG=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
Convert CONFIG_SYS_MAXARGS to Kconfig This converts the following to Kconfig: CONFIG_SYS_MAXARGS Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-12 04:21:06 +08:00
CONFIG_SYS_MAXARGS=64
Convert CONFIG_SYS_CBSIZE to Kconfig This converts the following to Kconfig: CONFIG_SYS_CBSIZE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-12 06:01:06 +08:00
CONFIG_SYS_CBSIZE=2048
Convert CONFIG_SYS_PBSIZE to Kconfig This converts the following to Kconfig: CONFIG_SYS_PBSIZE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-12 05:38:09 +08:00
CONFIG_SYS_PBSIZE=2074
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_EEPROM=y
Convert CONFIG_SYS_I2C_EEPROM_ADDR et al to Kconfig - Rename usages of CONFIG_SYS_DEF_EEPROM_ADDR to CONFIG_SYS_I2C_EEPROM_ADDR based on current usage. - Convert CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SYS_I2C_EEPROM_BUS, CONFIG_CONFIG_SYS_EEPROM_SIZE CONFIG_SYS_EEPROM_PAGE_WRITE_BITS and CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS to Kconfig. We move these symbols around a bit and add appropriate dependencies to them. In some cases, we now add a correct default value as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-18 05:59:45 +08:00
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_EEPROM_SIZE=4096
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
configs: phycore-imx8mm_defconfig: Enable clk command Enable clk command to dump clock tree. Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-06 17:56:53 +08:00
CONFIG_CMD_CLK=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
board: phytec: phycore-imx8mm: Add SPI-NOR flash support Adds SPI-NOR flash support to erase, read and write in bootloader. Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-06 17:56:52 +08:00
CONFIG_CMD_SF_TEST=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x51
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
Convert CONFIG_FSL_USDHC to Kconfig This converts the following to Kconfig: CONFIG_FSL_USDHC Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-08 11:59:37 +08:00
CONFIG_FSL_USDHC=y
board: phytec: phycore-imx8mm: Add SPI-NOR flash support Adds SPI-NOR flash support to erase, read and write in bootloader. Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-06 17:56:52 +08:00
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
CONFIG_SF_DEFAULT_SPEED=80000000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_PHYLIB=y
CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
imx: imx8m[m/p]_phycore: Enable DM_SERIAL Enable CONFIG_DM_SERIAL. uart and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work. Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-11 20:20:58 +08:00
CONFIG_DM_SERIAL=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_MXC_UART=y
board: phytec: phycore-imx8mm: Add SPI-NOR flash support Adds SPI-NOR flash support to erase, read and write in bootloader. Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-06 17:56:52 +08:00
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 15:55:53 +08:00
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_WATCHDOG=y
Reference in New Issue Copy Permalink