mirrors/u-boot
0
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2024-12-02 00:53:29 +08:00
Code Issues Packages Projects Releases Wiki Activity
6c49c22846
u-boot/drivers/pch/pch-uclass.c

69 lines
1.2 KiB
C
Raw Normal View History

SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 05:58:06 +08:00
// SPDX-License-Identifier: GPL-2.0+
dm: x86: Add a uclass for a Platform Controller Hub Add a simple uclass for this chip which is often found in x86 systems where the CPU is a separate device. The device can have children, so make it scan the device tree for these. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 23:29:27 +08:00
/*
* Copyright (c) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*/
#include <common.h>
#include <dm.h>
dm: Expand the uclass for Platform Controller Hubs (PCH) A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 11:19:17 +08:00
#include <pch.h>
dm: x86: Add a uclass for a Platform Controller Hub Add a simple uclass for this chip which is often found in x86 systems where the CPU is a separate device. The device can have children, so make it scan the device tree for these. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 23:29:27 +08:00
dm: pch: Rename get_sbase op to get_spi_base Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 17:40:42 +08:00
int pch_get_spi_base(struct udevice *dev, ulong *sbasep)
dm: Expand the uclass for Platform Controller Hubs (PCH) A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 11:19:17 +08:00
{
struct pch_ops *ops = pch_get_ops(dev);
*sbasep = 0;
dm: pch: Rename get_sbase op to get_spi_base Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 17:40:42 +08:00
if (!ops->get_spi_base)
dm: Expand the uclass for Platform Controller Hubs (PCH) A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 11:19:17 +08:00
return -ENOSYS;
dm: pch: Rename get_sbase op to get_spi_base Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 17:40:42 +08:00
return ops->get_spi_base(dev, sbasep);
dm: Expand the uclass for Platform Controller Hubs (PCH) A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 11:19:17 +08:00
}
int pch_set_spi_protect(struct udevice *dev, bool protect)
{
struct pch_ops *ops = pch_get_ops(dev);
if (!ops->set_spi_protect)
return -ENOSYS;
return ops->set_spi_protect(dev, protect);
}
dm: pch: Add get_gpio_base op x86 GPIO registers are accessed via I/O port whose base address is configured in a PCI configuration register on the PCH device. Add an op get_gpio_base to get the GPIO base address from PCH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 17:40:43 +08:00
int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
{
struct pch_ops *ops = pch_get_ops(dev);
*gbasep = 0;
if (!ops->get_gpio_base)
return -ENOSYS;
return ops->get_gpio_base(dev, gbasep);
}
dm: pch: Add get_io_base op On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 17:40:45 +08:00
int pch_get_io_base(struct udevice *dev, u32 *iobasep)
{
struct pch_ops *ops = pch_get_ops(dev);
*iobasep = 0;
if (!ops->get_io_base)
return -ENOSYS;
return ops->get_io_base(dev, iobasep);
}
pch: Add ioctl support At present the PCH has 4 operations and these are reasonably widely used in the drivers. But sometimes we want to add rarely used operations, and each of these currently adds to the size of the PCH operations table. Add an ioctl() method which can be easily expanded without any more impact on the operations table. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-17 11:24:51 +08:00
int pch_ioctl(struct udevice *dev, ulong req, void *data, int size)
{
struct pch_ops *ops = pch_get_ops(dev);
if (!ops->ioctl)
return -ENOSYS;
return ops->ioctl(dev, req, data, size);
}
dm: x86: Add a uclass for a Platform Controller Hub Add a simple uclass for this chip which is often found in x86 systems where the CPU is a separate device. The device can have children, so make it scan the device tree for these. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 23:29:27 +08:00
UCLASS_DRIVER(pch) = {
.id = UCLASS_PCH,
.name = "pch",
dm: Use dm_scan_fdt_dev() directly where possible Quite a few places have a bind() method which just calls dm_scan_fdt_dev(). We may as well call dm_scan_fdt_dev() directly. Update the code to do this. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-06 07:10:10 +08:00
.post_bind = dm_scan_fdt_dev,
dm: x86: Add a uclass for a Platform Controller Hub Add a simple uclass for this chip which is often found in x86 systems where the CPU is a separate device. The device can have children, so make it scan the device tree for these. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 23:29:27 +08:00
};
Reference in New Issue Copy Permalink