2008-03-26 22:55:32 +08:00
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/*
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* Copyright (C) 2008 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <libata.h>
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#include <fis.h>
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#include "fsl_sata.h"
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extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAX_DEVICE];
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#ifndef CFG_SATA1_FLAGS
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#define CFG_SATA1_FLAGS FLAGS_DMA
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#endif
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#ifndef CFG_SATA2_FLAGS
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#define CFG_SATA2_FLAGS FLAGS_DMA
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#endif
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static struct fsl_sata_info fsl_sata_info[] = {
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#ifdef CONFIG_SATA1
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{CFG_SATA1, CFG_SATA1_FLAGS},
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#else
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{0, 0},
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#endif
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#ifdef CONFIG_SATA2
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{CFG_SATA2, CFG_SATA2_FLAGS},
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#else
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{0, 0},
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#endif
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};
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static inline void mdelay(unsigned long msec)
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{
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unsigned long i;
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for (i = 0; i < msec; i++)
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udelay(1000);
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}
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static inline void sdelay(unsigned long sec)
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{
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unsigned long i;
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for (i = 0; i < sec; i++)
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mdelay(1000);
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}
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void dprint_buffer(unsigned char *buf, int len)
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{
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int i, j;
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i = 0;
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j = 0;
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printf("\n\r");
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for (i = 0; i < len; i++) {
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printf("%02x ", *buf++);
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j++;
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if (j == 16) {
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printf("\n\r");
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j = 0;
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}
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}
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printf("\n\r");
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}
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static void fsl_sata_dump_sfis(struct sfis *s)
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{
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printf("Status FIS dump:\n\r");
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printf("fis_type: %02x\n\r", s->fis_type);
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printf("pm_port_i: %02x\n\r", s->pm_port_i);
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printf("status: %02x\n\r", s->status);
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printf("error: %02x\n\r", s->error);
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printf("lba_low: %02x\n\r", s->lba_low);
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printf("lba_mid: %02x\n\r", s->lba_mid);
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printf("lba_high: %02x\n\r", s->lba_high);
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printf("device: %02x\n\r", s->device);
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printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
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printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
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printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
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printf("res1: %02x\n\r", s->res1);
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printf("sector_count: %02x\n\r", s->sector_count);
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printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
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}
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static int ata_wait_register(volatile unsigned *addr, u32 mask,
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u32 val, u32 timeout_msec)
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{
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int i;
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u32 temp;
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for (i = 0; (((temp = in_le32(addr)) & mask) != val)
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&& i < timeout_msec; i++)
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mdelay(1);
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return (i < timeout_msec) ? 0 : -1;
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}
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int init_sata(int dev)
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{
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u32 length, align;
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cmd_hdr_tbl_t *cmd_hdr;
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u32 cda;
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u32 val32;
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fsl_sata_reg_t *reg;
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u32 sig;
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int i;
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fsl_sata_t *sata;
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if (dev < 0 || dev > (CFG_SATA_MAX_DEVICE - 1)) {
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printf("the sata index %d is out of ranges\n\r", dev);
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return -1;
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}
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/* Allocate SATA device driver struct */
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sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
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if (!sata) {
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printf("alloc the sata device struct failed\n\r");
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return -1;
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}
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/* Zero all of the device driver struct */
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memset((void *)sata, 0, sizeof(fsl_sata_t));
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/* Save the private struct to block device struct */
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sata_dev_desc[dev].priv = (void *)sata;
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sprintf(sata->name, "SATA%d", dev);
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/* Set the controller register base address to device struct */
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reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
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sata->reg_base = reg;
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/* Allocate the command header table, 4 bytes aligned */
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length = sizeof(struct cmd_hdr_tbl);
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align = SATA_HC_CMD_HDR_TBL_ALIGN;
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sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
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if (!sata) {
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printf("alloc the command header failed\n\r");
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return -1;
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}
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cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
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& ~(align - 1));
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sata->cmd_hdr = cmd_hdr;
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/* Zero all of the command header table */
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memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
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/* Allocate command descriptor for all command */
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length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
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align = SATA_HC_CMD_DESC_ALIGN;
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sata->cmd_desc_offset = (void *)malloc(length + align);
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if (!sata->cmd_desc_offset) {
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printf("alloc the command descriptor failed\n\r");
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return -1;
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}
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sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
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& ~(align - 1));
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/* Zero all of command descriptor */
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memset((void *)sata->cmd_desc_offset, 0, length + align);
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/* Link the command descriptor to command header */
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for (i = 0; i < SATA_HC_MAX_CMD; i++) {
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cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
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& ~(CMD_HDR_CDA_ALIGN - 1);
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cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
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}
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/* To have safe state, force the controller offline */
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val32 = in_le32(®->hcontrol);
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val32 &= ~HCONTROL_ONOFF;
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val32 |= HCONTROL_FORCE_OFFLINE;
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out_le32(®->hcontrol, val32);
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/* Wait the controller offline */
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ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000);
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/* Set the command header base address to CHBA register to tell DMA */
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out_le32(®->chba, (u32)cmd_hdr & ~0x3);
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/* Snoop for the command header */
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val32 = in_le32(®->hcontrol);
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val32 |= HCONTROL_HDR_SNOOP;
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out_le32(®->hcontrol, val32);
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/* Disable all of interrupts */
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val32 = in_le32(®->hcontrol);
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val32 &= ~HCONTROL_INT_EN_ALL;
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out_le32(®->hcontrol, val32);
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/* Clear all of interrupts */
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val32 = in_le32(®->hstatus);
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out_le32(®->hstatus, val32);
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/* Set the ICC, no interrupt coalescing */
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out_le32(®->icc, 0x01000000);
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/* No PM attatched, the SATA device direct connect */
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out_le32(®->cqpmp, 0);
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/* Clear SError register */
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val32 = in_le32(®->serror);
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out_le32(®->serror, val32);
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/* Clear CER register */
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val32 = in_le32(®->cer);
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out_le32(®->cer, val32);
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/* Clear DER register */
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val32 = in_le32(®->der);
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out_le32(®->der, val32);
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/* No device detection or initialization action requested */
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out_le32(®->scontrol, 0x00000300);
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/* Configure the transport layer, default value */
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out_le32(®->transcfg, 0x08000016);
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/* Configure the link layer, default value */
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out_le32(®->linkcfg, 0x0000ff34);
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/* Bring the controller online */
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val32 = in_le32(®->hcontrol);
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val32 |= HCONTROL_ONOFF;
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out_le32(®->hcontrol, val32);
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mdelay(100);
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/* print sata device name */
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if (!dev)
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printf("%s ", sata->name);
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else
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printf(" %s ", sata->name);
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2008-06-03 17:38:19 +08:00
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/* Wait PHY RDY signal changed for 500ms */
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ata_wait_register(®->hstatus, HSTATUS_PHY_RDY,
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HSTATUS_PHY_RDY, 500);
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2008-03-26 22:55:32 +08:00
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/* Check PHYRDY */
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val32 = in_le32(®->hstatus);
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if (val32 & HSTATUS_PHY_RDY) {
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sata->link = 1;
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} else {
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sata->link = 0;
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printf("(No RDY)\n\r");
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return -1;
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}
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2008-06-03 17:38:19 +08:00
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/* Wait for signature updated, which is 1st D2H */
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ata_wait_register(®->hstatus, HSTATUS_SIGNATURE,
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HSTATUS_SIGNATURE, 10000);
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2008-03-26 22:55:32 +08:00
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if (val32 & HSTATUS_SIGNATURE) {
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sig = in_le32(®->sig);
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debug("Signature updated, the sig =%08x\n\r", sig);
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sata->ata_device_type = ata_dev_classify(sig);
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}
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/* Check the speed */
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val32 = in_le32(®->sstatus);
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if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
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printf("(1.5 Gbps)\n\r");
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else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
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printf("(3 Gbps)\n\r");
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return 0;
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}
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/* Hardware reset, like Power-on and COMRESET */
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void fsl_sata_hardware_reset(u32 reg_base)
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{
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fsl_sata_reg_t *reg = (fsl_sata_reg_t *)reg_base;
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u32 scontrol;
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/* Disable the SATA interface and put PHY offline */
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scontrol = in_le32(®->scontrol);
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scontrol = (scontrol & 0x0f0) | 0x304;
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out_le32(®->scontrol, scontrol);
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/* No speed strict */
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scontrol = in_le32(®->scontrol);
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scontrol = scontrol & ~0x0f0;
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out_le32(®->scontrol, scontrol);
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/* Issue PHY wake/reset, Hardware_reset_asserted */
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scontrol = in_le32(®->scontrol);
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scontrol = (scontrol & 0x0f0) | 0x301;
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out_le32(®->scontrol, scontrol);
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mdelay(100);
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/* Resume PHY, COMRESET negated, the device initialize hardware
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* and execute diagnostics, send good status-signature to host,
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* which is D2H register FIS, and then the device enter idle state.
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*/
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scontrol = in_le32(®->scontrol);
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scontrol = (scontrol & 0x0f0) | 0x300;
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out_le32(®->scontrol, scontrol);
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mdelay(100);
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return;
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}
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static void fsl_sata_dump_regs(fsl_sata_reg_t *reg)
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{
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printf("\n\rSATA: %08x\n\r", (u32)reg);
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printf("CQR: %08x\n\r", in_le32(®->cqr));
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printf("CAR: %08x\n\r", in_le32(®->car));
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printf("CCR: %08x\n\r", in_le32(®->ccr));
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printf("CER: %08x\n\r", in_le32(®->cer));
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printf("CQR: %08x\n\r", in_le32(®->cqr));
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printf("DER: %08x\n\r", in_le32(®->der));
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printf("CHBA: %08x\n\r", in_le32(®->chba));
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printf("HStatus: %08x\n\r", in_le32(®->hstatus));
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printf("HControl: %08x\n\r", in_le32(®->hcontrol));
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printf("CQPMP: %08x\n\r", in_le32(®->cqpmp));
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printf("SIG: %08x\n\r", in_le32(®->sig));
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printf("ICC: %08x\n\r", in_le32(®->icc));
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printf("SStatus: %08x\n\r", in_le32(®->sstatus));
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printf("SError: %08x\n\r", in_le32(®->serror));
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printf("SControl: %08x\n\r", in_le32(®->scontrol));
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printf("SNotification: %08x\n\r", in_le32(®->snotification));
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printf("TransCfg: %08x\n\r", in_le32(®->transcfg));
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printf("TransStatus: %08x\n\r", in_le32(®->transstatus));
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printf("LinkCfg: %08x\n\r", in_le32(®->linkcfg));
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printf("LinkCfg1: %08x\n\r", in_le32(®->linkcfg1));
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printf("LinkCfg2: %08x\n\r", in_le32(®->linkcfg2));
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printf("LinkStatus: %08x\n\r", in_le32(®->linkstatus));
|
|
|
|
printf("LinkStatus1: %08x\n\r", in_le32(®->linkstatus1));
|
|
|
|
printf("PhyCtrlCfg: %08x\n\r", in_le32(®->phyctrlcfg));
|
|
|
|
printf("SYSPR: %08x\n\r", in_be32(®->syspr));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct cfis *cfis,
|
|
|
|
int is_ncq, int tag, u8 *buffer, u32 len)
|
|
|
|
{
|
|
|
|
cmd_hdr_entry_t *cmd_hdr;
|
|
|
|
cmd_desc_t *cmd_desc;
|
|
|
|
sata_fis_h2d_t *h2d;
|
|
|
|
prd_entry_t *prde;
|
|
|
|
u32 ext_c_ddc;
|
|
|
|
u32 prde_count;
|
|
|
|
u32 val32;
|
|
|
|
u32 ttl;
|
|
|
|
fsl_sata_reg_t *reg = sata->reg_base;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Check xfer length */
|
|
|
|
if (len > SATA_HC_MAX_XFER_LEN) {
|
|
|
|
printf("max transfer length is 64MB\n\r");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup the command descriptor */
|
|
|
|
cmd_desc = sata->cmd_desc + tag;
|
|
|
|
|
|
|
|
/* Get the pointer cfis of command descriptor */
|
|
|
|
h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
|
|
|
|
|
|
|
|
/* Zero the cfis of command descriptor */
|
|
|
|
memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
|
|
|
|
|
|
|
|
/* Copy the cfis from user to command descriptor */
|
|
|
|
h2d->fis_type = cfis->fis_type;
|
|
|
|
h2d->pm_port_c = cfis->pm_port_c;
|
|
|
|
h2d->command = cfis->command;
|
|
|
|
|
|
|
|
h2d->features = cfis->features;
|
|
|
|
h2d->features_exp = cfis->features_exp;
|
|
|
|
|
|
|
|
h2d->lba_low = cfis->lba_low;
|
|
|
|
h2d->lba_mid = cfis->lba_mid;
|
|
|
|
h2d->lba_high = cfis->lba_high;
|
|
|
|
h2d->lba_low_exp = cfis->lba_low_exp;
|
|
|
|
h2d->lba_mid_exp = cfis->lba_mid_exp;
|
|
|
|
h2d->lba_high_exp = cfis->lba_high_exp;
|
|
|
|
|
|
|
|
if (!is_ncq) {
|
|
|
|
h2d->sector_count = cfis->sector_count;
|
|
|
|
h2d->sector_count_exp = cfis->sector_count_exp;
|
|
|
|
} else { /* NCQ */
|
|
|
|
h2d->sector_count = (u8)(tag << 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
h2d->device = cfis->device;
|
|
|
|
h2d->control = cfis->control;
|
|
|
|
|
|
|
|
/* Setup the PRD table */
|
|
|
|
prde = (prd_entry_t *)cmd_desc->prdt;
|
|
|
|
memset((void *)prde, 0, sizeof(struct prdt));
|
|
|
|
|
|
|
|
prde_count = 0;
|
|
|
|
ttl = len;
|
|
|
|
for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
|
|
|
|
if (!len)
|
|
|
|
break;
|
|
|
|
prde->dba = cpu_to_le32((u32)buffer & ~0x3);
|
|
|
|
debug("dba = %08x\n\r", (u32)buffer);
|
|
|
|
|
|
|
|
if (len < PRD_ENTRY_MAX_XFER_SZ) {
|
|
|
|
ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
|
|
|
|
debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len);
|
|
|
|
prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
|
|
|
|
prde_count++;
|
|
|
|
prde++;
|
|
|
|
break;
|
|
|
|
} else {
|
|
|
|
ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
|
|
|
|
debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len);
|
|
|
|
prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
|
|
|
|
buffer += PRD_ENTRY_MAX_XFER_SZ;
|
|
|
|
len -= PRD_ENTRY_MAX_XFER_SZ;
|
|
|
|
prde_count++;
|
|
|
|
prde++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup the command slot of cmd hdr */
|
|
|
|
cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
|
|
|
|
|
|
|
|
cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
|
|
|
|
|
|
|
|
val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
|
|
|
|
val32 |= sizeof(sata_fis_h2d_t);
|
|
|
|
cmd_hdr->prde_fis_len = cpu_to_le32(val32);
|
|
|
|
|
|
|
|
cmd_hdr->ttl = cpu_to_le32(ttl);
|
|
|
|
|
|
|
|
if (!is_ncq) {
|
|
|
|
val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
|
|
|
|
} else {
|
|
|
|
val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA;
|
|
|
|
}
|
|
|
|
|
|
|
|
tag &= CMD_HDR_ATTR_TAG;
|
|
|
|
val32 |= tag;
|
|
|
|
|
|
|
|
debug("attribute = %08x\n\r", val32);
|
|
|
|
cmd_hdr->attribute = cpu_to_le32(val32);
|
|
|
|
|
|
|
|
/* Make sure cmd desc and cmd slot valid before commmand issue */
|
|
|
|
sync();
|
|
|
|
|
|
|
|
/* PMP*/
|
|
|
|
val32 = (u32)(h2d->pm_port_c & 0x0f);
|
|
|
|
out_le32(®->cqpmp, val32);
|
|
|
|
|
|
|
|
/* Wait no active */
|
|
|
|
if (ata_wait_register(®->car, (1 << tag), 0, 10000))
|
|
|
|
printf("Wait no active time out\n\r");
|
|
|
|
|
|
|
|
/* Issue command */
|
|
|
|
if (!(in_le32(®->cqr) & (1 << tag))) {
|
|
|
|
val32 = 1 << tag;
|
|
|
|
out_le32(®->cqr, val32);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Wait command completed for 10s */
|
|
|
|
if (ata_wait_register(®->ccr, (1 << tag), (1 << tag), 10000)) {
|
|
|
|
if (!is_ncq)
|
|
|
|
printf("Non-NCQ command time out\n\r");
|
|
|
|
else
|
|
|
|
printf("NCQ command time out\n\r");
|
|
|
|
}
|
|
|
|
|
|
|
|
val32 = in_le32(®->cer);
|
|
|
|
|
|
|
|
if (val32) {
|
|
|
|
u32 der;
|
|
|
|
fsl_sata_dump_sfis((struct sfis *)cmd_desc->sfis);
|
|
|
|
printf("CE at device\n\r");
|
|
|
|
fsl_sata_dump_regs(reg);
|
|
|
|
der = in_le32(®->der);
|
|
|
|
out_le32(®->cer, val32);
|
|
|
|
out_le32(®->der, der);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Clear complete flags */
|
|
|
|
val32 = in_le32(®->ccr);
|
|
|
|
out_le32(®->ccr, val32);
|
|
|
|
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct cfis *cfis,
|
|
|
|
int tag, u8 *buffer, u32 len)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct cfis *cfis,
|
|
|
|
enum cmd_type command_type, int tag, u8 *buffer, u32 len)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (tag > SATA_HC_MAX_CMD || tag < 0) {
|
2008-07-11 03:00:15 +08:00
|
|
|
printf("tag is out of range, tag=%d\n\r", tag);
|
2008-03-26 22:55:32 +08:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (command_type) {
|
|
|
|
case CMD_ATA:
|
|
|
|
rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
|
|
|
|
return rc;
|
|
|
|
case CMD_RESET:
|
|
|
|
rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len);
|
|
|
|
return rc;
|
|
|
|
case CMD_NCQ:
|
|
|
|
rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
|
|
|
|
return rc;
|
|
|
|
case CMD_ATAPI:
|
|
|
|
case CMD_VENDOR_BIST:
|
|
|
|
case CMD_BIST:
|
|
|
|
printf("not support now\n\r");
|
|
|
|
return -1;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fsl_sata_identify(int dev, u16 *id)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
struct sata_fis_h2d h2d;
|
|
|
|
struct cfis *cfis;
|
|
|
|
|
|
|
|
cfis = (struct cfis *)&h2d;
|
|
|
|
memset((void *)cfis, 0, sizeof(struct cfis));
|
|
|
|
|
|
|
|
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
|
|
|
|
cfis->pm_port_c = 0x80; /* is command */
|
|
|
|
cfis->command = ATA_CMD_ID_ATA;
|
|
|
|
|
|
|
|
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
|
|
|
|
ata_swap_buf_le16(id, ATA_ID_WORDS);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fsl_sata_xfer_mode(int dev, u16 *id)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
|
|
|
|
sata->pio = id[ATA_ID_PIO_MODES];
|
|
|
|
sata->mwdma = id[ATA_ID_MWDMA_MODES];
|
|
|
|
sata->udma = id[ATA_ID_UDMA_MODES];
|
|
|
|
debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fsl_sata_set_features(int dev)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
struct sata_fis_h2d h2d;
|
|
|
|
struct cfis *cfis;
|
|
|
|
u8 udma_cap;
|
|
|
|
|
|
|
|
cfis = (struct cfis *)&h2d;
|
|
|
|
memset((void *)cfis, 0, sizeof(struct cfis));
|
|
|
|
|
|
|
|
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
|
|
|
|
cfis->pm_port_c = 0x80; /* is command */
|
|
|
|
cfis->command = ATA_CMD_SET_FEATURES;
|
|
|
|
cfis->features = SETFEATURES_XFER;
|
|
|
|
|
|
|
|
/* First check the device capablity */
|
|
|
|
udma_cap = (u8)(sata->udma & 0xff);
|
|
|
|
debug("udma_cap %02x\n\r", udma_cap);
|
|
|
|
|
|
|
|
if (udma_cap == ATA_UDMA6)
|
|
|
|
cfis->sector_count = XFER_UDMA_6;
|
|
|
|
if (udma_cap == ATA_UDMA5)
|
|
|
|
cfis->sector_count = XFER_UDMA_5;
|
|
|
|
if (udma_cap == ATA_UDMA4)
|
|
|
|
cfis->sector_count = XFER_UDMA_4;
|
|
|
|
if (udma_cap == ATA_UDMA3)
|
|
|
|
cfis->sector_count = XFER_UDMA_3;
|
|
|
|
|
|
|
|
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
struct sata_fis_h2d h2d;
|
|
|
|
struct cfis *cfis;
|
|
|
|
u32 block;
|
|
|
|
|
|
|
|
block = start;
|
|
|
|
cfis = (struct cfis *)&h2d;
|
|
|
|
|
|
|
|
memset((void *)cfis, 0, sizeof(struct cfis));
|
|
|
|
|
|
|
|
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
|
|
|
|
cfis->pm_port_c = 0x80; /* is command */
|
2008-04-01 15:22:11 +08:00
|
|
|
cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
|
2008-03-26 22:55:32 +08:00
|
|
|
cfis->device = ATA_LBA;
|
|
|
|
|
|
|
|
cfis->device |= (block >> 24) & 0xf;
|
|
|
|
cfis->lba_high = (block >> 16) & 0xff;
|
|
|
|
cfis->lba_mid = (block >> 8) & 0xff;
|
|
|
|
cfis->lba_low = block & 0xff;
|
|
|
|
cfis->sector_count = (u8)(blkcnt & 0xff);
|
|
|
|
|
|
|
|
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
|
|
|
|
return blkcnt;
|
|
|
|
}
|
|
|
|
|
|
|
|
void fsl_sata_flush_cache(int dev)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
struct sata_fis_h2d h2d;
|
|
|
|
struct cfis *cfis;
|
|
|
|
|
|
|
|
cfis = (struct cfis *)&h2d;
|
|
|
|
|
|
|
|
memset((void *)cfis, 0, sizeof(struct cfis));
|
|
|
|
|
|
|
|
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
|
|
|
|
cfis->pm_port_c = 0x80; /* is command */
|
2008-04-01 15:22:11 +08:00
|
|
|
cfis->command = ATA_CMD_FLUSH;
|
2008-03-26 22:55:32 +08:00
|
|
|
|
|
|
|
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
struct sata_fis_h2d h2d;
|
|
|
|
struct cfis *cfis;
|
|
|
|
u64 block;
|
|
|
|
|
|
|
|
block = (u64)start;
|
|
|
|
cfis = (struct cfis *)&h2d;
|
|
|
|
|
|
|
|
memset((void *)cfis, 0, sizeof(struct cfis));
|
|
|
|
|
|
|
|
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
|
|
|
|
cfis->pm_port_c = 0x80; /* is command */
|
|
|
|
|
2008-04-01 15:22:11 +08:00
|
|
|
cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
|
|
|
|
: ATA_CMD_READ_EXT;
|
2008-03-26 22:55:32 +08:00
|
|
|
|
|
|
|
cfis->lba_high_exp = (block >> 40) & 0xff;
|
|
|
|
cfis->lba_mid_exp = (block >> 32) & 0xff;
|
|
|
|
cfis->lba_low_exp = (block >> 24) & 0xff;
|
|
|
|
cfis->lba_high = (block >> 16) & 0xff;
|
|
|
|
cfis->lba_mid = (block >> 8) & 0xff;
|
|
|
|
cfis->lba_low = block & 0xff;
|
|
|
|
cfis->device = ATA_LBA;
|
|
|
|
cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
|
|
|
|
cfis->sector_count = blkcnt & 0xff;
|
|
|
|
|
|
|
|
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
|
|
|
|
return blkcnt;
|
|
|
|
}
|
|
|
|
|
|
|
|
u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
struct sata_fis_h2d h2d;
|
|
|
|
struct cfis *cfis;
|
|
|
|
int ncq_channel;
|
|
|
|
u64 block;
|
|
|
|
|
|
|
|
if (sata_dev_desc[dev].lba48 != 1) {
|
|
|
|
printf("execute FPDMA command on non-LBA48 hard disk\n\r");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
block = (u64)start;
|
|
|
|
cfis = (struct cfis *)&h2d;
|
|
|
|
|
|
|
|
memset((void *)cfis, 0, sizeof(struct cfis));
|
|
|
|
|
|
|
|
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
|
|
|
|
cfis->pm_port_c = 0x80; /* is command */
|
|
|
|
|
2008-04-01 15:22:11 +08:00
|
|
|
cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
|
|
|
|
: ATA_CMD_FPDMA_READ;
|
2008-03-26 22:55:32 +08:00
|
|
|
|
|
|
|
cfis->lba_high_exp = (block >> 40) & 0xff;
|
|
|
|
cfis->lba_mid_exp = (block >> 32) & 0xff;
|
|
|
|
cfis->lba_low_exp = (block >> 24) & 0xff;
|
|
|
|
cfis->lba_high = (block >> 16) & 0xff;
|
|
|
|
cfis->lba_mid = (block >> 8) & 0xff;
|
|
|
|
cfis->lba_low = block & 0xff;
|
|
|
|
|
|
|
|
cfis->device = ATA_LBA;
|
|
|
|
cfis->features_exp = (blkcnt >> 8) & 0xff;
|
|
|
|
cfis->features = blkcnt & 0xff;
|
|
|
|
|
|
|
|
if (sata->queue_depth >= SATA_HC_MAX_CMD)
|
|
|
|
ncq_channel = SATA_HC_MAX_CMD - 1;
|
|
|
|
else
|
|
|
|
ncq_channel = sata->queue_depth - 1;
|
|
|
|
|
|
|
|
/* Use the latest queue */
|
|
|
|
fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt);
|
|
|
|
return blkcnt;
|
|
|
|
}
|
|
|
|
|
|
|
|
void fsl_sata_flush_cache_ext(int dev)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
struct sata_fis_h2d h2d;
|
|
|
|
struct cfis *cfis;
|
|
|
|
|
|
|
|
cfis = (struct cfis *)&h2d;
|
|
|
|
|
|
|
|
memset((void *)cfis, 0, sizeof(struct cfis));
|
|
|
|
|
|
|
|
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
|
|
|
|
cfis->pm_port_c = 0x80; /* is command */
|
2008-04-01 15:22:11 +08:00
|
|
|
cfis->command = ATA_CMD_FLUSH_EXT;
|
2008-03-26 22:55:32 +08:00
|
|
|
|
|
|
|
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Software reset, set SRST of the Device Control register */
|
|
|
|
void fsl_sata_software_reset(int dev)
|
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fsl_sata_init_wcache(int dev, u16 *id)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
|
|
|
|
if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
|
|
|
|
sata->wcache = 1;
|
|
|
|
if (ata_id_has_flush(id))
|
|
|
|
sata->flush = 1;
|
|
|
|
if (ata_id_has_flush_ext(id))
|
|
|
|
sata->flush_ext = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_sata_get_wcache(int dev)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
return sata->wcache;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_sata_get_flush(int dev)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
return sata->flush;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_sata_get_flush_ext(int dev)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
return sata->flush_ext;
|
|
|
|
}
|
|
|
|
|
|
|
|
u32 ata_low_level_rw_lba48(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
|
|
|
|
{
|
|
|
|
u32 start, blks;
|
|
|
|
u8 *addr;
|
|
|
|
int max_blks;
|
|
|
|
|
|
|
|
start = blknr;
|
|
|
|
blks = blkcnt;
|
|
|
|
addr = (u8 *)buffer;
|
|
|
|
|
|
|
|
max_blks = ATA_MAX_SECTORS_LBA48;
|
|
|
|
do {
|
|
|
|
if (blks > max_blks) {
|
|
|
|
if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
|
|
|
|
fsl_sata_rw_cmd_ext(dev, start, max_blks, addr, is_write);
|
|
|
|
else
|
|
|
|
fsl_sata_rw_ncq_cmd(dev, start, max_blks, addr, is_write);
|
|
|
|
start += max_blks;
|
|
|
|
blks -= max_blks;
|
|
|
|
addr += ATA_SECT_SIZE * max_blks;
|
|
|
|
} else {
|
|
|
|
if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
|
|
|
|
fsl_sata_rw_cmd_ext(dev, start, blks, addr, is_write);
|
|
|
|
else
|
|
|
|
fsl_sata_rw_ncq_cmd(dev, start, blks, addr, is_write);
|
|
|
|
start += blks;
|
|
|
|
blks = 0;
|
|
|
|
addr += ATA_SECT_SIZE * blks;
|
|
|
|
}
|
|
|
|
} while (blks != 0);
|
|
|
|
|
|
|
|
return blkcnt;
|
|
|
|
}
|
|
|
|
|
|
|
|
u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
|
|
|
|
{
|
|
|
|
u32 start, blks;
|
|
|
|
u8 *addr;
|
|
|
|
int max_blks;
|
|
|
|
|
|
|
|
start = blknr;
|
|
|
|
blks = blkcnt;
|
|
|
|
addr = (u8 *)buffer;
|
|
|
|
|
|
|
|
max_blks = ATA_MAX_SECTORS;
|
|
|
|
do {
|
|
|
|
if (blks > max_blks) {
|
|
|
|
fsl_sata_rw_cmd(dev, start, max_blks, addr, is_write);
|
|
|
|
start += max_blks;
|
|
|
|
blks -= max_blks;
|
|
|
|
addr += ATA_SECT_SIZE * max_blks;
|
|
|
|
} else {
|
|
|
|
fsl_sata_rw_cmd(dev, start, blks, addr, is_write);
|
|
|
|
start += blks;
|
|
|
|
blks = 0;
|
|
|
|
addr += ATA_SECT_SIZE * blks;
|
|
|
|
}
|
|
|
|
} while (blks != 0);
|
|
|
|
|
|
|
|
return blkcnt;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* SATA interface between low level driver and command layer
|
|
|
|
*/
|
|
|
|
ulong sata_read(int dev, u32 blknr, u32 blkcnt, void *buffer)
|
|
|
|
{
|
|
|
|
u32 rc;
|
|
|
|
|
|
|
|
if (sata_dev_desc[dev].lba48)
|
|
|
|
rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
|
|
|
|
else
|
|
|
|
rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
ulong sata_write(int dev, u32 blknr, u32 blkcnt, void *buffer)
|
|
|
|
{
|
|
|
|
u32 rc;
|
|
|
|
|
|
|
|
if (sata_dev_desc[dev].lba48) {
|
|
|
|
rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
|
|
|
|
if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush_ext(dev))
|
|
|
|
fsl_sata_flush_cache_ext(dev);
|
|
|
|
} else {
|
|
|
|
rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
|
|
|
|
if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush(dev))
|
|
|
|
fsl_sata_flush_cache(dev);
|
|
|
|
}
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
int scan_sata(int dev)
|
|
|
|
{
|
|
|
|
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
|
|
|
|
unsigned char serial[ATA_ID_SERNO_LEN + 1];
|
|
|
|
unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
|
|
|
|
unsigned char product[ATA_ID_PROD_LEN + 1];
|
|
|
|
u16 *id;
|
|
|
|
u64 n_sectors;
|
|
|
|
|
|
|
|
/* if no detected link */
|
|
|
|
if (!sata->link)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
id = (u16 *)malloc(ATA_ID_WORDS * 2);
|
|
|
|
if (!id) {
|
|
|
|
printf("id malloc failed\n\r");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Identify device to get information */
|
|
|
|
fsl_sata_identify(dev, id);
|
|
|
|
|
|
|
|
/* Serial number */
|
|
|
|
ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
|
|
|
|
memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
|
|
|
|
|
|
|
|
/* Firmware version */
|
|
|
|
ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
|
|
|
|
memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
|
|
|
|
|
|
|
|
/* Product model */
|
|
|
|
ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
|
|
|
|
memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
|
|
|
|
|
|
|
|
/* Totoal sectors */
|
|
|
|
n_sectors = ata_id_n_sectors(id);
|
|
|
|
sata_dev_desc[dev].lba = (u32)n_sectors;
|
|
|
|
|
|
|
|
/* Check if support LBA48 */
|
|
|
|
if (ata_id_has_lba48(id)) {
|
|
|
|
sata_dev_desc[dev].lba48 = 1;
|
|
|
|
debug("Device support LBA48\n\r");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get the NCQ queue depth from device */
|
|
|
|
sata->queue_depth = ata_id_queue_depth(id);
|
|
|
|
|
|
|
|
/* Get the xfer mode from device */
|
|
|
|
fsl_sata_xfer_mode(dev, id);
|
|
|
|
|
|
|
|
/* Get the write cache status from device */
|
|
|
|
fsl_sata_init_wcache(dev, id);
|
|
|
|
|
|
|
|
/* Set the xfer mode to highest speed */
|
|
|
|
fsl_sata_set_features(dev);
|
|
|
|
#ifdef DEBUG
|
|
|
|
fsl_sata_identify(dev, id);
|
|
|
|
ata_dump_id(id);
|
|
|
|
#endif
|
|
|
|
free((void *)id);
|
|
|
|
return 0;
|
|
|
|
}
|