2018-05-07 05:58:06 +08:00
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// SPDX-License-Identifier: GPL-2.0+
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2013-03-11 14:49:53 +08:00
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2002-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*/
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#include <common.h>
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2018-11-16 09:43:52 +08:00
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#include <bloblist.h>
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2020-05-11 01:40:00 +08:00
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#include <bootstage.h>
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2019-12-29 01:44:58 +08:00
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#include <clock_legacy.h>
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2015-11-09 14:47:45 +08:00
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#include <console.h>
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2018-08-06 16:23:41 +08:00
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#include <cpu.h>
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2019-11-15 03:57:34 +08:00
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#include <cpu_func.h>
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2014-07-23 20:55:04 +08:00
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#include <dm.h>
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2019-08-01 23:46:43 +08:00
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#include <env.h>
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2019-08-02 23:44:25 +08:00
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#include <env_internal.h>
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2013-03-11 14:49:53 +08:00
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#include <fdtdec.h>
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2013-04-20 16:42:41 +08:00
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#include <fs.h>
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2019-12-29 01:45:07 +08:00
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#include <hang.h>
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2013-03-11 22:30:42 +08:00
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#include <i2c.h>
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2019-11-15 03:57:45 +08:00
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#include <init.h>
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2013-03-11 14:49:53 +08:00
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#include <initcall.h>
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2019-08-01 23:46:38 +08:00
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#include <lcd.h>
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2020-05-11 01:40:05 +08:00
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#include <log.h>
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2015-02-28 13:06:36 +08:00
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#include <malloc.h>
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2015-03-23 06:08:59 +08:00
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#include <mapmem.h>
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2013-04-26 10:53:43 +08:00
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#include <os.h>
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2013-03-11 14:49:53 +08:00
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#include <post.h>
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2017-03-31 22:40:38 +08:00
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#include <relocate.h>
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2019-11-15 03:57:24 +08:00
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#include <serial.h>
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2018-11-16 09:44:09 +08:00
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#ifdef CONFIG_SPL
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#include <spl.h>
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#endif
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2014-06-24 05:20:19 +08:00
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#include <status_led.h>
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2018-08-06 16:23:34 +08:00
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#include <sysreset.h>
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2016-02-25 00:14:50 +08:00
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#include <timer.h>
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2013-06-12 02:14:42 +08:00
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#include <trace.h>
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2016-01-19 10:52:21 +08:00
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#include <video.h>
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2013-03-11 22:30:42 +08:00
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#include <watchdog.h>
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2020-05-11 01:39:56 +08:00
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#include <asm/cache.h>
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2017-05-17 22:23:01 +08:00
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#ifdef CONFIG_MACH_TYPE
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#include <asm/mach-types.h>
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#endif
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2017-03-31 22:40:39 +08:00
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#if defined(CONFIG_MP) && defined(CONFIG_PPC)
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#include <asm/mp.h>
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#endif
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2020-10-31 11:38:53 +08:00
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#include <asm/global_data.h>
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2013-03-11 14:49:53 +08:00
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#include <asm/io.h>
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#include <asm/sections.h>
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2014-07-23 20:55:04 +08:00
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#include <dm/root.h>
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2017-03-31 22:40:35 +08:00
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#include <linux/errno.h>
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2013-03-11 14:49:53 +08:00
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/*
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* Pointer to initial global data area
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*
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* Here we initialize it if needed.
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*/
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#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
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#undef XTRN_DECLARE_GLOBAL_DATA_PTR
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#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
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2018-01-15 18:10:02 +08:00
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DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
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2013-03-11 14:49:53 +08:00
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#else
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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/*
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2015-04-29 10:25:03 +08:00
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* TODO(sjg@chromium.org): IMO this code should be
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2013-03-11 14:49:53 +08:00
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* refactored to a single function, something like:
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*
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* void led_set_state(enum led_colour_t colour, int on);
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*/
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/************************************************************************
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* Coloured LED functionality
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************************************************************************
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* May be supplied by boards if desired
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*/
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2014-06-24 05:20:19 +08:00
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__weak void coloured_LED_init(void) {}
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__weak void red_led_on(void) {}
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__weak void red_led_off(void) {}
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__weak void green_led_on(void) {}
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__weak void green_led_off(void) {}
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__weak void yellow_led_on(void) {}
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__weak void yellow_led_off(void) {}
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__weak void blue_led_on(void) {}
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__weak void blue_led_off(void) {}
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2013-03-11 14:49:53 +08:00
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/*
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* Why is gd allocated a register? Prior to reloc it might be better to
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* just pass it around to each function in this file?
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*
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* After reloc one could argue that it is hardly used and doesn't need
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* to be in a register. Or if it is it should perhaps hold pointers to all
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* global data for all modules, so that post-reloc we can avoid the massive
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* literal pool we get on ARM. Or perhaps just encourage each module to use
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* a structure...
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*/
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2014-07-17 19:01:34 +08:00
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#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
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2013-03-11 22:30:42 +08:00
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static int init_func_watchdog_init(void)
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{
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2017-03-14 23:08:10 +08:00
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# if defined(CONFIG_HW_WATCHDOG) && \
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(defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
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2018-10-10 02:46:40 +08:00
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defined(CONFIG_SH) || \
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2016-06-13 20:24:23 +08:00
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defined(CONFIG_DESIGNWARE_WATCHDOG) || \
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2015-03-10 15:04:36 +08:00
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defined(CONFIG_IMX_WATCHDOG))
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2014-07-17 19:01:34 +08:00
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hw_watchdog_init();
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2013-03-11 22:30:42 +08:00
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puts(" Watchdog enabled\n");
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2016-06-13 20:24:24 +08:00
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# endif
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2013-03-11 22:30:42 +08:00
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WATCHDOG_RESET();
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return 0;
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}
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int init_func_watchdog_reset(void)
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{
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WATCHDOG_RESET();
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return 0;
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}
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#endif /* CONFIG_WATCHDOG */
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2014-10-09 04:57:22 +08:00
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__weak void board_add_ram_info(int use_default)
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2013-03-11 22:30:42 +08:00
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{
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/* please define platform specific board_add_ram_info() */
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}
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2013-03-11 14:49:53 +08:00
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static int init_baud_rate(void)
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{
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2017-08-04 02:22:13 +08:00
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gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
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2013-03-11 14:49:53 +08:00
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return 0;
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}
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static int display_text_info(void)
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{
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2015-07-31 23:31:37 +08:00
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#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
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2014-11-16 06:46:53 +08:00
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ulong bss_start, bss_end, text_base;
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2013-03-11 14:49:53 +08:00
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2013-03-11 15:06:48 +08:00
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bss_start = (ulong)&__bss_start;
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bss_end = (ulong)&__bss_end;
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2014-02-23 00:53:43 +08:00
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2014-07-17 19:01:34 +08:00
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#ifdef CONFIG_SYS_TEXT_BASE
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2014-11-16 06:46:53 +08:00
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text_base = CONFIG_SYS_TEXT_BASE;
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2014-07-17 19:01:34 +08:00
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#else
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2014-11-16 06:46:53 +08:00
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text_base = CONFIG_SYS_MONITOR_BASE;
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2014-07-17 19:01:34 +08:00
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#endif
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2014-11-16 06:46:53 +08:00
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debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
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2018-01-15 18:10:02 +08:00
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text_base, bss_start, bss_end);
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2013-04-26 10:53:43 +08:00
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#endif
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2013-03-11 14:49:53 +08:00
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return 0;
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}
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2018-08-06 16:23:34 +08:00
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#ifdef CONFIG_SYSRESET
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static int print_resetinfo(void)
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{
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struct udevice *dev;
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char status[256];
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int ret;
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ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
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if (ret) {
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debug("%s: No sysreset device found (error: %d)\n",
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__func__, ret);
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/* Not all boards have sysreset drivers available during early
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* boot, so don't fail if one can't be found.
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*/
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return 0;
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}
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if (!sysreset_get_status(dev, status, sizeof(status)))
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printf("%s", status);
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return 0;
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}
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#endif
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2018-08-06 16:23:41 +08:00
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#if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
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static int print_cpuinfo(void)
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{
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struct udevice *dev;
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char desc[512];
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int ret;
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2020-05-03 21:58:50 +08:00
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dev = cpu_get_current_dev();
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if (!dev) {
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debug("%s: Could not get CPU device\n",
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__func__);
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return -ENODEV;
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2018-08-06 16:23:41 +08:00
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}
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ret = cpu_get_desc(dev, desc, sizeof(desc));
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if (ret) {
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debug("%s: Could not get CPU description (err = %d)\n",
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dev->name, ret);
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return ret;
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}
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2018-10-11 13:06:55 +08:00
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printf("CPU: %s\n", desc);
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2018-08-06 16:23:41 +08:00
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return 0;
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}
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#endif
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2013-03-11 14:49:53 +08:00
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static int announce_dram_init(void)
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{
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puts("DRAM: ");
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return 0;
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}
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static int show_dram_config(void)
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{
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2014-05-03 08:28:05 +08:00
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unsigned long long size;
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2013-03-11 14:49:53 +08:00
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int i;
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debug("\nRAM Configuration:\n");
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for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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size += gd->bd->bi_dram[i].size;
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2015-08-06 16:31:20 +08:00
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debug("Bank #%d: %llx ", i,
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(unsigned long long)(gd->bd->bi_dram[i].start));
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2013-03-11 14:49:53 +08:00
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#ifdef DEBUG
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print_size(gd->bd->bi_dram[i].size, "\n");
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#endif
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}
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debug("\nDRAM: ");
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2013-03-11 22:30:42 +08:00
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print_size(size, "");
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board_add_ram_info(0);
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putc('\n');
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2013-03-11 14:49:53 +08:00
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return 0;
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}
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2017-03-31 22:40:32 +08:00
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__weak int dram_init_banksize(void)
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2013-03-11 14:49:53 +08:00
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{
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2020-08-12 19:02:39 +08:00
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gd->bd->bi_dram[0].start = gd->ram_base;
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2013-03-11 14:49:53 +08:00
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gd->bd->bi_dram[0].size = get_effective_memsize();
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2017-03-31 22:40:32 +08:00
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return 0;
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2013-03-11 14:49:53 +08:00
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}
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2021-08-19 11:12:24 +08:00
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#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
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2013-03-11 22:30:42 +08:00
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static int init_func_i2c(void)
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{
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puts("I2C: ");
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2013-09-22 00:13:34 +08:00
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i2c_init_all();
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2013-03-11 22:30:42 +08:00
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puts("ready\n");
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return 0;
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}
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#endif
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2018-01-17 18:43:08 +08:00
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#if defined(CONFIG_VID)
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__weak int init_func_vid(void)
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{
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return 0;
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}
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#endif
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2013-03-11 14:49:53 +08:00
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static int setup_mon_len(void)
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{
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2014-05-08 22:08:44 +08:00
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#if defined(__ARM__) || defined(__MICROBLAZE__)
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2014-02-23 00:53:43 +08:00
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gd->mon_len = (ulong)&__bss_end - (ulong)_start;
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2021-05-19 18:02:39 +08:00
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#elif defined(CONFIG_SANDBOX)
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gd->mon_len = 0;
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#elif defined(CONFIG_EFI_APP)
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2013-04-26 10:53:43 +08:00
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gd->mon_len = (ulong)&_end - (ulong)_init;
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2017-03-14 23:08:10 +08:00
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#elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
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2014-07-17 19:01:34 +08:00
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gd->mon_len = CONFIG_SYS_MONITOR_LEN;
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2017-12-26 13:55:58 +08:00
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#elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
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2015-08-24 14:52:35 +08:00
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gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
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2016-05-15 08:49:28 +08:00
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#elif defined(CONFIG_SYS_MONITOR_BASE)
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2013-03-11 22:30:42 +08:00
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/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
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gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
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2013-03-11 15:06:48 +08:00
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#endif
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2013-03-11 14:49:53 +08:00
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return 0;
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}
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2018-11-16 09:44:09 +08:00
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static int setup_spl_handoff(void)
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{
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#if CONFIG_IS_ENABLED(HANDOFF)
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gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
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sizeof(struct spl_handoff));
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debug("Found SPL hand-off info %p\n", gd->spl_handoff);
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#endif
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return 0;
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}
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2013-03-11 14:49:53 +08:00
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__weak int arch_cpu_init(void)
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{
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return 0;
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}
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2016-09-21 18:18:46 +08:00
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__weak int mach_cpu_init(void)
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|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-03-11 14:49:53 +08:00
|
|
|
/* Get the top of usable RAM */
|
|
|
|
__weak ulong board_get_usable_ram_top(ulong total_size)
|
|
|
|
{
|
2020-05-10 03:21:14 +08:00
|
|
|
#if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0
|
2014-12-24 01:34:49 +08:00
|
|
|
/*
|
2015-04-29 10:25:03 +08:00
|
|
|
* Detect whether we have so much RAM that it goes past the end of our
|
2014-12-24 01:34:49 +08:00
|
|
|
* 32-bit address space. If so, clip the usable RAM so it doesn't.
|
|
|
|
*/
|
|
|
|
if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
|
|
|
|
/*
|
|
|
|
* Will wrap back to top of 32-bit space when reservations
|
|
|
|
* are made.
|
|
|
|
*/
|
|
|
|
return 0;
|
|
|
|
#endif
|
2013-03-11 14:49:53 +08:00
|
|
|
return gd->ram_top;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int setup_dest_addr(void)
|
|
|
|
{
|
|
|
|
debug("Monitor len: %08lX\n", gd->mon_len);
|
|
|
|
/*
|
|
|
|
* Ram is setup, size stored in gd !!
|
|
|
|
*/
|
|
|
|
debug("Ram size: %08lX\n", (ulong)gd->ram_size);
|
2017-03-07 01:02:28 +08:00
|
|
|
#if defined(CONFIG_SYS_MEM_TOP_HIDE)
|
2013-03-11 14:49:53 +08:00
|
|
|
/*
|
|
|
|
* Subtract specified amount of memory to hide so that it won't
|
|
|
|
* get "touched" at all by U-Boot. By fixing up gd->ram_size
|
|
|
|
* the Linux kernel should now get passed the now "corrected"
|
2017-03-07 01:02:28 +08:00
|
|
|
* memory size and won't touch it either. This should work
|
|
|
|
* for arch/ppc and arch/powerpc. Only Linux board ports in
|
|
|
|
* arch/powerpc with bootwrapper support, that recalculate the
|
|
|
|
* memory size from the SDRAM controller setup will have to
|
|
|
|
* get fixed.
|
2013-03-11 14:49:53 +08:00
|
|
|
*/
|
2017-03-07 01:02:28 +08:00
|
|
|
gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
|
|
|
|
#endif
|
2013-03-11 14:49:53 +08:00
|
|
|
#ifdef CONFIG_SYS_SDRAM_BASE
|
2018-07-16 18:26:10 +08:00
|
|
|
gd->ram_base = CONFIG_SYS_SDRAM_BASE;
|
2013-03-11 14:49:53 +08:00
|
|
|
#endif
|
2018-07-16 18:26:10 +08:00
|
|
|
gd->ram_top = gd->ram_base + get_effective_memsize();
|
2013-03-11 14:49:53 +08:00
|
|
|
gd->ram_top = board_get_usable_ram_top(gd->mon_len);
|
2013-05-27 08:37:30 +08:00
|
|
|
gd->relocaddr = gd->ram_top;
|
2013-03-11 14:49:53 +08:00
|
|
|
debug("Ram top: %08lX\n", (ulong)gd->ram_top);
|
2014-09-04 04:57:54 +08:00
|
|
|
#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
|
2013-03-11 22:30:42 +08:00
|
|
|
/*
|
|
|
|
* We need to make sure the location we intend to put secondary core
|
|
|
|
* boot code is reserved and not used by any part of u-boot
|
|
|
|
*/
|
2013-05-27 08:37:30 +08:00
|
|
|
if (gd->relocaddr > determine_mp_bootpg(NULL)) {
|
|
|
|
gd->relocaddr = determine_mp_bootpg(NULL);
|
|
|
|
debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
|
2013-03-11 22:30:42 +08:00
|
|
|
}
|
|
|
|
#endif
|
2013-03-11 14:49:53 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_PRAM
|
|
|
|
/* reserve protected RAM */
|
|
|
|
static int reserve_pram(void)
|
|
|
|
{
|
|
|
|
ulong reg;
|
|
|
|
|
2017-08-04 02:22:13 +08:00
|
|
|
reg = env_get_ulong("pram", 10, CONFIG_PRAM);
|
2013-05-27 08:37:30 +08:00
|
|
|
gd->relocaddr -= (reg << 10); /* size is in kB */
|
2013-03-11 14:49:53 +08:00
|
|
|
debug("Reserving %ldk for protected RAM at %08lx\n", reg,
|
2013-05-27 08:37:30 +08:00
|
|
|
gd->relocaddr);
|
2013-03-11 14:49:53 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PRAM */
|
|
|
|
|
|
|
|
/* Round memory pointer down to next 4 kB limit */
|
|
|
|
static int reserve_round_4k(void)
|
|
|
|
{
|
2013-05-27 08:37:30 +08:00
|
|
|
gd->relocaddr &= ~(4096 - 1);
|
2013-03-11 14:49:53 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-03-30 01:57:41 +08:00
|
|
|
__weak int arch_reserve_mmu(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-01-19 10:52:21 +08:00
|
|
|
static int reserve_video(void)
|
|
|
|
{
|
2017-03-31 22:40:30 +08:00
|
|
|
#ifdef CONFIG_DM_VIDEO
|
2016-01-19 10:52:21 +08:00
|
|
|
ulong addr;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
addr = gd->relocaddr;
|
|
|
|
ret = video_reserve(&addr);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2020-09-28 08:46:22 +08:00
|
|
|
debug("Reserving %luk for video at: %08lx\n",
|
2021-04-10 00:02:06 +08:00
|
|
|
((unsigned long)gd->relocaddr - addr) >> 10, addr);
|
2016-01-19 10:52:21 +08:00
|
|
|
gd->relocaddr = addr;
|
2017-03-31 22:40:30 +08:00
|
|
|
#elif defined(CONFIG_LCD)
|
2016-01-19 10:52:21 +08:00
|
|
|
# ifdef CONFIG_FB_ADDR
|
2013-03-11 14:49:53 +08:00
|
|
|
gd->fb_base = CONFIG_FB_ADDR;
|
2016-01-19 10:52:21 +08:00
|
|
|
# else
|
2013-03-11 14:49:53 +08:00
|
|
|
/* reserve memory for LCD display (always full pages) */
|
2013-05-27 08:37:30 +08:00
|
|
|
gd->relocaddr = lcd_setmem(gd->relocaddr);
|
|
|
|
gd->fb_base = gd->relocaddr;
|
2016-01-19 10:52:21 +08:00
|
|
|
# endif /* CONFIG_FB_ADDR */
|
2017-03-31 22:40:30 +08:00
|
|
|
#endif
|
2013-03-11 22:30:42 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-01-19 10:52:20 +08:00
|
|
|
static int reserve_trace(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_TRACE
|
|
|
|
gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
|
|
|
|
gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
|
2019-06-15 03:52:22 +08:00
|
|
|
debug("Reserving %luk for trace data at: %08lx\n",
|
|
|
|
(unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
|
2016-01-19 10:52:20 +08:00
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-03-11 14:49:53 +08:00
|
|
|
static int reserve_uboot(void)
|
|
|
|
{
|
2018-05-25 21:08:14 +08:00
|
|
|
if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
|
|
|
|
/*
|
|
|
|
* reserve memory for U-Boot code, data & bss
|
|
|
|
* round down to next 4 kB limit
|
|
|
|
*/
|
|
|
|
gd->relocaddr -= gd->mon_len;
|
|
|
|
gd->relocaddr &= ~(4096 - 1);
|
|
|
|
#if defined(CONFIG_E500) || defined(CONFIG_MIPS)
|
|
|
|
/* round down to next 64 kB limit so that IVPR stays aligned */
|
|
|
|
gd->relocaddr &= ~(65536 - 1);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
debug("Reserving %ldk for U-Boot at: %08lx\n",
|
|
|
|
gd->mon_len >> 10, gd->relocaddr);
|
|
|
|
}
|
2013-05-27 08:37:30 +08:00
|
|
|
|
|
|
|
gd->start_addr_sp = gd->relocaddr;
|
|
|
|
|
2013-03-11 14:49:53 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-03-10 17:15:05 +08:00
|
|
|
/*
|
|
|
|
* reserve after start_addr_sp the requested size and make the stack pointer
|
|
|
|
* 16-byte aligned, this alignment is needed for cast on the reserved memory
|
|
|
|
* ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes
|
|
|
|
* = ARMv8 Instruction Set Overview: quad word, 16 bytes
|
|
|
|
*/
|
|
|
|
static unsigned long reserve_stack_aligned(size_t size)
|
|
|
|
{
|
|
|
|
return ALIGN_DOWN(gd->start_addr_sp - size, 16);
|
|
|
|
}
|
|
|
|
|
2019-08-17 00:57:44 +08:00
|
|
|
#ifdef CONFIG_SYS_NONCACHED_MEMORY
|
|
|
|
static int reserve_noncached(void)
|
|
|
|
{
|
2019-08-28 01:54:31 +08:00
|
|
|
/*
|
|
|
|
* The value of gd->start_addr_sp must match the value of malloc_start
|
|
|
|
* calculated in boatrd_f.c:initr_malloc(), which is passed to
|
|
|
|
* board_r.c:mem_malloc_init() and then used by
|
|
|
|
* cache.c:noncached_init()
|
|
|
|
*
|
|
|
|
* These calculations must match the code in cache.c:noncached_init()
|
|
|
|
*/
|
|
|
|
gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
|
|
|
|
MMU_SECTION_SIZE;
|
|
|
|
gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
|
|
|
|
MMU_SECTION_SIZE);
|
2019-08-17 00:57:44 +08:00
|
|
|
debug("Reserving %dM for noncached_alloc() at: %08lx\n",
|
|
|
|
CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-03-11 14:49:53 +08:00
|
|
|
/* reserve memory for malloc() area */
|
|
|
|
static int reserve_malloc(void)
|
|
|
|
{
|
2020-03-10 17:15:05 +08:00
|
|
|
gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN);
|
2013-03-11 14:49:53 +08:00
|
|
|
debug("Reserving %dk for malloc() at: %08lx\n",
|
2018-01-15 18:10:02 +08:00
|
|
|
TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
|
2019-08-17 00:57:44 +08:00
|
|
|
#ifdef CONFIG_SYS_NONCACHED_MEMORY
|
|
|
|
reserve_noncached();
|
|
|
|
#endif
|
|
|
|
|
2013-03-11 14:49:53 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* (permanently) allocate a Board Info struct */
|
|
|
|
static int reserve_board(void)
|
|
|
|
{
|
2014-07-17 19:01:34 +08:00
|
|
|
if (!gd->bd) {
|
2020-06-26 14:13:33 +08:00
|
|
|
gd->start_addr_sp = reserve_stack_aligned(sizeof(struct bd_info));
|
|
|
|
gd->bd = (struct bd_info *)map_sysmem(gd->start_addr_sp,
|
|
|
|
sizeof(struct bd_info));
|
|
|
|
memset(gd->bd, '\0', sizeof(struct bd_info));
|
2014-07-17 19:01:34 +08:00
|
|
|
debug("Reserving %zu Bytes for Board Info at: %08lx\n",
|
2020-06-26 14:13:33 +08:00
|
|
|
sizeof(struct bd_info), gd->start_addr_sp);
|
2014-07-17 19:01:34 +08:00
|
|
|
}
|
2013-03-11 14:49:53 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int reserve_global_data(void)
|
|
|
|
{
|
2020-03-10 17:15:05 +08:00
|
|
|
gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t));
|
2013-05-27 08:37:30 +08:00
|
|
|
gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
|
2013-03-11 14:49:53 +08:00
|
|
|
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
|
2018-01-15 18:10:02 +08:00
|
|
|
sizeof(gd_t), gd->start_addr_sp);
|
2013-03-11 14:49:53 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int reserve_fdt(void)
|
|
|
|
{
|
2020-11-28 16:43:07 +08:00
|
|
|
if (!IS_ENABLED(CONFIG_OF_EMBED)) {
|
|
|
|
/*
|
|
|
|
* If the device tree is sitting immediately above our image
|
|
|
|
* then we must relocate it. If it is embedded in the data
|
|
|
|
* section, then it will be relocated with other data.
|
|
|
|
*/
|
|
|
|
if (gd->fdt_blob) {
|
|
|
|
gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32);
|
|
|
|
|
|
|
|
gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
|
|
|
|
gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
|
|
|
|
debug("Reserving %lu Bytes for FDT at: %08lx\n",
|
|
|
|
gd->fdt_size, gd->start_addr_sp);
|
|
|
|
}
|
2013-03-11 14:49:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-05-22 19:05:30 +08:00
|
|
|
static int reserve_bootstage(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_BOOTSTAGE
|
|
|
|
int size = bootstage_get_size();
|
|
|
|
|
2020-03-10 17:15:05 +08:00
|
|
|
gd->start_addr_sp = reserve_stack_aligned(size);
|
2017-05-22 19:05:30 +08:00
|
|
|
gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
|
|
|
|
debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
|
|
|
|
gd->start_addr_sp);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-03-13 20:57:00 +08:00
|
|
|
__weak int arch_reserve_stacks(void)
|
2013-03-11 14:49:53 +08:00
|
|
|
{
|
2015-02-07 06:06:45 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2013-03-05 22:39:45 +08:00
|
|
|
|
2015-02-07 06:06:45 +08:00
|
|
|
static int reserve_stacks(void)
|
|
|
|
{
|
|
|
|
/* make stack pointer 16-byte aligned */
|
2020-03-10 17:15:05 +08:00
|
|
|
gd->start_addr_sp = reserve_stack_aligned(16);
|
2013-03-11 14:49:53 +08:00
|
|
|
|
|
|
|
/*
|
2015-04-29 10:25:03 +08:00
|
|
|
* let the architecture-specific code tailor gd->start_addr_sp and
|
2015-02-07 06:06:45 +08:00
|
|
|
* gd->irq_sp
|
2013-03-11 14:49:53 +08:00
|
|
|
*/
|
2015-02-07 06:06:45 +08:00
|
|
|
return arch_reserve_stacks();
|
2013-03-11 14:49:53 +08:00
|
|
|
}
|
|
|
|
|
2018-11-16 09:43:52 +08:00
|
|
|
static int reserve_bloblist(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_BLOBLIST
|
2020-09-28 08:46:18 +08:00
|
|
|
/* Align to a 4KB boundary for easier reading of addresses */
|
2021-01-14 11:29:43 +08:00
|
|
|
gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp -
|
|
|
|
CONFIG_BLOBLIST_SIZE_RELOC, 0x1000);
|
|
|
|
gd->new_bloblist = map_sysmem(gd->start_addr_sp,
|
|
|
|
CONFIG_BLOBLIST_SIZE_RELOC);
|
2018-11-16 09:43:52 +08:00
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-03-11 14:49:53 +08:00
|
|
|
static int display_new_sp(void)
|
|
|
|
{
|
2013-05-27 08:37:30 +08:00
|
|
|
debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
|
2013-03-11 14:49:53 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-07-24 19:12:15 +08:00
|
|
|
__weak int arch_setup_bdinfo(void)
|
2020-07-24 19:12:14 +08:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-07-24 19:12:15 +08:00
|
|
|
int setup_bdinfo(void)
|
|
|
|
{
|
2020-07-24 19:12:16 +08:00
|
|
|
struct bd_info *bd = gd->bd;
|
|
|
|
|
2020-07-24 19:12:17 +08:00
|
|
|
if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
|
|
|
|
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
|
|
|
|
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
|
|
|
|
}
|
|
|
|
|
2020-11-28 16:43:06 +08:00
|
|
|
#ifdef CONFIG_MACH_TYPE
|
|
|
|
bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
|
|
|
|
#endif
|
|
|
|
|
2020-07-24 19:12:15 +08:00
|
|
|
return arch_setup_bdinfo();
|
|
|
|
}
|
|
|
|
|
2013-03-11 14:49:53 +08:00
|
|
|
#ifdef CONFIG_POST
|
|
|
|
static int init_post(void)
|
|
|
|
{
|
|
|
|
post_bootmode_init();
|
|
|
|
post_run(NULL, POST_ROM | post_bootmode_get(0));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static int reloc_fdt(void)
|
|
|
|
{
|
2020-11-28 16:43:07 +08:00
|
|
|
if (!IS_ENABLED(CONFIG_OF_EMBED)) {
|
|
|
|
if (gd->flags & GD_FLG_SKIP_RELOC)
|
|
|
|
return 0;
|
|
|
|
if (gd->new_fdt) {
|
|
|
|
memcpy(gd->new_fdt, gd->fdt_blob,
|
|
|
|
fdt_totalsize(gd->fdt_blob));
|
|
|
|
gd->fdt_blob = gd->new_fdt;
|
|
|
|
}
|
2013-03-11 14:49:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-05-22 19:05:30 +08:00
|
|
|
static int reloc_bootstage(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_BOOTSTAGE
|
|
|
|
if (gd->flags & GD_FLG_SKIP_RELOC)
|
|
|
|
return 0;
|
|
|
|
if (gd->new_bootstage) {
|
|
|
|
int size = bootstage_get_size();
|
|
|
|
|
|
|
|
debug("Copying bootstage from %p to %p, size %x\n",
|
|
|
|
gd->bootstage, gd->new_bootstage, size);
|
|
|
|
memcpy(gd->new_bootstage, gd->bootstage, size);
|
|
|
|
gd->bootstage = gd->new_bootstage;
|
2019-10-22 07:26:50 +08:00
|
|
|
bootstage_relocate();
|
2017-05-22 19:05:30 +08:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-11-16 09:43:52 +08:00
|
|
|
static int reloc_bloblist(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_BLOBLIST
|
|
|
|
if (gd->flags & GD_FLG_SKIP_RELOC)
|
|
|
|
return 0;
|
|
|
|
if (gd->new_bloblist) {
|
|
|
|
int size = CONFIG_BLOBLIST_SIZE;
|
|
|
|
|
|
|
|
debug("Copying bloblist from %p to %p, size %x\n",
|
|
|
|
gd->bloblist, gd->new_bloblist, size);
|
2021-01-14 11:29:43 +08:00
|
|
|
bloblist_reloc(gd->new_bloblist, CONFIG_BLOBLIST_SIZE_RELOC,
|
|
|
|
gd->bloblist, size);
|
2018-11-16 09:43:52 +08:00
|
|
|
gd->bloblist = gd->new_bloblist;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-03-11 14:49:53 +08:00
|
|
|
static int setup_reloc(void)
|
|
|
|
{
|
2021-11-14 01:34:04 +08:00
|
|
|
if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
|
2014-07-17 19:01:34 +08:00
|
|
|
#ifdef CONFIG_SYS_TEXT_BASE
|
2017-06-08 16:18:25 +08:00
|
|
|
#ifdef ARM
|
2021-11-14 01:34:04 +08:00
|
|
|
gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
|
2017-06-08 16:18:25 +08:00
|
|
|
#elif defined(CONFIG_M68K)
|
2021-11-14 01:34:04 +08:00
|
|
|
/*
|
|
|
|
* On all ColdFire arch cpu, monitor code starts always
|
|
|
|
* just after the default vector table location, so at 0x400
|
|
|
|
*/
|
|
|
|
gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
|
2019-04-09 03:20:41 +08:00
|
|
|
#elif !defined(CONFIG_SANDBOX)
|
2021-11-14 01:34:04 +08:00
|
|
|
gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
|
2015-02-12 08:40:17 +08:00
|
|
|
#endif
|
2014-07-17 19:01:34 +08:00
|
|
|
#endif
|
2021-11-14 01:34:04 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 14:49:53 +08:00
|
|
|
memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
|
|
|
|
|
2021-11-14 01:34:04 +08:00
|
|
|
if (gd->flags & GD_FLG_SKIP_RELOC) {
|
|
|
|
debug("Skipping relocation due to flag\n");
|
|
|
|
} else {
|
|
|
|
debug("Relocation Offset is: %08lx\n", gd->reloc_off);
|
|
|
|
debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
|
|
|
|
gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
|
|
|
|
gd->start_addr_sp);
|
|
|
|
}
|
2013-03-11 14:49:53 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
dm: Add callback to modify the device tree
Certain boards come in different variations by way of utilizing daughter
boards, for example. These boards might contain additional chips, which
are added to the main board's busses, e.g. I2C.
The device tree support for such boards would either, quite naturally,
employ the overlay mechanism to add such chips to the tree, or would use
one large default device tree, and delete the devices that are actually
not present.
Regardless of approach, even on the U-Boot level, a modification of the
device tree is a prerequisite to have such modular families of boards
supported properly.
Therefore, we add an option to make the U-Boot device tree (the actual
copy later used by the driver model) writeable, and add a callback
method that allows boards to modify the device tree at an early stage,
at which, hopefully, also the application of device tree overlays will
be possible.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-02-22 23:07:22 +08:00
|
|
|
#ifdef CONFIG_OF_BOARD_FIXUP
|
|
|
|
static int fix_fdt(void)
|
|
|
|
{
|
|
|
|
return board_fix_fdt((void *)gd->fdt_blob);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-03-11 14:49:53 +08:00
|
|
|
/* ARM calls relocate_code from its crt0.S */
|
2017-01-16 22:03:49 +08:00
|
|
|
#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
|
|
|
|
!CONFIG_IS_ENABLED(X86_64)
|
2013-03-11 14:49:53 +08:00
|
|
|
|
|
|
|
static int jump_to_copy(void)
|
|
|
|
{
|
2015-08-05 02:33:39 +08:00
|
|
|
if (gd->flags & GD_FLG_SKIP_RELOC)
|
|
|
|
return 0;
|
2013-03-05 22:39:52 +08:00
|
|
|
/*
|
|
|
|
* x86 is special, but in a nice way. It uses a trampoline which
|
|
|
|
* enables the dcache if possible.
|
|
|
|
*
|
|
|
|
* For now, other archs use relocate_code(), which is implemented
|
|
|
|
* similarly for all archs. When we do generic relocation, hopefully
|
|
|
|
* we can make all archs enable the dcache prior to relocation.
|
|
|
|
*/
|
2015-02-25 00:40:36 +08:00
|
|
|
#if defined(CONFIG_X86) || defined(CONFIG_ARC)
|
2013-03-05 22:39:52 +08:00
|
|
|
/*
|
|
|
|
* SDRAM and console are now initialised. The final stack can now
|
|
|
|
* be setup in SDRAM. Code execution will continue in Flash, but
|
|
|
|
* with the stack in SDRAM and Global Data in temporary memory
|
|
|
|
* (CPU cache)
|
|
|
|
*/
|
2015-08-11 10:44:32 +08:00
|
|
|
arch_setup_gd(gd->new_gd);
|
2013-03-05 22:39:52 +08:00
|
|
|
board_init_f_r_trampoline(gd->start_addr_sp);
|
|
|
|
#else
|
2013-05-27 08:37:30 +08:00
|
|
|
relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
|
2013-03-05 22:39:52 +08:00
|
|
|
#endif
|
2013-03-11 14:49:53 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Record the board_init_f() bootstage (after arch_cpu_init()) */
|
2017-05-22 19:05:25 +08:00
|
|
|
static int initf_bootstage(void)
|
2013-03-11 14:49:53 +08:00
|
|
|
{
|
2017-06-08 00:28:46 +08:00
|
|
|
bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
|
|
|
|
IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
|
2017-05-22 19:05:25 +08:00
|
|
|
int ret;
|
|
|
|
|
2017-05-22 19:05:35 +08:00
|
|
|
ret = bootstage_init(!from_spl);
|
2017-05-22 19:05:25 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2017-05-22 19:05:35 +08:00
|
|
|
if (from_spl) {
|
|
|
|
const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
|
|
|
|
CONFIG_BOOTSTAGE_STASH_SIZE);
|
|
|
|
|
|
|
|
ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
|
|
|
|
if (ret && ret != -ENOENT) {
|
|
|
|
debug("Failed to unstash bootstage: err=%d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
2017-05-22 19:05:25 +08:00
|
|
|
|
2013-03-11 14:49:53 +08:00
|
|
|
bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-07-23 20:55:04 +08:00
|
|
|
static int initf_dm(void)
|
|
|
|
{
|
2017-07-24 17:43:34 +08:00
|
|
|
#if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
|
2014-07-23 20:55:04 +08:00
|
|
|
int ret;
|
|
|
|
|
2020-05-11 01:39:59 +08:00
|
|
|
bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f");
|
2014-07-23 20:55:04 +08:00
|
|
|
ret = dm_init_and_scan(true);
|
2020-05-11 01:39:59 +08:00
|
|
|
bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_F);
|
2014-07-23 20:55:04 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2020-11-28 16:43:05 +08:00
|
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_TIMER_EARLY)) {
|
|
|
|
ret = dm_timer_init();
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2016-02-25 00:14:50 +08:00
|
|
|
#endif
|
2014-07-23 20:55:04 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-01-20 13:16:12 +08:00
|
|
|
/* Architecture-specific memory reservation */
|
|
|
|
__weak int reserve_arch(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-03-06 03:25:16 +08:00
|
|
|
__weak int arch_cpu_init_dm(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-01-23 04:28:25 +08:00
|
|
|
__weak int checkcpu(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-02-05 14:54:42 +08:00
|
|
|
__weak int clear_bss(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-16 22:03:50 +08:00
|
|
|
static const init_fnc_t init_sequence_f[] = {
|
2013-03-11 14:49:53 +08:00
|
|
|
setup_mon_len,
|
2015-02-28 13:06:34 +08:00
|
|
|
#ifdef CONFIG_OF_CONTROL
|
2015-02-28 13:06:35 +08:00
|
|
|
fdtdec_setup,
|
2015-02-28 13:06:34 +08:00
|
|
|
#endif
|
2019-06-02 06:53:24 +08:00
|
|
|
#ifdef CONFIG_TRACE_EARLY
|
2013-06-12 02:14:42 +08:00
|
|
|
trace_early_init,
|
2014-12-10 07:03:58 +08:00
|
|
|
#endif
|
2014-11-11 09:00:18 +08:00
|
|
|
initf_malloc,
|
2017-12-05 04:48:28 +08:00
|
|
|
log_init,
|
2017-05-22 19:05:31 +08:00
|
|
|
initf_bootstage, /* uses its own timer, so does not need DM */
|
2018-11-16 09:43:52 +08:00
|
|
|
#ifdef CONFIG_BLOBLIST
|
|
|
|
bloblist_init,
|
|
|
|
#endif
|
2018-11-16 09:44:09 +08:00
|
|
|
setup_spl_handoff,
|
2020-11-28 16:43:04 +08:00
|
|
|
#if defined(CONFIG_CONSOLE_RECORD_INIT_F)
|
|
|
|
console_record_init,
|
|
|
|
#endif
|
2017-03-29 00:27:18 +08:00
|
|
|
#if defined(CONFIG_HAVE_FSP)
|
|
|
|
arch_fsp_init,
|
2013-03-11 22:30:42 +08:00
|
|
|
#endif
|
2013-03-11 14:49:53 +08:00
|
|
|
arch_cpu_init, /* basic arch cpu dependent setup */
|
2016-09-21 18:18:46 +08:00
|
|
|
mach_cpu_init, /* SoC/machine dependent CPU setup */
|
2014-09-04 07:36:59 +08:00
|
|
|
initf_dm,
|
2015-03-06 03:25:16 +08:00
|
|
|
arch_cpu_init_dm,
|
2013-03-11 14:49:53 +08:00
|
|
|
#if defined(CONFIG_BOARD_EARLY_INIT_F)
|
|
|
|
board_early_init_f,
|
|
|
|
#endif
|
2017-03-29 00:27:26 +08:00
|
|
|
#if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
|
2017-03-29 00:27:19 +08:00
|
|
|
/* get CPU and bus clocks according to the environment variable */
|
2013-03-11 22:30:42 +08:00
|
|
|
get_clocks, /* get CPU and bus clocks (etc.) */
|
2017-03-29 00:27:23 +08:00
|
|
|
#endif
|
2017-05-11 05:58:06 +08:00
|
|
|
#if !defined(CONFIG_M68K)
|
2013-03-11 14:49:53 +08:00
|
|
|
timer_init, /* initialize timer */
|
2017-05-11 05:58:06 +08:00
|
|
|
#endif
|
2013-03-11 22:30:42 +08:00
|
|
|
#if defined(CONFIG_BOARD_POSTCLK_INIT)
|
|
|
|
board_postclk_init,
|
2013-03-11 14:49:53 +08:00
|
|
|
#endif
|
|
|
|
env_init, /* initialize environment */
|
|
|
|
init_baud_rate, /* initialze baudrate settings */
|
|
|
|
serial_init, /* serial communications setup */
|
|
|
|
console_init_f, /* stage 1 init of console */
|
|
|
|
display_options, /* say that we are here */
|
|
|
|
display_text_info, /* show debugging info if required */
|
2013-03-11 22:30:42 +08:00
|
|
|
checkcpu,
|
2018-08-06 16:23:34 +08:00
|
|
|
#if defined(CONFIG_SYSRESET)
|
|
|
|
print_resetinfo,
|
|
|
|
#endif
|
2017-01-24 04:31:25 +08:00
|
|
|
#if defined(CONFIG_DISPLAY_CPUINFO)
|
2013-03-11 14:49:53 +08:00
|
|
|
print_cpuinfo, /* display cpu info (and speed) */
|
2017-01-24 04:31:25 +08:00
|
|
|
#endif
|
2017-06-17 06:25:12 +08:00
|
|
|
#if defined(CONFIG_DTB_RESELECT)
|
|
|
|
embedded_dtb_select,
|
|
|
|
#endif
|
2013-03-11 14:49:53 +08:00
|
|
|
#if defined(CONFIG_DISPLAY_BOARDINFO)
|
2015-01-14 16:07:05 +08:00
|
|
|
show_board_info,
|
2013-03-11 22:30:42 +08:00
|
|
|
#endif
|
|
|
|
INIT_FUNC_WATCHDOG_INIT
|
|
|
|
#if defined(CONFIG_MISC_INIT_F)
|
|
|
|
misc_init_f,
|
|
|
|
#endif
|
|
|
|
INIT_FUNC_WATCHDOG_RESET
|
2021-08-19 11:12:24 +08:00
|
|
|
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
|
2013-03-11 22:30:42 +08:00
|
|
|
init_func_i2c,
|
|
|
|
#endif
|
2018-01-17 18:43:08 +08:00
|
|
|
#if defined(CONFIG_VID) && !defined(CONFIG_SPL)
|
|
|
|
init_func_vid,
|
2013-03-11 14:49:53 +08:00
|
|
|
#endif
|
|
|
|
announce_dram_init,
|
|
|
|
dram_init, /* configure available RAM banks */
|
2013-03-11 22:30:42 +08:00
|
|
|
#ifdef CONFIG_POST
|
|
|
|
post_init_f,
|
|
|
|
#endif
|
|
|
|
INIT_FUNC_WATCHDOG_RESET
|
|
|
|
#if defined(CONFIG_SYS_DRAM_TEST)
|
|
|
|
testdram,
|
|
|
|
#endif /* CONFIG_SYS_DRAM_TEST */
|
|
|
|
INIT_FUNC_WATCHDOG_RESET
|
|
|
|
|
2013-03-11 14:49:53 +08:00
|
|
|
#ifdef CONFIG_POST
|
|
|
|
init_post,
|
|
|
|
#endif
|
2013-03-11 22:30:42 +08:00
|
|
|
INIT_FUNC_WATCHDOG_RESET
|
2013-03-11 14:49:53 +08:00
|
|
|
/*
|
|
|
|
* Now that we have DRAM mapped and working, we can
|
|
|
|
* relocate the code and continue running from DRAM.
|
|
|
|
*
|
|
|
|
* Reserve memory at end of RAM for (top down in that order):
|
|
|
|
* - area that won't get touched by U-Boot and Linux (optional)
|
|
|
|
* - kernel log buffer
|
|
|
|
* - protected RAM
|
|
|
|
* - LCD framebuffer
|
|
|
|
* - monitor code
|
|
|
|
* - board info struct
|
|
|
|
*/
|
|
|
|
setup_dest_addr,
|
2020-08-13 12:42:26 +08:00
|
|
|
#ifdef CONFIG_OF_BOARD_FIXUP
|
|
|
|
fix_fdt,
|
|
|
|
#endif
|
2013-03-11 14:49:53 +08:00
|
|
|
#ifdef CONFIG_PRAM
|
|
|
|
reserve_pram,
|
|
|
|
#endif
|
|
|
|
reserve_round_4k,
|
2020-03-30 01:57:41 +08:00
|
|
|
arch_reserve_mmu,
|
2016-01-19 10:52:21 +08:00
|
|
|
reserve_video,
|
2016-01-19 10:52:20 +08:00
|
|
|
reserve_trace,
|
2013-03-11 14:49:53 +08:00
|
|
|
reserve_uboot,
|
|
|
|
reserve_malloc,
|
|
|
|
reserve_board,
|
|
|
|
reserve_global_data,
|
|
|
|
reserve_fdt,
|
2017-05-22 19:05:30 +08:00
|
|
|
reserve_bootstage,
|
2018-11-16 09:43:52 +08:00
|
|
|
reserve_bloblist,
|
2015-01-20 13:16:12 +08:00
|
|
|
reserve_arch,
|
2013-03-11 14:49:53 +08:00
|
|
|
reserve_stacks,
|
2017-03-31 22:40:32 +08:00
|
|
|
dram_init_banksize,
|
2013-03-11 14:49:53 +08:00
|
|
|
show_dram_config,
|
2013-03-11 22:30:42 +08:00
|
|
|
INIT_FUNC_WATCHDOG_RESET
|
2020-07-24 19:12:20 +08:00
|
|
|
setup_bdinfo,
|
2013-03-11 14:49:53 +08:00
|
|
|
display_new_sp,
|
2013-03-11 22:30:42 +08:00
|
|
|
INIT_FUNC_WATCHDOG_RESET
|
2013-03-11 14:49:53 +08:00
|
|
|
reloc_fdt,
|
2017-05-22 19:05:30 +08:00
|
|
|
reloc_bootstage,
|
2018-11-16 09:43:52 +08:00
|
|
|
reloc_bloblist,
|
2013-03-11 14:49:53 +08:00
|
|
|
setup_reloc,
|
2015-02-25 00:40:36 +08:00
|
|
|
#if defined(CONFIG_X86) || defined(CONFIG_ARC)
|
2015-01-02 07:18:09 +08:00
|
|
|
copy_uboot_to_ram,
|
|
|
|
do_elf_reloc_fixups,
|
|
|
|
#endif
|
2016-08-10 23:36:43 +08:00
|
|
|
clear_bss,
|
2017-01-16 22:03:49 +08:00
|
|
|
#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
|
|
|
|
!CONFIG_IS_ENABLED(X86_64)
|
2013-03-11 14:49:53 +08:00
|
|
|
jump_to_copy,
|
|
|
|
#endif
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
void board_init_f(ulong boot_flags)
|
|
|
|
{
|
|
|
|
gd->flags = boot_flags;
|
2013-11-28 02:32:40 +08:00
|
|
|
gd->have_console = 0;
|
2013-03-11 14:49:53 +08:00
|
|
|
|
|
|
|
if (initcall_run_list(init_sequence_f))
|
|
|
|
hang();
|
|
|
|
|
2015-07-31 23:31:37 +08:00
|
|
|
#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
|
2015-12-17 00:24:10 +08:00
|
|
|
!defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
|
|
|
|
!defined(CONFIG_ARC)
|
2013-03-11 14:49:53 +08:00
|
|
|
/* NOTREACHED - jump_to_copy() does not return */
|
|
|
|
hang();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2015-02-25 00:40:36 +08:00
|
|
|
#if defined(CONFIG_X86) || defined(CONFIG_ARC)
|
2013-03-05 22:39:52 +08:00
|
|
|
/*
|
|
|
|
* For now this code is only used on x86.
|
|
|
|
*
|
|
|
|
* init_sequence_f_r is the list of init functions which are run when
|
|
|
|
* U-Boot is executing from Flash with a semi-limited 'C' environment.
|
|
|
|
* The following limitations must be considered when implementing an
|
|
|
|
* '_f_r' function:
|
|
|
|
* - 'static' variables are read-only
|
|
|
|
* - Global Data (gd->xxx) is read/write
|
|
|
|
*
|
|
|
|
* The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
|
|
|
|
* supported). It _should_, if possible, copy global data to RAM and
|
|
|
|
* initialise the CPU caches (to speed up the relocation process)
|
|
|
|
*
|
|
|
|
* NOTE: At present only x86 uses this route, but it is intended that
|
|
|
|
* all archs will move to this when generic relocation is implemented.
|
|
|
|
*/
|
2017-01-16 22:03:50 +08:00
|
|
|
static const init_fnc_t init_sequence_f_r[] = {
|
2017-01-16 22:03:49 +08:00
|
|
|
#if !CONFIG_IS_ENABLED(X86_64)
|
2013-03-05 22:39:52 +08:00
|
|
|
init_cache_f_r,
|
2017-01-16 22:03:49 +08:00
|
|
|
#endif
|
2013-03-05 22:39:52 +08:00
|
|
|
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
void board_init_f_r(void)
|
|
|
|
{
|
|
|
|
if (initcall_run_list(init_sequence_f_r))
|
|
|
|
hang();
|
|
|
|
|
2016-03-12 13:06:51 +08:00
|
|
|
/*
|
|
|
|
* The pre-relocation drivers may be using memory that has now gone
|
|
|
|
* away. Mark serial as unavailable - this will fall back to the debug
|
|
|
|
* UART if available.
|
2017-12-05 04:48:28 +08:00
|
|
|
*
|
|
|
|
* Do the same with log drivers since the memory may not be available.
|
2016-03-12 13:06:51 +08:00
|
|
|
*/
|
2017-12-05 04:48:28 +08:00
|
|
|
gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
|
2017-09-06 09:49:45 +08:00
|
|
|
#ifdef CONFIG_TIMER
|
|
|
|
gd->timer = NULL;
|
|
|
|
#endif
|
2016-03-12 13:06:51 +08:00
|
|
|
|
2013-03-05 22:39:52 +08:00
|
|
|
/*
|
|
|
|
* U-Boot has been copied into SDRAM, the BSS has been cleared etc.
|
|
|
|
* Transfer execution from Flash to RAM by calculating the address
|
|
|
|
* of the in-RAM copy of board_init_r() and calling it
|
|
|
|
*/
|
2015-02-25 22:59:02 +08:00
|
|
|
(board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
|
2013-03-05 22:39:52 +08:00
|
|
|
|
|
|
|
/* NOTREACHED - board_init_r() does not return */
|
|
|
|
hang();
|
|
|
|
}
|
2015-03-24 16:12:47 +08:00
|
|
|
#endif /* CONFIG_X86 */
|